-------------------------------------------------------------------------------
-- Title      : vga entitiy
-- Project    : LU Digital Design
-------------------------------------------------------------------------------
-- File       : vga_ent.vhd
-- Author     : Thomas Handl
-- Company    : TU Wien
-- Created    : 2004-04-07
-- Last update: 2007-09-13
-------------------------------------------------------------------------------
-- Description: entity of top level module, external pins defined here
-------------------------------------------------------------------------------
-- Copyright (c) 2004 TU Wien
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004-04-07  1.0      handl   Created
-- 2006-02-24  2.0      ST      revised
-------------------------------------------------------------------------------


-------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

use work.vga_pak.all;


-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------

entity vga is
  port(
 input pins from PCB board  
       clk_pin                                  : in  std_logic;         -- clock pin
       reset_pin                                : in  std_logic;         -- reset pins (from switch)
-- output pins to RGB connector / VGA screen
       r0_pin, r1_pin, r2_pin                   : out std_logic;         -- to RGB connector "red"
       g0_pin, g1_pin, g2_pin                   : out std_logic;         -- to RGB connector "green"
       b0_pin, b1_pin                           : out std_logic;         -- to RGB connector "blue"
       hsync_pin                                : out std_logic;         -- to RGB connector "Hsync"
       vsync_pin                                : out std_logic;         -- to RGB connector "Vsync"
-- output pins to 7-segment display
       seven_seg_pin                                 : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
-- output pins provided for debugging only / logic analyzer
       d_hsync, d_vsync                         : out std_logic;         -- copy of hsync_pin, vsync_pin
       d_column_counter                         : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
       d_line_counter                           : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
       d_set_column_counter, d_set_line_counter : out std_logic;
       d_hsync_counter                          : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
       d_vsync_counter                          : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
       d_set_hsync_counter, d_set_vsync_counter : out std_logic;
       d_h_enable                               : out std_logic;
       d_v_enable                               : out std_logic;
       d_r, d_g, d_b                            : out std_logic;
       d_hsync_state                            : out hsync_state_type;
       d_vsync_state                            : out vsync_state_type;
       d_state_clk                              : out std_logic;
       d_toggle                                 : out std_logic;
       d_toggle_counter                         : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)
       );

end vga;

-------------------------------------------------------------------------------
-- END ENTITY
-------------------------------------------------------------------------------