// // Written by Synplify // Product Version "C-2009.06" // Program "Synplify Pro", Mapper "map450rc, Build 029R" // Thu Oct 29 16:49:33 2009 // // Source file index table: // Object locations will have the form : // file 0 "noname" // file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd " // file 2 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd " // file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd " // file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd " // file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd " // file 6 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd " // file 7 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd " // file 8 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd " // file 9 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd " // file 10 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_arc.vhd " // file 11 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_arc.vhd " // file 12 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd " // file 13 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd " // VQM4.1+ module vga_driver ( line_counter_sig_0, line_counter_sig_1, line_counter_sig_2, line_counter_sig_3, line_counter_sig_4, line_counter_sig_5, line_counter_sig_6, line_counter_sig_7, line_counter_sig_8, dly_counter_1, dly_counter_0, vsync_state_2, vsync_state_5, vsync_state_3, vsync_state_6, vsync_state_4, vsync_state_1, vsync_state_0, hsync_state_2, hsync_state_4, hsync_state_0, hsync_state_5, hsync_state_1, hsync_state_3, hsync_state_6, column_counter_sig_0, column_counter_sig_1, column_counter_sig_2, column_counter_sig_3, column_counter_sig_4, column_counter_sig_5, column_counter_sig_6, column_counter_sig_7, column_counter_sig_8, column_counter_sig_9, vsync_counter_9, vsync_counter_8, vsync_counter_7, vsync_counter_6, vsync_counter_5, vsync_counter_4, vsync_counter_3, vsync_counter_2, vsync_counter_1, vsync_counter_0, hsync_counter_9, hsync_counter_8, hsync_counter_7, hsync_counter_6, hsync_counter_5, hsync_counter_4, hsync_counter_3, hsync_counter_2, hsync_counter_1, hsync_counter_0, d_set_vsync_counter, un10_column_counter_siglt6_1, un10_column_counter_siglt6_3, v_sync, h_sync, h_enable_sig, v_enable_sig, reset_pin_c, un6_dly_counter_0_x, d_set_hsync_counter, clk_pin_c ) ; output line_counter_sig_0 ; output line_counter_sig_1 ; output line_counter_sig_2 ; output line_counter_sig_3 ; output line_counter_sig_4 ; output line_counter_sig_5 ; output line_counter_sig_6 ; output line_counter_sig_7 ; output line_counter_sig_8 ; input dly_counter_1 ; input dly_counter_0 ; output vsync_state_2 ; output vsync_state_5 ; output vsync_state_3 ; output vsync_state_6 ; output vsync_state_4 ; output vsync_state_1 ; output vsync_state_0 ; output hsync_state_2 ; output hsync_state_4 ; output hsync_state_0 ; output hsync_state_5 ; output hsync_state_1 ; output hsync_state_3 ; output hsync_state_6 ; output column_counter_sig_0 ; output column_counter_sig_1 ; output column_counter_sig_2 ; output column_counter_sig_3 ; output column_counter_sig_4 ; output column_counter_sig_5 ; output column_counter_sig_6 ; output column_counter_sig_7 ; output column_counter_sig_8 ; output column_counter_sig_9 ; output vsync_counter_9 ; output vsync_counter_8 ; output vsync_counter_7 ; output vsync_counter_6 ; output vsync_counter_5 ; output vsync_counter_4 ; output vsync_counter_3 ; output vsync_counter_2 ; output vsync_counter_1 ; output vsync_counter_0 ; output hsync_counter_9 ; output hsync_counter_8 ; output hsync_counter_7 ; output hsync_counter_6 ; output hsync_counter_5 ; output hsync_counter_4 ; output hsync_counter_3 ; output hsync_counter_2 ; output hsync_counter_1 ; output hsync_counter_0 ; output d_set_vsync_counter ; output un10_column_counter_siglt6_1 ; output un10_column_counter_siglt6_3 ; output v_sync ; output h_sync ; output h_enable_sig ; output v_enable_sig ; input reset_pin_c ; output un6_dly_counter_0_x ; output d_set_hsync_counter ; input clk_pin_c ; wire line_counter_sig_0 ; wire line_counter_sig_1 ; wire line_counter_sig_2 ; wire line_counter_sig_3 ; wire line_counter_sig_4 ; wire line_counter_sig_5 ; wire line_counter_sig_6 ; wire line_counter_sig_7 ; wire line_counter_sig_8 ; wire dly_counter_1 ; wire dly_counter_0 ; wire vsync_state_2 ; wire vsync_state_5 ; wire vsync_state_3 ; wire vsync_state_6 ; wire vsync_state_4 ; wire vsync_state_1 ; wire vsync_state_0 ; wire hsync_state_2 ; wire hsync_state_4 ; wire hsync_state_0 ; wire hsync_state_5 ; wire hsync_state_1 ; wire hsync_state_3 ; wire hsync_state_6 ; wire column_counter_sig_0 ; wire column_counter_sig_1 ; wire column_counter_sig_2 ; wire column_counter_sig_3 ; wire column_counter_sig_4 ; wire column_counter_sig_5 ; wire column_counter_sig_6 ; wire column_counter_sig_7 ; wire column_counter_sig_8 ; wire column_counter_sig_9 ; wire vsync_counter_9 ; wire vsync_counter_8 ; wire vsync_counter_7 ; wire vsync_counter_6 ; wire vsync_counter_5 ; wire vsync_counter_4 ; wire vsync_counter_3 ; wire vsync_counter_2 ; wire vsync_counter_1 ; wire vsync_counter_0 ; wire hsync_counter_9 ; wire hsync_counter_8 ; wire hsync_counter_7 ; wire hsync_counter_6 ; wire hsync_counter_5 ; wire hsync_counter_4 ; wire hsync_counter_3 ; wire hsync_counter_2 ; wire hsync_counter_1 ; wire hsync_counter_0 ; wire d_set_vsync_counter ; wire un10_column_counter_siglt6_1 ; wire un10_column_counter_siglt6_3 ; wire v_sync ; wire h_sync ; wire h_enable_sig ; wire v_enable_sig ; wire reset_pin_c ; wire un6_dly_counter_0_x ; wire d_set_hsync_counter ; wire clk_pin_c ; wire [8:0] hsync_counter_cout; wire [8:0] vsync_counter_cout; wire [9:1] un2_column_counter_next_combout; wire [9:1] un1_line_counter_sig_combout; wire [7:1] un1_line_counter_sig_cout; wire [1:1] un1_line_counter_sig_a_cout; wire [7:0] un2_column_counter_next_cout; wire hsync_counter_next_1_sqmuxa ; wire G_2_i ; wire un9_hsync_counterlt9 ; wire vsync_counter_next_1_sqmuxa ; wire G_16_i ; wire un9_vsync_counterlt9 ; wire un10_column_counter_siglto9 ; wire column_counter_next_0_sqmuxa_1_1 ; wire vsync_state_3_iv_0_0__g0_0_a3_0 ; wire vsync_state_next_2_sqmuxa ; wire un12_vsync_counter_7 ; wire un13_vsync_counter_4 ; wire un10_line_counter_siglto8 ; wire line_counter_next_0_sqmuxa_1_1 ; wire v_enable_sig_1_0_0_0_g0_i_o4 ; wire h_enable_sig_1_0_0_0_g0_i_o4 ; wire h_sync_1_0_0_0_g1 ; wire v_sync_1_0_0_0_g1 ; wire un14_vsync_counter_8 ; wire hsync_state_3_0_0_0__g0_0 ; wire un10_hsync_counter_3 ; wire un10_hsync_counter_1 ; wire un10_hsync_counter_4 ; wire un12_hsync_counter ; wire un11_hsync_counter_2 ; wire un11_hsync_counter_3 ; wire un13_hsync_counter ; wire vsync_state_next_1_sqmuxa_1 ; wire vsync_state_next_1_sqmuxa_3 ; wire un1_vsync_state_next_1_sqmuxa_0 ; wire hsync_state_next_1_sqmuxa_1 ; wire hsync_state_next_1_sqmuxa_2 ; wire un1_hsync_state_next_1_sqmuxa_0 ; wire un12_vsync_counter_6 ; wire un15_vsync_counter_4 ; wire vsync_state_next_1_sqmuxa_2 ; wire un10_column_counter_siglt6 ; wire un10_line_counter_siglto5 ; wire un9_vsync_counterlt9_5 ; wire un9_vsync_counterlt9_6 ; wire un12_hsync_counter_3 ; wire un12_hsync_counter_4 ; wire un13_hsync_counter_2 ; wire un13_hsync_counter_7 ; wire un9_hsync_counterlt9_3 ; wire un10_line_counter_siglt4_2 ; wire un13_vsync_counter_3 ; wire un15_vsync_counter_3 ; wire un1_vsync_state_2_0 ; wire un1_hsync_state_3_0 ; wire VCC ; wire GND ; wire line_counter_next_0_sqmuxa_1_1_i ; wire column_counter_next_0_sqmuxa_1_1_i ; wire un9_vsync_counterlt9_i ; wire G_16_i_i ; wire un9_hsync_counterlt9_i ; wire G_2_i_i ; //@1:1 assign VCC = 1'b1; assign GND = 1'b0; // @13:158 stratix_lcell hsync_counter_0_ ( .regout(hsync_counter_0), .cout(hsync_counter_cout[0]), .clk(clk_pin_c), .dataa(hsync_counter_0), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_0_.operation_mode="arithmetic"; defparam hsync_counter_0_.output_mode="reg_only"; defparam hsync_counter_0_.lut_mask="55aa"; defparam hsync_counter_0_.synch_mode="on"; defparam hsync_counter_0_.sum_lutc_input="datac"; // @13:158 stratix_lcell hsync_counter_1_ ( .regout(hsync_counter_1), .cout(hsync_counter_cout[1]), .clk(clk_pin_c), .dataa(hsync_counter_1), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[0]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_1_.cin_used="true"; defparam hsync_counter_1_.operation_mode="arithmetic"; defparam hsync_counter_1_.output_mode="reg_only"; defparam hsync_counter_1_.lut_mask="5aa0"; defparam hsync_counter_1_.synch_mode="on"; defparam hsync_counter_1_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_2_ ( .regout(hsync_counter_2), .cout(hsync_counter_cout[2]), .clk(clk_pin_c), .dataa(hsync_counter_2), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[1]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_2_.cin_used="true"; defparam hsync_counter_2_.operation_mode="arithmetic"; defparam hsync_counter_2_.output_mode="reg_only"; defparam hsync_counter_2_.lut_mask="5aa0"; defparam hsync_counter_2_.synch_mode="on"; defparam hsync_counter_2_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_3_ ( .regout(hsync_counter_3), .cout(hsync_counter_cout[3]), .clk(clk_pin_c), .dataa(hsync_counter_3), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[2]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_3_.cin_used="true"; defparam hsync_counter_3_.operation_mode="arithmetic"; defparam hsync_counter_3_.output_mode="reg_only"; defparam hsync_counter_3_.lut_mask="5aa0"; defparam hsync_counter_3_.synch_mode="on"; defparam hsync_counter_3_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_4_ ( .regout(hsync_counter_4), .cout(hsync_counter_cout[4]), .clk(clk_pin_c), .dataa(hsync_counter_4), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[3]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_4_.cin_used="true"; defparam hsync_counter_4_.operation_mode="arithmetic"; defparam hsync_counter_4_.output_mode="reg_only"; defparam hsync_counter_4_.lut_mask="5aa0"; defparam hsync_counter_4_.synch_mode="on"; defparam hsync_counter_4_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_5_ ( .regout(hsync_counter_5), .cout(hsync_counter_cout[5]), .clk(clk_pin_c), .dataa(hsync_counter_5), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[4]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_5_.cin_used="true"; defparam hsync_counter_5_.operation_mode="arithmetic"; defparam hsync_counter_5_.output_mode="reg_only"; defparam hsync_counter_5_.lut_mask="5aa0"; defparam hsync_counter_5_.synch_mode="on"; defparam hsync_counter_5_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_6_ ( .regout(hsync_counter_6), .cout(hsync_counter_cout[6]), .clk(clk_pin_c), .dataa(hsync_counter_6), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[5]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_6_.cin_used="true"; defparam hsync_counter_6_.operation_mode="arithmetic"; defparam hsync_counter_6_.output_mode="reg_only"; defparam hsync_counter_6_.lut_mask="5aa0"; defparam hsync_counter_6_.synch_mode="on"; defparam hsync_counter_6_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_7_ ( .regout(hsync_counter_7), .cout(hsync_counter_cout[7]), .clk(clk_pin_c), .dataa(hsync_counter_7), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[6]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_7_.cin_used="true"; defparam hsync_counter_7_.operation_mode="arithmetic"; defparam hsync_counter_7_.output_mode="reg_only"; defparam hsync_counter_7_.lut_mask="5aa0"; defparam hsync_counter_7_.synch_mode="on"; defparam hsync_counter_7_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_8_ ( .regout(hsync_counter_8), .cout(hsync_counter_cout[8]), .clk(clk_pin_c), .dataa(hsync_counter_8), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[7]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_8_.cin_used="true"; defparam hsync_counter_8_.operation_mode="arithmetic"; defparam hsync_counter_8_.output_mode="reg_only"; defparam hsync_counter_8_.lut_mask="5aa0"; defparam hsync_counter_8_.synch_mode="on"; defparam hsync_counter_8_.sum_lutc_input="cin"; // @13:158 stratix_lcell hsync_counter_9_ ( .regout(hsync_counter_9), .clk(clk_pin_c), .dataa(hsync_counter_9), .datab(VCC), .datac(hsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_2_i_i), .sload(un9_hsync_counterlt9_i), .ena(VCC), .cin(hsync_counter_cout[8]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_9_.cin_used="true"; defparam hsync_counter_9_.operation_mode="normal"; defparam hsync_counter_9_.output_mode="reg_only"; defparam hsync_counter_9_.lut_mask="5a5a"; defparam hsync_counter_9_.synch_mode="on"; defparam hsync_counter_9_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_0_ ( .regout(vsync_counter_0), .cout(vsync_counter_cout[0]), .clk(clk_pin_c), .dataa(vsync_counter_0), .datab(d_set_hsync_counter), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_0_.operation_mode="arithmetic"; defparam vsync_counter_0_.output_mode="reg_only"; defparam vsync_counter_0_.lut_mask="6688"; defparam vsync_counter_0_.synch_mode="on"; defparam vsync_counter_0_.sum_lutc_input="datac"; // @13:267 stratix_lcell vsync_counter_1_ ( .regout(vsync_counter_1), .cout(vsync_counter_cout[1]), .clk(clk_pin_c), .dataa(vsync_counter_1), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[0]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_1_.cin_used="true"; defparam vsync_counter_1_.operation_mode="arithmetic"; defparam vsync_counter_1_.output_mode="reg_only"; defparam vsync_counter_1_.lut_mask="5aa0"; defparam vsync_counter_1_.synch_mode="on"; defparam vsync_counter_1_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_2_ ( .regout(vsync_counter_2), .cout(vsync_counter_cout[2]), .clk(clk_pin_c), .dataa(vsync_counter_2), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[1]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_2_.cin_used="true"; defparam vsync_counter_2_.operation_mode="arithmetic"; defparam vsync_counter_2_.output_mode="reg_only"; defparam vsync_counter_2_.lut_mask="5aa0"; defparam vsync_counter_2_.synch_mode="on"; defparam vsync_counter_2_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_3_ ( .regout(vsync_counter_3), .cout(vsync_counter_cout[3]), .clk(clk_pin_c), .dataa(vsync_counter_3), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[2]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_3_.cin_used="true"; defparam vsync_counter_3_.operation_mode="arithmetic"; defparam vsync_counter_3_.output_mode="reg_only"; defparam vsync_counter_3_.lut_mask="5aa0"; defparam vsync_counter_3_.synch_mode="on"; defparam vsync_counter_3_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_4_ ( .regout(vsync_counter_4), .cout(vsync_counter_cout[4]), .clk(clk_pin_c), .dataa(vsync_counter_4), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[3]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_4_.cin_used="true"; defparam vsync_counter_4_.operation_mode="arithmetic"; defparam vsync_counter_4_.output_mode="reg_only"; defparam vsync_counter_4_.lut_mask="5aa0"; defparam vsync_counter_4_.synch_mode="on"; defparam vsync_counter_4_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_5_ ( .regout(vsync_counter_5), .cout(vsync_counter_cout[5]), .clk(clk_pin_c), .dataa(vsync_counter_5), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[4]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_5_.cin_used="true"; defparam vsync_counter_5_.operation_mode="arithmetic"; defparam vsync_counter_5_.output_mode="reg_only"; defparam vsync_counter_5_.lut_mask="5aa0"; defparam vsync_counter_5_.synch_mode="on"; defparam vsync_counter_5_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_6_ ( .regout(vsync_counter_6), .cout(vsync_counter_cout[6]), .clk(clk_pin_c), .dataa(vsync_counter_6), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[5]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_6_.cin_used="true"; defparam vsync_counter_6_.operation_mode="arithmetic"; defparam vsync_counter_6_.output_mode="reg_only"; defparam vsync_counter_6_.lut_mask="5aa0"; defparam vsync_counter_6_.synch_mode="on"; defparam vsync_counter_6_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_7_ ( .regout(vsync_counter_7), .cout(vsync_counter_cout[7]), .clk(clk_pin_c), .dataa(vsync_counter_7), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[6]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_7_.cin_used="true"; defparam vsync_counter_7_.operation_mode="arithmetic"; defparam vsync_counter_7_.output_mode="reg_only"; defparam vsync_counter_7_.lut_mask="5aa0"; defparam vsync_counter_7_.synch_mode="on"; defparam vsync_counter_7_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_8_ ( .regout(vsync_counter_8), .cout(vsync_counter_cout[8]), .clk(clk_pin_c), .dataa(vsync_counter_8), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[7]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_8_.cin_used="true"; defparam vsync_counter_8_.operation_mode="arithmetic"; defparam vsync_counter_8_.output_mode="reg_only"; defparam vsync_counter_8_.lut_mask="5aa0"; defparam vsync_counter_8_.synch_mode="on"; defparam vsync_counter_8_.sum_lutc_input="cin"; // @13:267 stratix_lcell vsync_counter_9_ ( .regout(vsync_counter_9), .clk(clk_pin_c), .dataa(vsync_counter_9), .datab(VCC), .datac(vsync_counter_next_1_sqmuxa), .datad(VCC), .aclr(GND), .sclr(G_16_i_i), .sload(un9_vsync_counterlt9_i), .ena(VCC), .cin(vsync_counter_cout[8]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_9_.cin_used="true"; defparam vsync_counter_9_.operation_mode="normal"; defparam vsync_counter_9_.output_mode="reg_only"; defparam vsync_counter_9_.lut_mask="5a5a"; defparam vsync_counter_9_.synch_mode="on"; defparam vsync_counter_9_.sum_lutc_input="cin"; // @13:97 stratix_lcell column_counter_sig_9_ ( .regout(column_counter_sig_9), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[9]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_9_.operation_mode="normal"; defparam column_counter_sig_9_.output_mode="reg_only"; defparam column_counter_sig_9_.lut_mask="bbbb"; defparam column_counter_sig_9_.synch_mode="on"; defparam column_counter_sig_9_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_8_ ( .regout(column_counter_sig_8), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[8]), .datab(column_counter_next_0_sqmuxa_1_1), .datac(un10_column_counter_siglto9), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_8_.operation_mode="normal"; defparam column_counter_sig_8_.output_mode="reg_only"; defparam column_counter_sig_8_.lut_mask="8080"; defparam column_counter_sig_8_.synch_mode="off"; defparam column_counter_sig_8_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_7_ ( .regout(column_counter_sig_7), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[7]), .datab(column_counter_next_0_sqmuxa_1_1), .datac(un10_column_counter_siglto9), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_7_.operation_mode="normal"; defparam column_counter_sig_7_.output_mode="reg_only"; defparam column_counter_sig_7_.lut_mask="8080"; defparam column_counter_sig_7_.synch_mode="off"; defparam column_counter_sig_7_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_6_ ( .regout(column_counter_sig_6), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[6]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_6_.operation_mode="normal"; defparam column_counter_sig_6_.output_mode="reg_only"; defparam column_counter_sig_6_.lut_mask="bbbb"; defparam column_counter_sig_6_.synch_mode="on"; defparam column_counter_sig_6_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_5_ ( .regout(column_counter_sig_5), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[5]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_5_.operation_mode="normal"; defparam column_counter_sig_5_.output_mode="reg_only"; defparam column_counter_sig_5_.lut_mask="bbbb"; defparam column_counter_sig_5_.synch_mode="on"; defparam column_counter_sig_5_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_4_ ( .regout(column_counter_sig_4), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[4]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_4_.operation_mode="normal"; defparam column_counter_sig_4_.output_mode="reg_only"; defparam column_counter_sig_4_.lut_mask="bbbb"; defparam column_counter_sig_4_.synch_mode="on"; defparam column_counter_sig_4_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_3_ ( .regout(column_counter_sig_3), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[3]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_3_.operation_mode="normal"; defparam column_counter_sig_3_.output_mode="reg_only"; defparam column_counter_sig_3_.lut_mask="bbbb"; defparam column_counter_sig_3_.synch_mode="on"; defparam column_counter_sig_3_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_2_ ( .regout(column_counter_sig_2), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[2]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_2_.operation_mode="normal"; defparam column_counter_sig_2_.output_mode="reg_only"; defparam column_counter_sig_2_.lut_mask="bbbb"; defparam column_counter_sig_2_.synch_mode="on"; defparam column_counter_sig_2_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_1_ ( .regout(column_counter_sig_1), .clk(clk_pin_c), .dataa(un2_column_counter_next_combout[1]), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_1_.operation_mode="normal"; defparam column_counter_sig_1_.output_mode="reg_only"; defparam column_counter_sig_1_.lut_mask="bbbb"; defparam column_counter_sig_1_.synch_mode="on"; defparam column_counter_sig_1_.sum_lutc_input="datac"; // @13:97 stratix_lcell column_counter_sig_0_ ( .regout(column_counter_sig_0), .clk(clk_pin_c), .dataa(column_counter_sig_0), .datab(un10_column_counter_siglto9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(column_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_sig_0_.operation_mode="normal"; defparam column_counter_sig_0_.output_mode="reg_only"; defparam column_counter_sig_0_.lut_mask="7777"; defparam column_counter_sig_0_.synch_mode="on"; defparam column_counter_sig_0_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_6_ ( .regout(hsync_state_6), .clk(clk_pin_c), .dataa(VCC), .datab(VCC), .datac(VCC), .datad(un6_dly_counter_0_x), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_6_.operation_mode="normal"; defparam hsync_state_6_.output_mode="reg_only"; defparam hsync_state_6_.lut_mask="ff00"; defparam hsync_state_6_.synch_mode="off"; defparam hsync_state_6_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_0_ ( .regout(vsync_state_0), .clk(clk_pin_c), .dataa(vsync_state_0), .datab(un6_dly_counter_0_x), .datac(vsync_state_3_iv_0_0__g0_0_a3_0), .datad(vsync_state_next_2_sqmuxa), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_0_.operation_mode="normal"; defparam vsync_state_0_.output_mode="reg_only"; defparam vsync_state_0_.lut_mask="30ba"; defparam vsync_state_0_.synch_mode="off"; defparam vsync_state_0_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_1_ ( .regout(vsync_state_1), .clk(clk_pin_c), .dataa(vsync_state_4), .datab(un12_vsync_counter_7), .datac(un13_vsync_counter_4), .datad(un6_dly_counter_0_x), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_1_.operation_mode="normal"; defparam vsync_state_1_.output_mode="reg_only"; defparam vsync_state_1_.lut_mask="0080"; defparam vsync_state_1_.synch_mode="off"; defparam vsync_state_1_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_6_ ( .combout(un6_dly_counter_0_x), .regout(vsync_state_6), .clk(clk_pin_c), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_6_.operation_mode="normal"; defparam vsync_state_6_.output_mode="reg_and_comb"; defparam vsync_state_6_.lut_mask="7f7f"; defparam vsync_state_6_.synch_mode="off"; defparam vsync_state_6_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_8_ ( .regout(line_counter_sig_8), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[9]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_8_.operation_mode="normal"; defparam line_counter_sig_8_.output_mode="reg_only"; defparam line_counter_sig_8_.lut_mask="dddd"; defparam line_counter_sig_8_.synch_mode="on"; defparam line_counter_sig_8_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_7_ ( .regout(line_counter_sig_7), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[8]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_7_.operation_mode="normal"; defparam line_counter_sig_7_.output_mode="reg_only"; defparam line_counter_sig_7_.lut_mask="dddd"; defparam line_counter_sig_7_.synch_mode="on"; defparam line_counter_sig_7_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_6_ ( .regout(line_counter_sig_6), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[7]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_6_.operation_mode="normal"; defparam line_counter_sig_6_.output_mode="reg_only"; defparam line_counter_sig_6_.lut_mask="dddd"; defparam line_counter_sig_6_.synch_mode="on"; defparam line_counter_sig_6_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_5_ ( .regout(line_counter_sig_5), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(line_counter_next_0_sqmuxa_1_1), .datac(un1_line_counter_sig_combout[6]), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_5_.operation_mode="normal"; defparam line_counter_sig_5_.output_mode="reg_only"; defparam line_counter_sig_5_.lut_mask="8080"; defparam line_counter_sig_5_.synch_mode="off"; defparam line_counter_sig_5_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_4_ ( .regout(line_counter_sig_4), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[5]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_4_.operation_mode="normal"; defparam line_counter_sig_4_.output_mode="reg_only"; defparam line_counter_sig_4_.lut_mask="dddd"; defparam line_counter_sig_4_.synch_mode="on"; defparam line_counter_sig_4_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_3_ ( .regout(line_counter_sig_3), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[4]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_3_.operation_mode="normal"; defparam line_counter_sig_3_.output_mode="reg_only"; defparam line_counter_sig_3_.lut_mask="dddd"; defparam line_counter_sig_3_.synch_mode="on"; defparam line_counter_sig_3_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_2_ ( .regout(line_counter_sig_2), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[3]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_2_.operation_mode="normal"; defparam line_counter_sig_2_.output_mode="reg_only"; defparam line_counter_sig_2_.lut_mask="dddd"; defparam line_counter_sig_2_.synch_mode="on"; defparam line_counter_sig_2_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_1_ ( .regout(line_counter_sig_1), .clk(clk_pin_c), .dataa(un10_line_counter_siglto8), .datab(un1_line_counter_sig_combout[2]), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_1_.operation_mode="normal"; defparam line_counter_sig_1_.output_mode="reg_only"; defparam line_counter_sig_1_.lut_mask="dddd"; defparam line_counter_sig_1_.synch_mode="on"; defparam line_counter_sig_1_.sum_lutc_input="datac"; // @13:125 stratix_lcell line_counter_sig_0_ ( .regout(line_counter_sig_0), .clk(clk_pin_c), .dataa(un1_line_counter_sig_combout[1]), .datab(un10_line_counter_siglto8), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(line_counter_next_0_sqmuxa_1_1_i), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_sig_0_.operation_mode="normal"; defparam line_counter_sig_0_.output_mode="reg_only"; defparam line_counter_sig_0_.lut_mask="bbbb"; defparam line_counter_sig_0_.synch_mode="on"; defparam line_counter_sig_0_.sum_lutc_input="datac"; // @13:187 stratix_lcell v_enable_sig_Z ( .regout(v_enable_sig), .clk(clk_pin_c), .dataa(hsync_state_3), .datab(hsync_state_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(v_enable_sig_1_0_0_0_g0_i_o4), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam v_enable_sig_Z.operation_mode="normal"; defparam v_enable_sig_Z.output_mode="reg_only"; defparam v_enable_sig_Z.lut_mask="eeee"; defparam v_enable_sig_Z.synch_mode="on"; defparam v_enable_sig_Z.sum_lutc_input="datac"; // @13:300 stratix_lcell h_enable_sig_Z ( .regout(h_enable_sig), .clk(clk_pin_c), .dataa(vsync_state_3), .datab(vsync_state_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(h_enable_sig_1_0_0_0_g0_i_o4), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam h_enable_sig_Z.operation_mode="normal"; defparam h_enable_sig_Z.output_mode="reg_only"; defparam h_enable_sig_Z.lut_mask="eeee"; defparam h_enable_sig_Z.synch_mode="on"; defparam h_enable_sig_Z.sum_lutc_input="datac"; // @13:187 stratix_lcell h_sync_Z ( .regout(h_sync), .clk(clk_pin_c), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(h_sync_1_0_0_0_g1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam h_sync_Z.operation_mode="normal"; defparam h_sync_Z.output_mode="reg_only"; defparam h_sync_Z.lut_mask="ff7f"; defparam h_sync_Z.synch_mode="off"; defparam h_sync_Z.sum_lutc_input="datac"; // @13:300 stratix_lcell v_sync_Z ( .regout(v_sync), .clk(clk_pin_c), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(v_sync_1_0_0_0_g1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam v_sync_Z.operation_mode="normal"; defparam v_sync_Z.output_mode="reg_only"; defparam v_sync_Z.lut_mask="ff7f"; defparam v_sync_Z.synch_mode="off"; defparam v_sync_Z.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_5_ ( .regout(vsync_state_5), .clk(clk_pin_c), .dataa(vsync_state_6), .datab(vsync_state_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(vsync_state_next_2_sqmuxa), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_5_.operation_mode="normal"; defparam vsync_state_5_.output_mode="reg_only"; defparam vsync_state_5_.lut_mask="eeee"; defparam vsync_state_5_.synch_mode="on"; defparam vsync_state_5_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_4_ ( .regout(vsync_state_4), .clk(clk_pin_c), .dataa(vsync_counter_0), .datab(vsync_counter_9), .datac(vsync_state_5), .datad(un14_vsync_counter_8), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(vsync_state_next_2_sqmuxa), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_4_.operation_mode="normal"; defparam vsync_state_4_.output_mode="reg_only"; defparam vsync_state_4_.lut_mask="2000"; defparam vsync_state_4_.synch_mode="on"; defparam vsync_state_4_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_3_ ( .regout(vsync_state_3), .clk(clk_pin_c), .dataa(vsync_state_1), .datab(VCC), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(vsync_state_next_2_sqmuxa), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_3_.operation_mode="normal"; defparam vsync_state_3_.output_mode="reg_only"; defparam vsync_state_3_.lut_mask="aaaa"; defparam vsync_state_3_.synch_mode="on"; defparam vsync_state_3_.sum_lutc_input="datac"; // @13:300 stratix_lcell vsync_state_2_ ( .regout(vsync_state_2), .clk(clk_pin_c), .dataa(vsync_counter_0), .datab(vsync_counter_9), .datac(vsync_state_3), .datad(un14_vsync_counter_8), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(vsync_state_next_2_sqmuxa), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_2_.operation_mode="normal"; defparam vsync_state_2_.output_mode="reg_only"; defparam vsync_state_2_.lut_mask="8000"; defparam vsync_state_2_.synch_mode="on"; defparam vsync_state_2_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_5_ ( .regout(hsync_state_5), .clk(clk_pin_c), .dataa(hsync_state_6), .datab(hsync_state_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_5_.operation_mode="normal"; defparam hsync_state_5_.output_mode="reg_only"; defparam hsync_state_5_.lut_mask="eeee"; defparam hsync_state_5_.synch_mode="on"; defparam hsync_state_5_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_4_ ( .regout(hsync_state_4), .clk(clk_pin_c), .dataa(hsync_state_5), .datab(un10_hsync_counter_3), .datac(un10_hsync_counter_1), .datad(un10_hsync_counter_4), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_4_.operation_mode="normal"; defparam hsync_state_4_.output_mode="reg_only"; defparam hsync_state_4_.lut_mask="8000"; defparam hsync_state_4_.synch_mode="on"; defparam hsync_state_4_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_3_ ( .regout(hsync_state_3), .clk(clk_pin_c), .dataa(hsync_state_1), .datab(VCC), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_3_.operation_mode="normal"; defparam hsync_state_3_.output_mode="reg_only"; defparam hsync_state_3_.lut_mask="aaaa"; defparam hsync_state_3_.synch_mode="on"; defparam hsync_state_3_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_2_ ( .regout(hsync_state_2), .clk(clk_pin_c), .dataa(hsync_state_3), .datab(un12_hsync_counter), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_2_.operation_mode="normal"; defparam hsync_state_2_.output_mode="reg_only"; defparam hsync_state_2_.lut_mask="8888"; defparam hsync_state_2_.synch_mode="on"; defparam hsync_state_2_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_1_ ( .regout(hsync_state_1), .clk(clk_pin_c), .dataa(hsync_state_4), .datab(un11_hsync_counter_2), .datac(un10_hsync_counter_1), .datad(un11_hsync_counter_3), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_1_.operation_mode="normal"; defparam hsync_state_1_.output_mode="reg_only"; defparam hsync_state_1_.lut_mask="8000"; defparam hsync_state_1_.synch_mode="on"; defparam hsync_state_1_.sum_lutc_input="datac"; // @13:187 stratix_lcell hsync_state_0_ ( .regout(hsync_state_0), .clk(clk_pin_c), .dataa(hsync_state_2), .datab(un13_hsync_counter), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(un6_dly_counter_0_x), .sload(GND), .ena(hsync_state_3_0_0_0__g0_0), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_0_.operation_mode="normal"; defparam hsync_state_0_.output_mode="reg_only"; defparam hsync_state_0_.lut_mask="8888"; defparam hsync_state_0_.synch_mode="on"; defparam hsync_state_0_.sum_lutc_input="datac"; // @13:97 stratix_lcell vsync_state_next_2_sqmuxa_cZ ( .combout(vsync_state_next_2_sqmuxa), .clk(GND), .dataa(un6_dly_counter_0_x), .datab(vsync_state_next_1_sqmuxa_1), .datac(vsync_state_next_1_sqmuxa_3), .datad(un1_vsync_state_next_1_sqmuxa_0), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal"; defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only"; defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab"; defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off"; defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac"; stratix_lcell hsync_state_3_0_0_0__g0_0_cZ ( .combout(hsync_state_3_0_0_0__g0_0), .clk(GND), .dataa(hsync_state_next_1_sqmuxa_1), .datab(hsync_state_next_1_sqmuxa_2), .datac(un6_dly_counter_0_x), .datad(un1_hsync_state_next_1_sqmuxa_0), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal"; defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only"; defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1"; defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off"; defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac"; // @13:206 stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ ( .combout(un1_hsync_state_next_1_sqmuxa_0), .clk(GND), .dataa(hsync_state_2), .datab(hsync_state_3), .datac(un13_hsync_counter), .datad(un12_hsync_counter), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal"; defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only"; defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace"; defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off"; defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac"; // @13:319 stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ ( .combout(un1_vsync_state_next_1_sqmuxa_0), .clk(GND), .dataa(vsync_state_2), .datab(un12_vsync_counter_6), .datac(un15_vsync_counter_4), .datad(vsync_state_next_1_sqmuxa_2), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal"; defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only"; defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a"; defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off"; defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac"; // @13:111 stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 ( .combout(un10_column_counter_siglto9), .clk(GND), .dataa(column_counter_sig_7), .datab(column_counter_sig_8), .datac(column_counter_sig_9), .datad(un10_column_counter_siglt6), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal"; defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only"; defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f"; defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off"; defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac"; stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ ( .combout(vsync_state_3_iv_0_0__g0_0_a3_0), .clk(GND), .dataa(vsync_state_2), .datab(un12_vsync_counter_6), .datac(un15_vsync_counter_4), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal"; defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only"; defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080"; defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off"; defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac"; // @13:139 stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 ( .combout(un10_line_counter_siglto8), .clk(GND), .dataa(line_counter_sig_6), .datab(line_counter_sig_7), .datac(line_counter_sig_8), .datad(un10_line_counter_siglto5), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal"; defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only"; defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f"; defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off"; defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac"; // @13:326 stratix_lcell vsync_state_next_1_sqmuxa_1_cZ ( .combout(vsync_state_next_1_sqmuxa_1), .clk(GND), .dataa(vsync_counter_0), .datab(vsync_counter_9), .datac(vsync_state_5), .datad(un14_vsync_counter_8), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal"; defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only"; defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0"; defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off"; defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac"; // @13:331 stratix_lcell vsync_state_next_1_sqmuxa_2_cZ ( .combout(vsync_state_next_1_sqmuxa_2), .clk(GND), .dataa(vsync_state_4), .datab(un12_vsync_counter_7), .datac(un13_vsync_counter_4), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal"; defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only"; defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a"; defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off"; defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac"; // @13:339 stratix_lcell vsync_state_next_1_sqmuxa_3_cZ ( .combout(vsync_state_next_1_sqmuxa_3), .clk(GND), .dataa(vsync_counter_0), .datab(vsync_counter_9), .datac(vsync_state_3), .datad(un14_vsync_counter_8), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal"; defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only"; defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0"; defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off"; defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac"; // @10:159 stratix_lcell G_16 ( .combout(G_16_i), .clk(GND), .dataa(vsync_state_0), .datab(vsync_state_6), .datac(un9_vsync_counterlt9), .datad(un6_dly_counter_0_x), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam G_16.operation_mode="normal"; defparam G_16.output_mode="comb_only"; defparam G_16.lut_mask="0f1f"; defparam G_16.synch_mode="off"; defparam G_16.sum_lutc_input="datac"; // @10:159 stratix_lcell G_2 ( .combout(G_2_i), .clk(GND), .dataa(hsync_state_0), .datab(hsync_state_6), .datac(un9_hsync_counterlt9), .datad(un6_dly_counter_0_x), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam G_2.operation_mode="normal"; defparam G_2.output_mode="comb_only"; defparam G_2.lut_mask="0f1f"; defparam G_2.synch_mode="off"; defparam G_2.sum_lutc_input="datac"; // @13:218 stratix_lcell hsync_state_next_1_sqmuxa_2_cZ ( .combout(hsync_state_next_1_sqmuxa_2), .clk(GND), .dataa(hsync_state_4), .datab(un11_hsync_counter_2), .datac(un10_hsync_counter_1), .datad(un11_hsync_counter_3), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal"; defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only"; defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa"; defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off"; defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac"; // @13:213 stratix_lcell hsync_state_next_1_sqmuxa_1_cZ ( .combout(hsync_state_next_1_sqmuxa_1), .clk(GND), .dataa(hsync_state_5), .datab(un10_hsync_counter_3), .datac(un10_hsync_counter_1), .datad(un10_hsync_counter_4), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal"; defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only"; defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa"; defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off"; defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac"; // @13:281 stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 ( .combout(un9_vsync_counterlt9), .clk(GND), .dataa(vsync_counter_4), .datab(vsync_counter_5), .datac(un9_vsync_counterlt9_5), .datad(un9_vsync_counterlt9_6), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac"; // @13:111 stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 ( .combout(un10_column_counter_siglt6), .clk(GND), .dataa(column_counter_sig_3), .datab(column_counter_sig_4), .datac(un10_column_counter_siglt6_3), .datad(un10_column_counter_siglt6_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="fff7"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac"; // @13:226 stratix_lcell HSYNC_FSM_next_un12_hsync_counter ( .combout(un12_hsync_counter), .clk(GND), .dataa(hsync_counter_0), .datab(hsync_counter_1), .datac(un12_hsync_counter_3), .datad(un12_hsync_counter_4), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal"; defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only"; defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000"; defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off"; defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac"; // @13:231 stratix_lcell HSYNC_FSM_next_un13_hsync_counter ( .combout(un13_hsync_counter), .clk(GND), .dataa(hsync_counter_6), .datab(hsync_counter_7), .datac(un13_hsync_counter_2), .datad(un13_hsync_counter_7), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal"; defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only"; defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000"; defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off"; defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac"; // @13:172 stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 ( .combout(un9_hsync_counterlt9), .clk(GND), .dataa(hsync_counter_4), .datab(hsync_counter_5), .datac(un9_hsync_counterlt9_3), .datad(un13_hsync_counter_7), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac"; // @13:139 stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 ( .combout(un10_line_counter_siglto5), .clk(GND), .dataa(line_counter_sig_1), .datab(line_counter_sig_2), .datac(line_counter_sig_5), .datad(un10_line_counter_siglt4_2), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal"; defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only"; defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07"; defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off"; defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac"; // @13:331 stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 ( .combout(un13_vsync_counter_4), .clk(GND), .dataa(vsync_counter_0), .datab(vsync_counter_5), .datac(un13_vsync_counter_3), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal"; defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only"; defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080"; defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off"; defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac"; // @13:344 stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 ( .combout(un15_vsync_counter_4), .clk(GND), .dataa(vsync_counter_1), .datab(vsync_counter_4), .datac(un15_vsync_counter_3), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal"; defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only"; defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010"; defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off"; defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac"; // @13:139 stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ ( .combout(line_counter_next_0_sqmuxa_1_1), .clk(GND), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(vsync_state_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal"; defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only"; defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080"; defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off"; defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac"; stratix_lcell v_sync_1_0_0_0_g1_cZ ( .combout(v_sync_1_0_0_0_g1), .clk(GND), .dataa(vsync_state_2), .datab(v_sync), .datac(vsync_state_4), .datad(un1_vsync_state_2_0), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal"; defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only"; defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8"; defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off"; defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac"; stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ ( .combout(h_enable_sig_1_0_0_0_g0_i_o4), .clk(GND), .dataa(vsync_state_4), .datab(vsync_state_5), .datac(un6_dly_counter_0_x), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal"; defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only"; defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1"; defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off"; defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac"; // @13:278 stratix_lcell vsync_counter_next_1_sqmuxa_cZ ( .combout(vsync_counter_next_1_sqmuxa), .clk(GND), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(d_set_vsync_counter), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal"; defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only"; defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080"; defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off"; defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac"; // @13:339 stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 ( .combout(un14_vsync_counter_8), .clk(GND), .dataa(un12_vsync_counter_6), .datab(un12_vsync_counter_7), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal"; defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only"; defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888"; defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off"; defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac"; // @13:169 stratix_lcell hsync_counter_next_1_sqmuxa_cZ ( .combout(hsync_counter_next_1_sqmuxa), .clk(GND), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(d_set_hsync_counter), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal"; defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only"; defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080"; defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off"; defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac"; // @13:111 stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ ( .combout(column_counter_next_0_sqmuxa_1_1), .clk(GND), .dataa(reset_pin_c), .datab(dly_counter_0), .datac(dly_counter_1), .datad(hsync_state_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal"; defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only"; defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080"; defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off"; defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac"; stratix_lcell h_sync_1_0_0_0_g1_cZ ( .combout(h_sync_1_0_0_0_g1), .clk(GND), .dataa(hsync_state_2), .datab(h_sync), .datac(hsync_state_4), .datad(un1_hsync_state_3_0), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal"; defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only"; defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8"; defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off"; defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac"; stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ ( .combout(v_enable_sig_1_0_0_0_g0_i_o4), .clk(GND), .dataa(hsync_state_4), .datab(hsync_state_5), .datac(un6_dly_counter_0_x), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal"; defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only"; defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1"; defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off"; defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac"; // @13:226 stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 ( .combout(un12_hsync_counter_4), .clk(GND), .dataa(hsync_counter_6), .datab(hsync_counter_7), .datac(hsync_counter_8), .datad(hsync_counter_4), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal"; defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only"; defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010"; defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off"; defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac"; // @13:226 stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 ( .combout(un12_hsync_counter_3), .clk(GND), .dataa(hsync_counter_9), .datab(hsync_counter_5), .datac(hsync_counter_2), .datad(hsync_counter_3), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal"; defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only"; defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0020"; defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off"; defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac"; // @13:218 stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 ( .combout(un11_hsync_counter_3), .clk(GND), .dataa(hsync_counter_0), .datab(hsync_counter_1), .datac(hsync_counter_3), .datad(hsync_counter_4), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal"; defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only"; defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008"; defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off"; defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac"; // @13:218 stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 ( .combout(un11_hsync_counter_2), .clk(GND), .dataa(hsync_counter_2), .datab(hsync_counter_7), .datac(hsync_counter_6), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal"; defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only"; defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808"; defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off"; defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac"; // @13:172 stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 ( .combout(un9_hsync_counterlt9_3), .clk(GND), .dataa(hsync_counter_6), .datab(hsync_counter_7), .datac(hsync_counter_8), .datad(hsync_counter_9), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off"; defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac"; // @13:231 stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 ( .combout(un13_hsync_counter_2), .clk(GND), .dataa(hsync_counter_8), .datab(hsync_counter_9), .datac(hsync_counter_4), .datad(hsync_counter_5), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal"; defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only"; defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080"; defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off"; defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac"; // @13:281 stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 ( .combout(un9_vsync_counterlt9_6), .clk(GND), .dataa(vsync_counter_2), .datab(vsync_counter_3), .datac(vsync_counter_0), .datad(vsync_counter_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac"; // @13:281 stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 ( .combout(un9_vsync_counterlt9_5), .clk(GND), .dataa(vsync_counter_8), .datab(vsync_counter_9), .datac(vsync_counter_6), .datad(vsync_counter_7), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off"; defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac"; // @13:331 stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 ( .combout(un13_vsync_counter_3), .clk(GND), .dataa(vsync_counter_6), .datab(vsync_counter_7), .datac(vsync_counter_8), .datad(vsync_counter_9), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal"; defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only"; defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001"; defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off"; defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac"; // @13:344 stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 ( .combout(un15_vsync_counter_3), .clk(GND), .dataa(vsync_counter_3), .datab(vsync_counter_9), .datac(vsync_counter_0), .datad(vsync_counter_2), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal"; defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only"; defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0008"; defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off"; defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac"; // @13:213 stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 ( .combout(un10_hsync_counter_4), .clk(GND), .dataa(hsync_counter_4), .datab(hsync_counter_6), .datac(hsync_counter_1), .datad(hsync_counter_3), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal"; defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only"; defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000"; defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off"; defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac"; // @13:213 stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 ( .combout(un10_hsync_counter_3), .clk(GND), .dataa(hsync_counter_0), .datab(hsync_counter_7), .datac(hsync_counter_2), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal"; defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only"; defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101"; defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off"; defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac"; // @13:139 stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 ( .combout(un10_line_counter_siglt4_2), .clk(GND), .dataa(line_counter_sig_3), .datab(line_counter_sig_4), .datac(line_counter_sig_0), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal"; defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only"; defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f"; defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off"; defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac"; // @13:326 stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 ( .combout(un12_vsync_counter_6), .clk(GND), .dataa(vsync_counter_7), .datab(vsync_counter_8), .datac(vsync_counter_5), .datad(vsync_counter_6), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal"; defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only"; defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001"; defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off"; defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac"; // @13:326 stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 ( .combout(un12_vsync_counter_7), .clk(GND), .dataa(vsync_counter_3), .datab(vsync_counter_4), .datac(vsync_counter_1), .datad(vsync_counter_2), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal"; defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only"; defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001"; defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off"; defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac"; // @13:111 stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_1 ( .combout(un10_column_counter_siglt6_1), .clk(GND), .dataa(column_counter_sig_0), .datab(column_counter_sig_2), .datac(column_counter_sig_1), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.operation_mode="normal"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.output_mode="comb_only"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.lut_mask="7f7f"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.synch_mode="off"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.sum_lutc_input="datac"; // @13:231 stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 ( .combout(un13_hsync_counter_7), .clk(GND), .dataa(hsync_counter_2), .datab(hsync_counter_3), .datac(hsync_counter_0), .datad(hsync_counter_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal"; defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only"; defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000"; defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off"; defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac"; // @13:213 stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 ( .combout(un10_hsync_counter_1), .clk(GND), .dataa(hsync_counter_5), .datab(hsync_counter_8), .datac(hsync_counter_9), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal"; defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only"; defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101"; defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off"; defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac"; // @13:206 stratix_lcell un1_hsync_state_3_0_cZ ( .combout(un1_hsync_state_3_0), .clk(GND), .dataa(hsync_state_3), .datab(hsync_state_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_hsync_state_3_0_cZ.operation_mode="normal"; defparam un1_hsync_state_3_0_cZ.output_mode="comb_only"; defparam un1_hsync_state_3_0_cZ.lut_mask="eeee"; defparam un1_hsync_state_3_0_cZ.synch_mode="off"; defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac"; // @13:319 stratix_lcell un1_vsync_state_2_0_cZ ( .combout(un1_vsync_state_2_0), .clk(GND), .dataa(vsync_state_3), .datab(vsync_state_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_vsync_state_2_0_cZ.operation_mode="normal"; defparam un1_vsync_state_2_0_cZ.output_mode="comb_only"; defparam un1_vsync_state_2_0_cZ.lut_mask="eeee"; defparam un1_vsync_state_2_0_cZ.synch_mode="off"; defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac"; // @13:361 stratix_lcell d_set_vsync_counter_cZ ( .combout(d_set_vsync_counter), .clk(GND), .dataa(vsync_state_6), .datab(vsync_state_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam d_set_vsync_counter_cZ.operation_mode="normal"; defparam d_set_vsync_counter_cZ.output_mode="comb_only"; defparam d_set_vsync_counter_cZ.lut_mask="eeee"; defparam d_set_vsync_counter_cZ.synch_mode="off"; defparam d_set_vsync_counter_cZ.sum_lutc_input="datac"; // @13:111 stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_3 ( .combout(un10_column_counter_siglt6_3), .clk(GND), .dataa(column_counter_sig_6), .datab(column_counter_sig_5), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.operation_mode="normal"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.output_mode="comb_only"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.lut_mask="7777"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.synch_mode="off"; defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.sum_lutc_input="datac"; // @13:248 stratix_lcell d_set_hsync_counter_cZ ( .combout(d_set_hsync_counter), .clk(GND), .dataa(hsync_state_6), .datab(hsync_state_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam d_set_hsync_counter_cZ.operation_mode="normal"; defparam d_set_hsync_counter_cZ.output_mode="comb_only"; defparam d_set_hsync_counter_cZ.lut_mask="eeee"; defparam d_set_hsync_counter_cZ.synch_mode="off"; defparam d_set_hsync_counter_cZ.sum_lutc_input="datac"; // @13:141 stratix_lcell un1_line_counter_sig_9_ ( .combout(un1_line_counter_sig_combout[9]), .clk(GND), .dataa(line_counter_sig_7), .datab(line_counter_sig_8), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[7]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_9_.cin_used="true"; defparam un1_line_counter_sig_9_.operation_mode="normal"; defparam un1_line_counter_sig_9_.output_mode="comb_only"; defparam un1_line_counter_sig_9_.lut_mask="6c6c"; defparam un1_line_counter_sig_9_.synch_mode="off"; defparam un1_line_counter_sig_9_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_8_ ( .combout(un1_line_counter_sig_combout[8]), .clk(GND), .dataa(line_counter_sig_7), .datab(VCC), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[6]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_8_.cin_used="true"; defparam un1_line_counter_sig_8_.operation_mode="normal"; defparam un1_line_counter_sig_8_.output_mode="comb_only"; defparam un1_line_counter_sig_8_.lut_mask="5a5a"; defparam un1_line_counter_sig_8_.synch_mode="off"; defparam un1_line_counter_sig_8_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_7_ ( .combout(un1_line_counter_sig_combout[7]), .cout(un1_line_counter_sig_cout[7]), .clk(GND), .dataa(line_counter_sig_5), .datab(line_counter_sig_6), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[5]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_7_.cin_used="true"; defparam un1_line_counter_sig_7_.operation_mode="arithmetic"; defparam un1_line_counter_sig_7_.output_mode="comb_only"; defparam un1_line_counter_sig_7_.lut_mask="6c80"; defparam un1_line_counter_sig_7_.synch_mode="off"; defparam un1_line_counter_sig_7_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_6_ ( .combout(un1_line_counter_sig_combout[6]), .cout(un1_line_counter_sig_cout[6]), .clk(GND), .dataa(line_counter_sig_5), .datab(line_counter_sig_6), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[4]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_6_.cin_used="true"; defparam un1_line_counter_sig_6_.operation_mode="arithmetic"; defparam un1_line_counter_sig_6_.output_mode="comb_only"; defparam un1_line_counter_sig_6_.lut_mask="5a80"; defparam un1_line_counter_sig_6_.synch_mode="off"; defparam un1_line_counter_sig_6_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_5_ ( .combout(un1_line_counter_sig_combout[5]), .cout(un1_line_counter_sig_cout[5]), .clk(GND), .dataa(line_counter_sig_3), .datab(line_counter_sig_4), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[3]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_5_.cin_used="true"; defparam un1_line_counter_sig_5_.operation_mode="arithmetic"; defparam un1_line_counter_sig_5_.output_mode="comb_only"; defparam un1_line_counter_sig_5_.lut_mask="6c80"; defparam un1_line_counter_sig_5_.synch_mode="off"; defparam un1_line_counter_sig_5_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_4_ ( .combout(un1_line_counter_sig_combout[4]), .cout(un1_line_counter_sig_cout[4]), .clk(GND), .dataa(line_counter_sig_3), .datab(line_counter_sig_4), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[2]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_4_.cin_used="true"; defparam un1_line_counter_sig_4_.operation_mode="arithmetic"; defparam un1_line_counter_sig_4_.output_mode="comb_only"; defparam un1_line_counter_sig_4_.lut_mask="5a80"; defparam un1_line_counter_sig_4_.synch_mode="off"; defparam un1_line_counter_sig_4_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_3_ ( .combout(un1_line_counter_sig_combout[3]), .cout(un1_line_counter_sig_cout[3]), .clk(GND), .dataa(line_counter_sig_1), .datab(line_counter_sig_2), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_cout[1]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_3_.cin_used="true"; defparam un1_line_counter_sig_3_.operation_mode="arithmetic"; defparam un1_line_counter_sig_3_.output_mode="comb_only"; defparam un1_line_counter_sig_3_.lut_mask="6c80"; defparam un1_line_counter_sig_3_.synch_mode="off"; defparam un1_line_counter_sig_3_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_2_ ( .combout(un1_line_counter_sig_combout[2]), .cout(un1_line_counter_sig_cout[2]), .clk(GND), .dataa(line_counter_sig_1), .datab(line_counter_sig_2), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un1_line_counter_sig_a_cout[1]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_2_.cin_used="true"; defparam un1_line_counter_sig_2_.operation_mode="arithmetic"; defparam un1_line_counter_sig_2_.output_mode="comb_only"; defparam un1_line_counter_sig_2_.lut_mask="5a80"; defparam un1_line_counter_sig_2_.synch_mode="off"; defparam un1_line_counter_sig_2_.sum_lutc_input="cin"; // @13:141 stratix_lcell un1_line_counter_sig_a_1_ ( .cout(un1_line_counter_sig_a_cout[1]), .clk(GND), .dataa(d_set_hsync_counter), .datab(line_counter_sig_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic"; defparam un1_line_counter_sig_a_1_.output_mode="comb_only"; defparam un1_line_counter_sig_a_1_.lut_mask="0088"; defparam un1_line_counter_sig_a_1_.synch_mode="off"; defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac"; // @13:141 stratix_lcell un1_line_counter_sig_1_ ( .combout(un1_line_counter_sig_combout[1]), .cout(un1_line_counter_sig_cout[1]), .clk(GND), .dataa(d_set_hsync_counter), .datab(line_counter_sig_0), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un1_line_counter_sig_1_.operation_mode="arithmetic"; defparam un1_line_counter_sig_1_.output_mode="comb_only"; defparam un1_line_counter_sig_1_.lut_mask="6688"; defparam un1_line_counter_sig_1_.synch_mode="off"; defparam un1_line_counter_sig_1_.sum_lutc_input="datac"; // @13:112 stratix_lcell un2_column_counter_next_9_ ( .combout(un2_column_counter_next_combout[9]), .clk(GND), .dataa(column_counter_sig_8), .datab(column_counter_sig_9), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[7]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_9_.cin_used="true"; defparam un2_column_counter_next_9_.operation_mode="normal"; defparam un2_column_counter_next_9_.output_mode="comb_only"; defparam un2_column_counter_next_9_.lut_mask="6c6c"; defparam un2_column_counter_next_9_.synch_mode="off"; defparam un2_column_counter_next_9_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_8_ ( .combout(un2_column_counter_next_combout[8]), .clk(GND), .dataa(column_counter_sig_8), .datab(VCC), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[6]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_8_.cin_used="true"; defparam un2_column_counter_next_8_.operation_mode="normal"; defparam un2_column_counter_next_8_.output_mode="comb_only"; defparam un2_column_counter_next_8_.lut_mask="5a5a"; defparam un2_column_counter_next_8_.synch_mode="off"; defparam un2_column_counter_next_8_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_7_ ( .combout(un2_column_counter_next_combout[7]), .cout(un2_column_counter_next_cout[7]), .clk(GND), .dataa(column_counter_sig_6), .datab(column_counter_sig_7), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[5]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_7_.cin_used="true"; defparam un2_column_counter_next_7_.operation_mode="arithmetic"; defparam un2_column_counter_next_7_.output_mode="comb_only"; defparam un2_column_counter_next_7_.lut_mask="6c80"; defparam un2_column_counter_next_7_.synch_mode="off"; defparam un2_column_counter_next_7_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_6_ ( .combout(un2_column_counter_next_combout[6]), .cout(un2_column_counter_next_cout[6]), .clk(GND), .dataa(column_counter_sig_6), .datab(column_counter_sig_7), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[4]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_6_.cin_used="true"; defparam un2_column_counter_next_6_.operation_mode="arithmetic"; defparam un2_column_counter_next_6_.output_mode="comb_only"; defparam un2_column_counter_next_6_.lut_mask="5a80"; defparam un2_column_counter_next_6_.synch_mode="off"; defparam un2_column_counter_next_6_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_5_ ( .combout(un2_column_counter_next_combout[5]), .cout(un2_column_counter_next_cout[5]), .clk(GND), .dataa(column_counter_sig_4), .datab(column_counter_sig_5), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[3]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_5_.cin_used="true"; defparam un2_column_counter_next_5_.operation_mode="arithmetic"; defparam un2_column_counter_next_5_.output_mode="comb_only"; defparam un2_column_counter_next_5_.lut_mask="6c80"; defparam un2_column_counter_next_5_.synch_mode="off"; defparam un2_column_counter_next_5_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_4_ ( .combout(un2_column_counter_next_combout[4]), .cout(un2_column_counter_next_cout[4]), .clk(GND), .dataa(column_counter_sig_4), .datab(column_counter_sig_5), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[2]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_4_.cin_used="true"; defparam un2_column_counter_next_4_.operation_mode="arithmetic"; defparam un2_column_counter_next_4_.output_mode="comb_only"; defparam un2_column_counter_next_4_.lut_mask="5a80"; defparam un2_column_counter_next_4_.synch_mode="off"; defparam un2_column_counter_next_4_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_3_ ( .combout(un2_column_counter_next_combout[3]), .cout(un2_column_counter_next_cout[3]), .clk(GND), .dataa(column_counter_sig_2), .datab(column_counter_sig_3), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[1]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_3_.cin_used="true"; defparam un2_column_counter_next_3_.operation_mode="arithmetic"; defparam un2_column_counter_next_3_.output_mode="comb_only"; defparam un2_column_counter_next_3_.lut_mask="6c80"; defparam un2_column_counter_next_3_.synch_mode="off"; defparam un2_column_counter_next_3_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_2_ ( .combout(un2_column_counter_next_combout[2]), .cout(un2_column_counter_next_cout[2]), .clk(GND), .dataa(column_counter_sig_2), .datab(column_counter_sig_3), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .cin(un2_column_counter_next_cout[0]), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_2_.cin_used="true"; defparam un2_column_counter_next_2_.operation_mode="arithmetic"; defparam un2_column_counter_next_2_.output_mode="comb_only"; defparam un2_column_counter_next_2_.lut_mask="5a80"; defparam un2_column_counter_next_2_.synch_mode="off"; defparam un2_column_counter_next_2_.sum_lutc_input="cin"; // @13:112 stratix_lcell un2_column_counter_next_1_ ( .combout(un2_column_counter_next_combout[1]), .cout(un2_column_counter_next_cout[1]), .clk(GND), .dataa(column_counter_sig_0), .datab(column_counter_sig_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_1_.operation_mode="arithmetic"; defparam un2_column_counter_next_1_.output_mode="comb_only"; defparam un2_column_counter_next_1_.lut_mask="6688"; defparam un2_column_counter_next_1_.synch_mode="off"; defparam un2_column_counter_next_1_.sum_lutc_input="datac"; // @13:112 stratix_lcell un2_column_counter_next_0_ ( .cout(un2_column_counter_next_cout[0]), .clk(GND), .dataa(column_counter_sig_0), .datab(column_counter_sig_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam un2_column_counter_next_0_.operation_mode="arithmetic"; defparam un2_column_counter_next_0_.output_mode="comb_only"; defparam un2_column_counter_next_0_.lut_mask="5588"; defparam un2_column_counter_next_0_.synch_mode="off"; defparam un2_column_counter_next_0_.sum_lutc_input="datac"; assign line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1; assign column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1; assign un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9; assign G_16_i_i = ~ G_16_i; assign un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9; assign G_2_i_i = ~ G_2_i; endmodule /* vga_driver */ // VQM4.1+ module vga_control ( column_counter_sig_1, column_counter_sig_7, column_counter_sig_2, column_counter_sig_0, column_counter_sig_4, column_counter_sig_3, column_counter_sig_5, column_counter_sig_6, h_enable_sig, v_enable_sig, un10_column_counter_siglt6_1, g, un10_column_counter_siglt6_3, r, un6_dly_counter_0_x, clk_pin_c, b ) ; input column_counter_sig_1 ; input column_counter_sig_7 ; input column_counter_sig_2 ; input column_counter_sig_0 ; input column_counter_sig_4 ; input column_counter_sig_3 ; input column_counter_sig_5 ; input column_counter_sig_6 ; input h_enable_sig ; input v_enable_sig ; input un10_column_counter_siglt6_1 ; output g ; input un10_column_counter_siglt6_3 ; output r ; input un6_dly_counter_0_x ; input clk_pin_c ; output b ; wire column_counter_sig_1 ; wire column_counter_sig_7 ; wire column_counter_sig_2 ; wire column_counter_sig_0 ; wire column_counter_sig_4 ; wire column_counter_sig_3 ; wire column_counter_sig_5 ; wire column_counter_sig_6 ; wire h_enable_sig ; wire v_enable_sig ; wire un10_column_counter_siglt6_1 ; wire g ; wire un10_column_counter_siglt6_3 ; wire r ; wire un6_dly_counter_0_x ; wire clk_pin_c ; wire b ; wire b_next_i_o3_0 ; wire b_next_i_a7_1 ; wire N_6_i_0_g0_0 ; wire N_4_i_0_g0_1 ; wire r_next_i_o7 ; wire N_23_i_0_g0_a ; wire g_next_i_o3 ; wire GND ; wire VCC ; assign VCC = 1'b1; assign GND = 1'b0; // @12:46 stratix_lcell b_Z ( .regout(b), .clk(clk_pin_c), .dataa(column_counter_sig_6), .datab(b_next_i_o3_0), .datac(b_next_i_a7_1), .datad(N_6_i_0_g0_0), .aclr(un6_dly_counter_0_x), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam b_Z.operation_mode="normal"; defparam b_Z.output_mode="reg_only"; defparam b_Z.lut_mask="0700"; defparam b_Z.synch_mode="off"; defparam b_Z.sum_lutc_input="datac"; // @12:46 stratix_lcell r_Z ( .regout(r), .clk(clk_pin_c), .dataa(column_counter_sig_6), .datab(un10_column_counter_siglt6_3), .datac(b_next_i_o3_0), .datad(N_4_i_0_g0_1), .aclr(un6_dly_counter_0_x), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam r_Z.operation_mode="normal"; defparam r_Z.output_mode="reg_only"; defparam r_Z.lut_mask="1b00"; defparam r_Z.synch_mode="off"; defparam r_Z.sum_lutc_input="datac"; // @12:46 stratix_lcell g_Z ( .regout(g), .clk(clk_pin_c), .dataa(column_counter_sig_6), .datab(column_counter_sig_5), .datac(r_next_i_o7), .datad(N_23_i_0_g0_a), .aclr(un6_dly_counter_0_x), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam g_Z.operation_mode="normal"; defparam g_Z.output_mode="reg_only"; defparam g_Z.lut_mask="0400"; defparam g_Z.synch_mode="off"; defparam g_Z.sum_lutc_input="datac"; stratix_lcell N_23_i_0_g0_a_cZ ( .combout(N_23_i_0_g0_a), .clk(GND), .dataa(column_counter_sig_3), .datab(column_counter_sig_4), .datac(g_next_i_o3), .datad(un10_column_counter_siglt6_1), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam N_23_i_0_g0_a_cZ.operation_mode="normal"; defparam N_23_i_0_g0_a_cZ.output_mode="comb_only"; defparam N_23_i_0_g0_a_cZ.lut_mask="6c6e"; defparam N_23_i_0_g0_a_cZ.synch_mode="off"; defparam N_23_i_0_g0_a_cZ.sum_lutc_input="datac"; stratix_lcell N_4_i_0_g0_1_cZ ( .combout(N_4_i_0_g0_1), .clk(GND), .dataa(column_counter_sig_5), .datab(column_counter_sig_6), .datac(g_next_i_o3), .datad(r_next_i_o7), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam N_4_i_0_g0_1_cZ.operation_mode="normal"; defparam N_4_i_0_g0_1_cZ.output_mode="comb_only"; defparam N_4_i_0_g0_1_cZ.lut_mask="00ec"; defparam N_4_i_0_g0_1_cZ.synch_mode="off"; defparam N_4_i_0_g0_1_cZ.sum_lutc_input="datac"; stratix_lcell N_6_i_0_g0_0_cZ ( .combout(N_6_i_0_g0_0), .clk(GND), .dataa(column_counter_sig_5), .datab(column_counter_sig_6), .datac(un10_column_counter_siglt6_3), .datad(r_next_i_o7), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam N_6_i_0_g0_0_cZ.operation_mode="normal"; defparam N_6_i_0_g0_0_cZ.output_mode="comb_only"; defparam N_6_i_0_g0_0_cZ.lut_mask="00ef"; defparam N_6_i_0_g0_0_cZ.synch_mode="off"; defparam N_6_i_0_g0_0_cZ.sum_lutc_input="datac"; // @12:60 stratix_lcell b_next_i_a7_1_cZ ( .combout(b_next_i_a7_1), .clk(GND), .dataa(column_counter_sig_5), .datab(column_counter_sig_6), .datac(column_counter_sig_0), .datad(g_next_i_o3), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam b_next_i_a7_1_cZ.operation_mode="normal"; defparam b_next_i_a7_1_cZ.output_mode="comb_only"; defparam b_next_i_a7_1_cZ.lut_mask="0001"; defparam b_next_i_a7_1_cZ.synch_mode="off"; defparam b_next_i_a7_1_cZ.sum_lutc_input="datac"; // @12:60 stratix_lcell b_next_i_o3_0_cZ ( .combout(b_next_i_o3_0), .clk(GND), .dataa(column_counter_sig_3), .datab(column_counter_sig_4), .datac(column_counter_sig_2), .datad(column_counter_sig_5), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam b_next_i_o3_0_cZ.operation_mode="normal"; defparam b_next_i_o3_0_cZ.output_mode="comb_only"; defparam b_next_i_o3_0_cZ.lut_mask="ff80"; defparam b_next_i_o3_0_cZ.synch_mode="off"; defparam b_next_i_o3_0_cZ.sum_lutc_input="datac"; // @12:60 stratix_lcell r_next_i_o7_cZ ( .combout(r_next_i_o7), .clk(GND), .dataa(column_counter_sig_7), .datab(v_enable_sig), .datac(h_enable_sig), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam r_next_i_o7_cZ.operation_mode="normal"; defparam r_next_i_o7_cZ.output_mode="comb_only"; defparam r_next_i_o7_cZ.lut_mask="bfbf"; defparam r_next_i_o7_cZ.synch_mode="off"; defparam r_next_i_o7_cZ.sum_lutc_input="datac"; // @12:60 stratix_lcell g_next_i_o3_cZ ( .combout(g_next_i_o3), .clk(GND), .dataa(column_counter_sig_2), .datab(column_counter_sig_1), .datac(VCC), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam g_next_i_o3_cZ.operation_mode="normal"; defparam g_next_i_o3_cZ.output_mode="comb_only"; defparam g_next_i_o3_cZ.lut_mask="eeee"; defparam g_next_i_o3_cZ.synch_mode="off"; defparam g_next_i_o3_cZ.sum_lutc_input="datac"; endmodule /* vga_control */ // VQM4.1+ module vga ( clk_pin, reset_pin, r0_pin, r1_pin, r2_pin, g0_pin, g1_pin, g2_pin, b0_pin, b1_pin, hsync_pin, vsync_pin, seven_seg_pin, d_hsync, d_vsync, d_column_counter, d_line_counter, d_set_column_counter, d_set_line_counter, d_hsync_counter, d_vsync_counter, d_set_hsync_counter, d_set_vsync_counter, d_h_enable, d_v_enable, d_r, d_g, d_b, d_hsync_state, d_vsync_state, d_state_clk ) ; input clk_pin ; input reset_pin ; output r0_pin ; output r1_pin ; output r2_pin ; output g0_pin ; output g1_pin ; output g2_pin ; output b0_pin ; output b1_pin ; output hsync_pin ; output vsync_pin ; output [13:0] seven_seg_pin ; output d_hsync ; output d_vsync ; output [9:0] d_column_counter ; output [8:0] d_line_counter ; output d_set_column_counter ; output d_set_line_counter ; output [9:0] d_hsync_counter ; output [9:0] d_vsync_counter ; output d_set_hsync_counter ; output d_set_vsync_counter ; output d_h_enable ; output d_v_enable ; output d_r ; output d_g ; output d_b ; output [0:6] d_hsync_state ; output [0:6] d_vsync_state ; output d_state_clk ; wire clk_pin ; wire reset_pin ; wire r0_pin ; wire r1_pin ; wire r2_pin ; wire g0_pin ; wire g1_pin ; wire g2_pin ; wire b0_pin ; wire b1_pin ; wire hsync_pin ; wire vsync_pin ; wire d_hsync ; wire d_vsync ; wire d_set_column_counter ; wire d_set_line_counter ; wire d_set_hsync_counter ; wire d_set_vsync_counter ; wire d_h_enable ; wire d_v_enable ; wire d_r ; wire d_g ; wire d_b ; wire d_state_clk ; wire [1:0] dly_counter; wire [9:0] vga_driver_unit_column_counter_sig; wire [8:0] vga_driver_unit_line_counter_sig; wire [9:0] vga_driver_unit_hsync_counter; wire [9:0] vga_driver_unit_vsync_counter; wire [6:0] vga_driver_unit_hsync_state; wire [6:0] vga_driver_unit_vsync_state; wire VCC ; wire GND ; wire vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1 ; wire vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3 ; wire DELAY_RESET_next_un6_dly_counter_0_x ; wire vga_driver_unit_h_sync ; wire vga_driver_unit_v_sync ; wire vga_driver_unit_d_set_hsync_counter ; wire vga_driver_unit_d_set_vsync_counter ; wire vga_driver_unit_h_enable_sig ; wire vga_driver_unit_v_enable_sig ; wire vga_control_unit_r ; wire vga_control_unit_g ; wire vga_control_unit_b ; wire G_49 ; wire reset_pin_c ; //@1:1 assign VCC = 1'b1; //@1:1 assign GND = 1'b0; // @10:111 stratix_lcell dly_counter_1_ ( .regout(dly_counter[1]), .clk(G_49), .dataa(reset_pin_c), .datab(dly_counter[0]), .datac(dly_counter[1]), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam dly_counter_1_.operation_mode="normal"; defparam dly_counter_1_.output_mode="reg_only"; defparam dly_counter_1_.lut_mask="a8a8"; defparam dly_counter_1_.synch_mode="off"; defparam dly_counter_1_.sum_lutc_input="datac"; // @10:111 stratix_lcell dly_counter_0_ ( .regout(dly_counter[0]), .clk(G_49), .dataa(reset_pin_c), .datab(dly_counter[0]), .datac(dly_counter[1]), .datad(VCC), .aclr(GND), .sclr(GND), .sload(GND), .ena(VCC), .inverta(GND), .aload(GND), .regcascin(GND) ); defparam dly_counter_0_.operation_mode="normal"; defparam dly_counter_0_.output_mode="reg_only"; defparam dly_counter_0_.lut_mask="a2a2"; defparam dly_counter_0_.synch_mode="off"; defparam dly_counter_0_.sum_lutc_input="datac"; // @6:42 stratix_io reset_pin_in ( .padio(reset_pin), .combout(reset_pin_c), .datain(GND), .oe(GND), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam reset_pin_in.operation_mode = "input"; // @6:41 stratix_io clk_pin_in ( .padio(clk_pin), .combout(G_49), .datain(GND), .oe(GND), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam clk_pin_in.operation_mode = "input"; // @6:64 stratix_io d_state_clk_out ( .padio(d_state_clk), .datain(G_49), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_state_clk_out.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_0_ ( .padio(d_vsync_state[0]), .datain(vga_driver_unit_vsync_state[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_0_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_1_ ( .padio(d_vsync_state[1]), .datain(vga_driver_unit_vsync_state[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_1_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_2_ ( .padio(d_vsync_state[2]), .datain(vga_driver_unit_vsync_state[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_2_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_3_ ( .padio(d_vsync_state[3]), .datain(vga_driver_unit_vsync_state[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_3_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_4_ ( .padio(d_vsync_state[4]), .datain(vga_driver_unit_vsync_state[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_4_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_5_ ( .padio(d_vsync_state[5]), .datain(vga_driver_unit_vsync_state[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_5_.operation_mode = "output"; // @6:63 stratix_io d_vsync_state_out_6_ ( .padio(d_vsync_state[6]), .datain(vga_driver_unit_vsync_state[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_state_out_6_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_0_ ( .padio(d_hsync_state[0]), .datain(vga_driver_unit_hsync_state[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_0_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_1_ ( .padio(d_hsync_state[1]), .datain(vga_driver_unit_hsync_state[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_1_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_2_ ( .padio(d_hsync_state[2]), .datain(vga_driver_unit_hsync_state[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_2_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_3_ ( .padio(d_hsync_state[3]), .datain(vga_driver_unit_hsync_state[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_3_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_4_ ( .padio(d_hsync_state[4]), .datain(vga_driver_unit_hsync_state[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_4_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_5_ ( .padio(d_hsync_state[5]), .datain(vga_driver_unit_hsync_state[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_5_.operation_mode = "output"; // @6:62 stratix_io d_hsync_state_out_6_ ( .padio(d_hsync_state[6]), .datain(vga_driver_unit_hsync_state[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_state_out_6_.operation_mode = "output"; // @6:61 stratix_io d_b_out ( .padio(d_b), .datain(vga_control_unit_b), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_b_out.operation_mode = "output"; // @6:61 stratix_io d_g_out ( .padio(d_g), .datain(vga_control_unit_g), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_g_out.operation_mode = "output"; // @6:61 stratix_io d_r_out ( .padio(d_r), .datain(vga_control_unit_r), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_r_out.operation_mode = "output"; // @6:60 stratix_io d_v_enable_out ( .padio(d_v_enable), .datain(vga_driver_unit_v_enable_sig), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_v_enable_out.operation_mode = "output"; // @6:59 stratix_io d_h_enable_out ( .padio(d_h_enable), .datain(vga_driver_unit_h_enable_sig), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_h_enable_out.operation_mode = "output"; // @6:58 stratix_io d_set_vsync_counter_out ( .padio(d_set_vsync_counter), .datain(vga_driver_unit_d_set_vsync_counter), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_set_vsync_counter_out.operation_mode = "output"; // @6:58 stratix_io d_set_hsync_counter_out ( .padio(d_set_hsync_counter), .datain(vga_driver_unit_d_set_hsync_counter), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_set_hsync_counter_out.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_9_ ( .padio(d_vsync_counter[9]), .datain(vga_driver_unit_vsync_counter[9]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_9_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_8_ ( .padio(d_vsync_counter[8]), .datain(vga_driver_unit_vsync_counter[8]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_8_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_7_ ( .padio(d_vsync_counter[7]), .datain(vga_driver_unit_vsync_counter[7]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_7_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_6_ ( .padio(d_vsync_counter[6]), .datain(vga_driver_unit_vsync_counter[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_6_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_5_ ( .padio(d_vsync_counter[5]), .datain(vga_driver_unit_vsync_counter[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_5_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_4_ ( .padio(d_vsync_counter[4]), .datain(vga_driver_unit_vsync_counter[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_4_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_3_ ( .padio(d_vsync_counter[3]), .datain(vga_driver_unit_vsync_counter[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_3_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_2_ ( .padio(d_vsync_counter[2]), .datain(vga_driver_unit_vsync_counter[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_2_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_1_ ( .padio(d_vsync_counter[1]), .datain(vga_driver_unit_vsync_counter[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_1_.operation_mode = "output"; // @6:57 stratix_io d_vsync_counter_out_0_ ( .padio(d_vsync_counter[0]), .datain(vga_driver_unit_vsync_counter[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_counter_out_0_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_9_ ( .padio(d_hsync_counter[9]), .datain(vga_driver_unit_hsync_counter[9]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_9_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_8_ ( .padio(d_hsync_counter[8]), .datain(vga_driver_unit_hsync_counter[8]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_8_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_7_ ( .padio(d_hsync_counter[7]), .datain(vga_driver_unit_hsync_counter[7]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_7_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_6_ ( .padio(d_hsync_counter[6]), .datain(vga_driver_unit_hsync_counter[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_6_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_5_ ( .padio(d_hsync_counter[5]), .datain(vga_driver_unit_hsync_counter[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_5_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_4_ ( .padio(d_hsync_counter[4]), .datain(vga_driver_unit_hsync_counter[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_4_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_3_ ( .padio(d_hsync_counter[3]), .datain(vga_driver_unit_hsync_counter[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_3_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_2_ ( .padio(d_hsync_counter[2]), .datain(vga_driver_unit_hsync_counter[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_2_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_1_ ( .padio(d_hsync_counter[1]), .datain(vga_driver_unit_hsync_counter[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_1_.operation_mode = "output"; // @6:56 stratix_io d_hsync_counter_out_0_ ( .padio(d_hsync_counter[0]), .datain(vga_driver_unit_hsync_counter[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_counter_out_0_.operation_mode = "output"; // @6:55 stratix_io d_set_line_counter_out ( .padio(d_set_line_counter), .datain(vga_driver_unit_vsync_state[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_set_line_counter_out.operation_mode = "output"; // @6:55 stratix_io d_set_column_counter_out ( .padio(d_set_column_counter), .datain(vga_driver_unit_hsync_state[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_set_column_counter_out.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_8_ ( .padio(d_line_counter[8]), .datain(vga_driver_unit_line_counter_sig[8]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_8_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_7_ ( .padio(d_line_counter[7]), .datain(vga_driver_unit_line_counter_sig[7]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_7_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_6_ ( .padio(d_line_counter[6]), .datain(vga_driver_unit_line_counter_sig[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_6_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_5_ ( .padio(d_line_counter[5]), .datain(vga_driver_unit_line_counter_sig[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_5_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_4_ ( .padio(d_line_counter[4]), .datain(vga_driver_unit_line_counter_sig[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_4_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_3_ ( .padio(d_line_counter[3]), .datain(vga_driver_unit_line_counter_sig[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_3_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_2_ ( .padio(d_line_counter[2]), .datain(vga_driver_unit_line_counter_sig[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_2_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_1_ ( .padio(d_line_counter[1]), .datain(vga_driver_unit_line_counter_sig[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_1_.operation_mode = "output"; // @6:54 stratix_io d_line_counter_out_0_ ( .padio(d_line_counter[0]), .datain(vga_driver_unit_line_counter_sig[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_line_counter_out_0_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_9_ ( .padio(d_column_counter[9]), .datain(vga_driver_unit_column_counter_sig[9]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_9_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_8_ ( .padio(d_column_counter[8]), .datain(vga_driver_unit_column_counter_sig[8]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_8_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_7_ ( .padio(d_column_counter[7]), .datain(vga_driver_unit_column_counter_sig[7]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_7_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_6_ ( .padio(d_column_counter[6]), .datain(vga_driver_unit_column_counter_sig[6]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_6_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_5_ ( .padio(d_column_counter[5]), .datain(vga_driver_unit_column_counter_sig[5]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_5_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_4_ ( .padio(d_column_counter[4]), .datain(vga_driver_unit_column_counter_sig[4]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_4_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_3_ ( .padio(d_column_counter[3]), .datain(vga_driver_unit_column_counter_sig[3]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_3_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_2_ ( .padio(d_column_counter[2]), .datain(vga_driver_unit_column_counter_sig[2]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_2_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_1_ ( .padio(d_column_counter[1]), .datain(vga_driver_unit_column_counter_sig[1]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_1_.operation_mode = "output"; // @6:53 stratix_io d_column_counter_out_0_ ( .padio(d_column_counter[0]), .datain(vga_driver_unit_column_counter_sig[0]), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_column_counter_out_0_.operation_mode = "output"; // @6:52 stratix_io d_vsync_out ( .padio(d_vsync), .datain(vga_driver_unit_v_sync), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_vsync_out.operation_mode = "output"; // @6:52 stratix_io d_hsync_out ( .padio(d_hsync), .datain(vga_driver_unit_h_sync), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam d_hsync_out.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_13_ ( .padio(seven_seg_pin[13]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_13_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_12_ ( .padio(seven_seg_pin[12]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_12_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_11_ ( .padio(seven_seg_pin[11]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_11_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_10_ ( .padio(seven_seg_pin[10]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_10_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_9_ ( .padio(seven_seg_pin[9]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_9_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_8_ ( .padio(seven_seg_pin[8]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_8_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_7_ ( .padio(seven_seg_pin[7]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_7_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_6_ ( .padio(seven_seg_pin[6]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_6_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_5_ ( .padio(seven_seg_pin[5]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_5_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_4_ ( .padio(seven_seg_pin[4]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_4_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_3_ ( .padio(seven_seg_pin[3]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_3_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_2_ ( .padio(seven_seg_pin[2]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_2_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_out_1_ ( .padio(seven_seg_pin[1]), .datain(DELAY_RESET_next_un6_dly_counter_0_x), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_out_1_.operation_mode = "output"; // @6:50 stratix_io seven_seg_pin_tri_0_ ( .padio(seven_seg_pin[0]), .datain(VCC), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam seven_seg_pin_tri_0_.operation_mode = "output"; // @6:48 stratix_io vsync_pin_out ( .padio(vsync_pin), .datain(vga_driver_unit_v_sync), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam vsync_pin_out.operation_mode = "output"; // @6:47 stratix_io hsync_pin_out ( .padio(hsync_pin), .datain(vga_driver_unit_h_sync), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam hsync_pin_out.operation_mode = "output"; // @6:46 stratix_io b1_pin_out ( .padio(b1_pin), .datain(vga_control_unit_b), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam b1_pin_out.operation_mode = "output"; // @6:46 stratix_io b0_pin_out ( .padio(b0_pin), .datain(vga_control_unit_b), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam b0_pin_out.operation_mode = "output"; // @6:45 stratix_io g2_pin_out ( .padio(g2_pin), .datain(vga_control_unit_g), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam g2_pin_out.operation_mode = "output"; // @6:45 stratix_io g1_pin_out ( .padio(g1_pin), .datain(vga_control_unit_g), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam g1_pin_out.operation_mode = "output"; // @6:45 stratix_io g0_pin_out ( .padio(g0_pin), .datain(vga_control_unit_g), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam g0_pin_out.operation_mode = "output"; // @6:44 stratix_io r2_pin_out ( .padio(r2_pin), .datain(vga_control_unit_r), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam r2_pin_out.operation_mode = "output"; // @6:44 stratix_io r1_pin_out ( .padio(r1_pin), .datain(vga_control_unit_r), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam r1_pin_out.operation_mode = "output"; // @6:44 stratix_io r0_pin_out ( .padio(r0_pin), .datain(vga_control_unit_r), .oe(VCC), .outclk(GND), .outclkena(VCC), .inclk(GND), .inclkena(VCC), .areset(GND), .sreset(GND) ); defparam r0_pin_out.operation_mode = "output"; //@6:41 // @10:159 vga_driver vga_driver_unit ( .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]), .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]), .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]), .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]), .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]), .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]), .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]), .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]), .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]), .dly_counter_1(dly_counter[1]), .dly_counter_0(dly_counter[0]), .vsync_state_2(vga_driver_unit_vsync_state[2]), .vsync_state_5(vga_driver_unit_vsync_state[5]), .vsync_state_3(vga_driver_unit_vsync_state[3]), .vsync_state_6(vga_driver_unit_vsync_state[6]), .vsync_state_4(vga_driver_unit_vsync_state[4]), .vsync_state_1(vga_driver_unit_vsync_state[1]), .vsync_state_0(vga_driver_unit_vsync_state[0]), .hsync_state_2(vga_driver_unit_hsync_state[2]), .hsync_state_4(vga_driver_unit_hsync_state[4]), .hsync_state_0(vga_driver_unit_hsync_state[0]), .hsync_state_5(vga_driver_unit_hsync_state[5]), .hsync_state_1(vga_driver_unit_hsync_state[1]), .hsync_state_3(vga_driver_unit_hsync_state[3]), .hsync_state_6(vga_driver_unit_hsync_state[6]), .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]), .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]), .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]), .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]), .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]), .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]), .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]), .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]), .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]), .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]), .vsync_counter_9(vga_driver_unit_vsync_counter[9]), .vsync_counter_8(vga_driver_unit_vsync_counter[8]), .vsync_counter_7(vga_driver_unit_vsync_counter[7]), .vsync_counter_6(vga_driver_unit_vsync_counter[6]), .vsync_counter_5(vga_driver_unit_vsync_counter[5]), .vsync_counter_4(vga_driver_unit_vsync_counter[4]), .vsync_counter_3(vga_driver_unit_vsync_counter[3]), .vsync_counter_2(vga_driver_unit_vsync_counter[2]), .vsync_counter_1(vga_driver_unit_vsync_counter[1]), .vsync_counter_0(vga_driver_unit_vsync_counter[0]), .hsync_counter_9(vga_driver_unit_hsync_counter[9]), .hsync_counter_8(vga_driver_unit_hsync_counter[8]), .hsync_counter_7(vga_driver_unit_hsync_counter[7]), .hsync_counter_6(vga_driver_unit_hsync_counter[6]), .hsync_counter_5(vga_driver_unit_hsync_counter[5]), .hsync_counter_4(vga_driver_unit_hsync_counter[4]), .hsync_counter_3(vga_driver_unit_hsync_counter[3]), .hsync_counter_2(vga_driver_unit_hsync_counter[2]), .hsync_counter_1(vga_driver_unit_hsync_counter[1]), .hsync_counter_0(vga_driver_unit_hsync_counter[0]), .d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter), .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1), .un10_column_counter_siglt6_3(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3), .v_sync(vga_driver_unit_v_sync), .h_sync(vga_driver_unit_h_sync), .h_enable_sig(vga_driver_unit_h_enable_sig), .v_enable_sig(vga_driver_unit_v_enable_sig), .reset_pin_c(reset_pin_c), .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x), .d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter), .clk_pin_c(G_49) ); // @10:184 vga_control vga_control_unit ( .column_counter_sig_1(vga_driver_unit_column_counter_sig[3]), .column_counter_sig_7(vga_driver_unit_column_counter_sig[9]), .column_counter_sig_2(vga_driver_unit_column_counter_sig[4]), .column_counter_sig_0(vga_driver_unit_column_counter_sig[2]), .column_counter_sig_4(vga_driver_unit_column_counter_sig[6]), .column_counter_sig_3(vga_driver_unit_column_counter_sig[5]), .column_counter_sig_5(vga_driver_unit_column_counter_sig[7]), .column_counter_sig_6(vga_driver_unit_column_counter_sig[8]), .h_enable_sig(vga_driver_unit_h_enable_sig), .v_enable_sig(vga_driver_unit_v_enable_sig), .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1), .g(vga_control_unit_g), .un10_column_counter_siglt6_3(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3), .r(vga_control_unit_r), .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x), .clk_pin_c(G_49), .b(vga_control_unit_b) ); endmodule /* vga */