#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
#install: /opt/synplify/fpga_c200906
#OS: Linux 
#Hostname: ti14

#Implementation: rev_1

#Thu Oct 29 16:44:32 2009

$ Start of Compile
#Thu Oct 29 16:44:32 2009

Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved

@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
@N:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
@E: CD169 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd":43:2:43:16|Illegal declaration
1 error parsing file /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd
@END
1 error parsing file /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd
@END
@E|Parse errors encountered - exiting
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 29 16:44:32 2009

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