m255
K3
13
cModel Technology
Z0 d/homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre
T_opt
Z1 V2U0:J6hC1Tnnbgd;S6@lJ3
Z2 04 12 0 work vga_conf_pre 1
Z3 =1-0015609ed0a8-4ae9ba91-bb307-1314
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5b;42
Evga
Z7 w1256831373
Z8 DPx17 __model_tech/ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
Z9 DPx20 __model_tech/stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
Z10 DPx17 __model_tech/ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
Z11 DPx20 __model_tech/stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
Z12 DPx21 __model_tech/synplify 10 components 0 22 @=LFfPB8UiBPm8Y3jZ0Dj3
Z13 DPx17 __model_tech/ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
Z14 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
32
Z15 8/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vhm
Z16 F/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vhm
l0
L3515
Z17 V1IZ]kOHFNGODfLLmIAK4Z0
Z18 OE;C;6.5b;42
Z19 o-work work
Z20 tExplicit 1
Z21 !s100 ?je6GkYAl9C4bRI0=Vnj40
Abeh
Z22 DEx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 11 vga_control 0 22 iM8Slb>8F]WOeH5T<?2Z>3
Z23 DEx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 10 vga_driver 0 22 2[f_E^`<?L^bT>FDC^3Eh2
Z24 DEx20 __model_tech/stratix 10 stratix_io 0 22 8g8W4@DX]PW8dgJFjd5lT1
Z25 DEx20 __model_tech/stratix 13 stratix_lcell 0 22 aWl_l1>i5>lzY<SO57h5o1
R8
R9
R10
R11
R12
R13
R14
Z26 DEx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 3 vga 0 22 1IZ]kOHFNGODfLLmIAK4Z0
32
Z27 Mx8 17 __model_tech/ieee 14 std_logic_1164
Z28 Mx7 17 __model_tech/ieee 11 numeric_std
Z29 Mx6 21 __model_tech/synplify 10 components
Z30 Mx5 20 __model_tech/stratix 18 stratix_components
Z31 Mx4 17 __model_tech/ieee 12 vital_timing
Z32 Mx3 16 __model_tech/std 6 textio
Z33 Mx2 20 __model_tech/stratix 17 stratix_atom_pack
Z34 Mx1 17 __model_tech/ieee 16 vital_primitives
l3789
L3550
Z35 V2cBoj:8QWgn5dfF<=Eh9c1
R18
R19
R20
Z36 !s100 znZmGE;QZ8`Wbn]G4hZg^0
Cvga_conf_pre
R8
R9
R10
R11
R12
R13
R26
DAx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 10 vga_pre_tb 9 structure 22 l<iY:0YYNA^;NVLi]z;SV0
Z37 DPx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 7 vga_pak 0 22 HGKInm?j6h_E?hCL1=3Rf2
Z38 DPx17 __model_tech/ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z39 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R14
Z40 DEx57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 10 vga_pre_tb 0 22 lBieNQVlYd]7:AWzH`k4l2
32
Z41 Mx11 17 __model_tech/ieee 14 std_logic_1164
Z42 Mx10 17 __model_tech/ieee 18 std_logic_unsigned
Z43 Mx9 17 __model_tech/ieee 15 std_logic_arith
Z44 Mx8 57 /homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre/work 7 vga_pak
R28
R29
R30
R31
R32
R33
R34
Z45 astructure
Z46 evga_pre_tb
Z47 w1255952276
Z48 8/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pre_tb.vhd
Z49 F/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pre_tb.vhd
l0
L183
Z50 VaNjILBk^@SVk6Z1ONfaFf3
R18
R19
R20
Z51 !s100 [cbZKiGBUbhKkFd>g4kgG0
Evga_control
R7
R8
R9
R10
R11
R12
R13
R14
32
R15
R16
l0
L21
Z52 ViM8Slb>8F]WOeH5T<?2Z>3
R18
R19
R20
Z53 !s100 cARWILLA2jkIezceCfQhO0
Abeh
R25
R8
R9
R10
R11
R12
R13
R14
R22
32
R27
R28
R29
R30
R31
R32
R33
R34
l55
L42
Z54 VbU;JfUJ`P<QoiYU8d=Z`A2
R18
R19
R20
Z55 !s100 Un@URIhiDPMkb3K7nCBA]1
Evga_driver
R7
R8
R9
R10
R11
R12
R13
R14
32
R15
R16
l0
L288
Z56 V2[f_E^`<?L^bT>FDC^3Eh2
R18
R19
R20
Z57 !s100 H`[B7Qa3Tzi2R<9UOVVF`2
Abeh
Z58 DEx20 __model_tech/stratix 22 stratix_lcell_register 0 22 CWH?gQ078^87jkOg?o7Z63
Z59 DEx20 __model_tech/stratix 20 stratix_asynch_lcell 0 22 8j4Kk3oSOGiVF;kHH9H=I1
R25
R8
R9
R10
R11
R12
R13
R14
R23
32
R27
R28
R29
R30
R31
R32
R33
R34
l487
L358
Z60 VQ6GQEDImWUnHG8g>LY9A]1
R18
R19
R20
Z61 !s100 I:B2OkcJZiMG=N]jWY;Ri1
Pvga_pak
R38
R39
R14
32
Z62 Mx3 17 __model_tech/ieee 14 std_logic_1164
Mx2 17 __model_tech/ieee 18 std_logic_unsigned
Z63 Mx1 17 __model_tech/ieee 15 std_logic_arith
Z64 w1256830367
Z65 8/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd
Z66 F/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd
l0
L35
Z67 VHGKInm?j6h_E?hCL1=3Rf2
R18
R19
R20
Z68 !s100 cALhF4me<zNWYz_BWPd?70
Evga_pre_tb
R47
R37
R38
R39
R14
32
R48
R49
l0
L37
Z69 VlBieNQVlYd]7:AWzH`k4l2
R18
R19
R20
Z70 !s100 E`OC=4TKQQZR9AW6:_aWL3
Astructure
R8
R9
R10
R11
R12
R13
R26
R37
R38
R39
R14
R40
32
R41
R42
R43
R44
R28
R29
R30
R31
R32
R33
R34
l97
L45
Z71 Vl<iY:0YYNA^;NVLi]z;SV0
R18
R19
R20
Z72 !s100 ==[?_XkYb5@TcOP8^IKLZ3