Analysis & Synthesis report for vga Thu Oct 29 16:59:53 2009 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. General Register Statistics 8. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Thu Oct 29 16:59:53 2009 ; ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; ; Revision Name ; vga ; ; Top-level Entity Name ; vga ; ; Family ; Stratix ; ; Total logic elements ; 143 ; ; Total pins ; 91 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; DSP block 9-bit elements ; 0 ; ; Total PLLs ; 0 ; ; Total DLLs ; 0 ; +-----------------------------+------------------------------------------+ +----------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP1S25F672C6 ; ; ; Top-level entity name ; vga ; vga ; ; Family name ; Stratix ; Stratix II ; ; Type of Retiming Performed During Resynthesis ; Full ; ; ; Resynthesis Optimization Effort ; Normal ; ; ; Physical Synthesis Level for Resynthesis ; Normal ; ; ; Use Generated Physical Constraints File ; On ; ; ; Use smart compilation ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Parallel Synthesis ; Off ; Off ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; +----------------------------------------------------------------+--------------------+--------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ ; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ; +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ +-------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+---------+ ; Resource ; Usage ; +---------------------------------------------+---------+ ; Total logic elements ; 143 ; ; -- Combinational with no register ; 81 ; ; -- Register only ; 3 ; ; -- Combinational with a register ; 59 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 53 ; ; -- 3 input functions ; 32 ; ; -- 2 input functions ; 54 ; ; -- 1 input functions ; 1 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 109 ; ; -- arithmetic mode ; 34 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 48 ; ; -- asynchronous clear/load mode ; 3 ; ; ; ; ; Total registers ; 62 ; ; Total logic cells in carry chains ; 40 ; ; I/O pins ; 91 ; ; Maximum fan-out node ; clk_pin ; ; Maximum fan-out ; 63 ; ; Total fan-out ; 666 ; ; Average fan-out ; 2.85 ; +---------------------------------------------+---------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ ; |vga ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga ; work ; ; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ; ; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga|vga_driver:vga_driver_unit ; work ; +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 62 ; ; Number of registers using Synchronous Clear ; 48 ; ; Number of registers using Synchronous Load ; 20 ; ; Number of registers using Asynchronous Clear ; 3 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 12 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Thu Oct 29 16:59:47 2009 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm Info: Found entity 1: vga_driver Info: Found entity 2: vga_control Info: Found entity 3: vga Info: Elaborating entity "vga" for the top level hierarchy Info: Elaborating entity "vga_driver" for hierarchy "vga_driver:vga_driver_unit" Info: Elaborating entity "vga_control" for hierarchy "vga_control:vga_control_unit" Info: Implemented 234 device resources after synthesis - the final resource count might be different Info: Implemented 2 input pins Info: Implemented 89 output pins Info: Implemented 143 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings Info: Peak virtual memory: 185 megabytes Info: Processing ended: Thu Oct 29 16:59:53 2009 Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:02