Flow report for vga
Thu Oct 29 17:00:56 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Thu Oct 29 17:00:56 2009    ;
; Quartus II Version       ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name            ; vga                                      ;
; Top-level Entity Name    ; vga                                      ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S25F672C6                             ;
; Timing Models            ; Final                                    ;
; Met timing requirements  ; Yes                                      ;
; Total logic elements     ; 141 / 25,660 ( < 1 % )                   ;
; Total pins               ; 91 / 474 ( 19 % )                        ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0 / 1,944,576 ( 0 % )                    ;
; DSP block 9-bit elements ; 0 / 80 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 10/29/2009 16:59:51 ;
; Main task         ; Compilation         ;
; Revision Name     ; vga                 ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                      ;
+------------------------------------+-----------------------------+---------------+-------------+----------------------+
; Assignment Name                    ; Value                       ; Default Value ; Entity Name ; Section Id           ;
+------------------------------------+-----------------------------+---------------+-------------+----------------------+
; COMPILER_SIGNATURE_ID              ; 91815334056.125683199105130 ; --            ; --          ; --                   ;
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL    ; Synplify Pro                ; <None>        ; --          ; --                   ;
; EDA_INPUT_DATA_FORMAT              ; Vqm                         ; --            ; --          ; eda_design_synthesis ;
; EDA_LMF_FILE                       ; synplcty.lmf                ; --            ; --          ; eda_design_synthesis ;
; EDA_OUTPUT_DATA_FORMAT             ; Vhdl                        ; --            ; --          ; eda_simulation       ;
; EDA_SIMULATION_TOOL                ; ModelSim-Altera (VHDL)      ; <None>        ; --          ; --                   ;
; MAX_CORE_JUNCTION_TEMP             ; 85                          ; --            ; --          ; --                   ;
; MIN_CORE_JUNCTION_TEMP             ; 0                           ; --            ; --          ; --                   ;
; PARTITION_COLOR                    ; 16764057                    ; --            ; --          ; Top                  ;
; PARTITION_NETLIST_TYPE             ; SOURCE                      ; --            ; --          ; Top                  ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                         ; --            ; --          ; eda_blast_fpga       ;
+------------------------------------+-----------------------------+---------------+-------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:05     ; 1.0                     ; --                  ; 00:00:01                           ;
; Fitter                  ; 00:00:30     ; 1.1                     ; --                  ; 00:00:28                           ;
; Assembler               ; 00:00:18     ; 1.0                     ; --                  ; 00:00:18                           ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ; --                  ; 00:00:00                           ;
; EDA Netlist Writer      ; 00:00:01     ; 1.0                     ; --                  ; 00:00:01                           ;
; Total                   ; 00:00:55     ; --                      ; --                  ; 00:00:48                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


+------------------------------------------------------------------------------------+
; Flow OS Summary                                                                    ;
+-------------------------+------------------+---------+------------+----------------+
; Module Name             ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------+------------+----------------+
; Analysis & Synthesis    ; ti14             ; Red Hat ; 5          ; x86_64         ;
; Fitter                  ; ti14             ; Red Hat ; 5          ; x86_64         ;
; Assembler               ; ti14             ; Red Hat ; 5          ; x86_64         ;
; Classic Timing Analyzer ; ti14             ; Red Hat ; 5          ; x86_64         ;
; EDA Netlist Writer      ; ti14             ; Red Hat ; 5          ; x86_64         ;
+-------------------------+------------------+---------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga
quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga
quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga