#-- Synplicity, Inc.
#-- Version C-2009.06
#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/vga.prj
#-- Written on Wed Oct 21 17:34:16 2009


#project files
add_file -vhdl -lib work "../src/vga_pak.vhd"
add_file -vhdl -lib work "../src/vga_ent.vhd"
add_file -vhdl -lib work "../src/vga_arc.vhd"
add_file -vhdl -lib work "../src/board_driver_ent.vhd"
add_file -vhdl -lib work "../src/board_driver_arc.vhd"
add_file -vhdl -lib work "../src/vga_control_ent.vhd"
add_file -vhdl -lib work "../src/vga_control_arc.vhd"
add_file -vhdl -lib work "../src/vga_driver_ent.vhd"
add_file -vhdl -lib work "../src/vga_driver_arc.vhd"


#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology STRATIX
set_option -part EP1S25
set_option -package FC672
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "vga"

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# mapper_options
set_option -frequency 25.175
set_option -write_verilog 0
set_option -write_vhdl 1

# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 500
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -quartus_version 9.0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./rev_1/vga.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "rev_1"