@TM:1256138598
@N:  :"":0:0:0:-1|Running in logic synthesis mode without enhanced optimization
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MF257 :"":0:0:0:-1|Gated clock conversion enabled 
@N: MF276 :"":0:0:0:-1|Gated clock conversion enabled, but no gated clocks found in design 
@N: MF333 :"":0:0:0:-1|Generated clock conversion enabled, but no generated clocks found in design 
@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1256138589
@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|M
@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|M
@TM:1256138598
@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|M
@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|M
@TM:1256138589
@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|M
@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|M
@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|M
@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|M