------------------------------------------------------------------------------- -- Title : vga architecture -- Project : LU Digital Design ------------------------------------------------------------------------------- -- File : vga.vhd -- Author : Thomas Handl -- Company : TU Wien -- Created : 2004-04-07 -- Last update: 2006-02-24 ------------------------------------------------------------------------------- -- Description: arch of top level module, the sub-modules are connected here ------------------------------------------------------------------------------- -- Copyright (c) 2004 TU Wien ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2004-04-07 1.0 handl Created -- 2006-02-24 2.0 ST revised ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- LIBRARIES ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use work.vga_pak.all; -- include package ------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------- architecture behav of vga is attribute syn_preserve : boolean; attribute syn_preserve of behav : architecture is true; ------------------------------------------------------------------------------- -- component declarations for the modules ------------------------------------------------------------------------------- component vga_driver port ( clk : in std_logic; reset : in std_logic; column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); h_enable : out std_logic; v_enable : out std_logic; hsync : out std_logic; vsync : out std_logic; d_hsync_state : out hsync_state_type; d_vsync_state : out vsync_state_type; d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); d_set_hsync_counter : out std_logic; d_set_vsync_counter : out std_logic; d_set_column_counter : out std_logic; d_set_line_counter : out std_logic); end component; component vga_control port ( clk : in std_logic; reset : in std_logic; column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); h_enable : in std_logic; v_enable : in std_logic; toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); toggle : out std_logic; r, g, b : out std_logic ); end component; component board_driver port ( reset : in std_logic; seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)); end component; -- declare signals needed for internal wiring of these components later signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); signal h_enable_sig : std_logic; signal v_enable_sig : std_logic; signal r_sig, g_sig, b_sig : std_logic; signal hsync_sig, vsync_sig : std_logic; -- declare signals needed for prolongation of reset signal dly_counter : std_logic_vector(1 downto 0); signal dly_counter_next : std_logic_vector(1 downto 0); constant MAX_DLY : std_logic_vector(1 downto 0) := "11"; signal reset_dly : std_logic; -- signal safe_reset : std_logic; ------------------------------------------------------------------------------- -- prolong duration of reset to prevent glitches at power-up ------------------------------------------------------------------------------- begin DELAY_RESET_syn : process(clk_pin) -- synchronous capture begin if clk_pin'event and clk_pin = '1' then -- upon rising clock dly_counter <= dly_counter_next; -- ... capture new counter value end if; end process; DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic begin if reset_pin = RES_ACT then -- upon reset dly_counter_next <= (others => '0'); -- ...clear dly counter elsif dly_counter < MAX_DLY then -- if no oflo dly_counter_next <= dly_counter + '1'; -- ...increment dly counter else dly_counter_next <= dly_counter; -- freeze dly counter when oflo end if; end process; DELAY_RESET_out: process(dly_counter) begin if dly_counter < MAX_DLY then -- until dly counter reaches maximum reset_dly <= RES_ACT; -- ...activate delayed reset signal else -- upon counter oflo reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset end if; end process; COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal begin if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input safe_reset <= RES_ACT; else safe_reset <= not(RES_ACT); end if; end process; ------------------------------------------------------------------------------- -- instantiate the components and connect to internal and external signals ------------------------------------------------------------------------------- board_driver_unit : board_driver port map ( reset => safe_reset, seven_seg => seven_seg_pin); vga_driver_unit : vga_driver port map ( clk => clk_pin, reset => safe_reset, column_counter => column_counter_sig, line_counter => line_counter_sig, h_enable => h_enable_sig, v_enable => v_enable_sig, hsync => hsync_sig, vsync => vsync_sig, d_hsync_state => d_hsync_state, d_vsync_state => d_vsync_state, d_hsync_counter => d_hsync_counter, d_vsync_counter => d_vsync_counter, d_set_hsync_counter => d_set_hsync_counter, d_set_vsync_counter => d_set_vsync_counter, d_set_column_counter => d_set_column_counter, d_set_line_counter => d_set_line_counter); -- make the wiring for hsync and vsync pins -- (pin is output only => internal _sig version required to allow readback of signal) vsync_pin <= vsync_sig; hsync_pin <= hsync_sig; vga_control_unit : vga_control port map ( clk => clk_pin, reset => safe_reset, column_counter => column_counter_sig, line_counter => line_counter_sig, h_enable => h_enable_sig, v_enable => v_enable_sig, toggle_counter => d_toggle_counter, toggle => d_toggle, r => r_sig, g => g_sig, b => b_sig); -- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode") r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig; g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig; b0_pin <= b_sig; b1_pin <= b_sig; -- make extra pin connections for debug signals d_hsync <= hsync_sig; -- make duplicate of signal for debug connector d_vsync <= vsync_sig; -- make duplicate of signal for debug connector d_column_counter <= column_counter_sig; d_line_counter <= line_counter_sig; d_h_enable <= h_enable_sig; d_v_enable <= v_enable_sig; d_r <= r_sig; d_g <= g_sig; d_b <= b_sig; d_state_clk <= clk_pin; -- make duplicate of signal for debug connector end behav; ------------------------------------------------------------------------------- -- END ARCHITECTURE -------------------------------------------------------------------------------