m255
K3
13
cModel Technology
Z0 d/homes/burban/didelu/dide_16/bsp2/Designflow/sim/post
T_opt
Z1 Vb_bYkEddIfG5^Q]G^IlDX2
Z2 04 12 0 work vga_conf_pos 1
Z3 =1-0015609ecc30-4ae84603-b3cb8-6ed0
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5b;42
T_opt1
VodUUKE^RkJgfPc_chPak<0
R2
Z7 =1-0015609ecc30-4ae84790-db1bd-6f83
Z8 o-quiet -auto_acc_if_foreign -work work -sdftyp /vga_unit=/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo -suppress 1948
Z9 n@_opt1
R6
Evga
Z10 w1256735995
Z11 DPx4 ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
Z12 DPx7 stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
Z13 DPx4 ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
Z14 DPx7 stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
Z15 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
Z16 8/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho
Z17 F/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho
l0
L33
Z18 Va^A3`oj7W2X29O[KC68:E3
Z19 OE;C;6.5b;42
32
Z20 o-work work
Z21 tExplicit 1
Z22 !s100 JmIRf5hghCim]`W8beHGP0
Astructure
R11
R12
R13
R14
R15
Z23 DEx4 work 3 vga 0 22 a^A3`oj7W2X29O[KC68:E3
l339
L71
Z24 Vk7P8U19m0:Dz967C1Akbk0
R19
32
Z25 Mx5 4 ieee 14 std_logic_1164
Z26 Mx4 7 stratix 18 stratix_components
Z27 Mx3 4 ieee 12 vital_timing
Z28 Mx2 7 stratix 17 stratix_atom_pack
Z29 Mx1 4 ieee 16 vital_primitives
R20
R21
Z30 !s100 AMfjh:;COKIUMWYOS[cBn1
Cvga_conf_pos
Z31 astructure
Z32 evga_pos_tb
R11
R12
R13
R14
R23
Z33 DAx4 work 10 vga_pos_tb 9 structure 22 2H0Zl8k[9mYf8bN=NCbeH0
Z34 DPx4 work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
Z35 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z36 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R15
Z37 DEx4 work 10 vga_pos_tb 0 22 WYVDk8:IlXF:G=gkK18_k0
Z38 w1255952276
Z39 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
Z40 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
l0
L190
Z41 V0i2Wgcf;160Sh<_O1]Yd91
R19
32
Z42 Mx8 4 ieee 14 std_logic_1164
Z43 Mx7 4 ieee 18 std_logic_unsigned
Z44 Mx6 4 ieee 15 std_logic_arith
Z45 Mx5 4 work 7 vga_pak
R26
R27
R28
R29
R20
R21
Z46 !s100 5AFP2EDWmkBg2TkYkScac0
Pvga_pak
R35
R36
R15
R38
Z47 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
Z48 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
l0
L35
Z49 VHkmzP=gd;mD@MOhh4AYKl3
R19
32
Z50 Mx3 4 ieee 14 std_logic_1164
Z51 Mx2 4 ieee 18 std_logic_unsigned
Z52 Mx1 4 ieee 15 std_logic_arith
R20
R21
Z53 !s100 VL:Z2?FJISz9N5>XaK:5k0
Evga_pos_tb
R38
R34
R35
R36
R15
R39
R40
l0
L37
Z54 VWYVDk8:IlXF:G=gkK18_k0
R19
32
R20
R21
Z55 !s100 ?:YH_R3N79K7J0L`IT49_0
Astructure
R34
R35
R36
R15
R37
l101
L45
Z56 V2H0Zl8k[9mYf8bN=NCbeH0
R19
32
Z57 Mx4 4 ieee 14 std_logic_1164
Z58 Mx3 4 ieee 18 std_logic_unsigned
Z59 Mx2 4 ieee 15 std_logic_arith
Z60 Mx1 4 work 7 vga_pak
R20
R21
Z61 !s100 T_8dcPYGCmK@^6g;3L5;b0