m255
K3
13
cModel Technology
Z0 d/homes/burban/didelu/dide_16/bsp2/Designflow/sim/post
T_opt
Z1 Vb_bYkEddIfG5^Q]G^IlDX2
Z2 04 12 0 work vga_conf_pos 1
Z3 =1-0015609ecc30-4ae84603-b3cb8-6ed0
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5b;42
T_opt1
Z7 VodUUKE^RkJgfPc_chPak<0
R2
Z8 =1-0015609ecc30-4ae84790-db1bd-6f83
Z9 o-quiet -auto_acc_if_foreign -work work -sdftyp /vga_unit=/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo -suppress 1948
Z10 n@_opt1
R6
Evga
Z11 w1256735995
Z12 DPx17 __model_tech/ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
Z13 DPx20 __model_tech/stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
Z14 DPx17 __model_tech/ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
Z15 DPx20 __model_tech/stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
Z16 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
32
Z17 8/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho
Z18 F/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho
l0
L33
Z19 Va^A3`oj7W2X29O[KC68:E3
Z20 OE;C;6.5b;42
Z21 o-work work
Z22 tExplicit 1
Z23 !s100 JmIRf5hghCim]`W8beHGP0
Astructure
Z24 DEx20 __model_tech/stratix 13 stratix_lcell 0 22 aWl_l1>i5>lzY<SO57h5o1
Z25 DEx20 __model_tech/stratix 10 stratix_io 0 22 8g8W4@DX]PW8dgJFjd5lT1
R12
R13
R14
R15
R16
Z26 DEx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 3 vga 0 22 a^A3`oj7W2X29O[KC68:E3
32
Z27 Mx6 17 __model_tech/ieee 14 std_logic_1164
Z28 Mx5 20 __model_tech/stratix 18 stratix_components
Z29 Mx4 17 __model_tech/ieee 12 vital_timing
Z30 Mx3 16 __model_tech/std 6 textio
Z31 Mx2 20 __model_tech/stratix 17 stratix_atom_pack
Z32 Mx1 17 __model_tech/ieee 16 vital_primitives
l339
L71
Z33 Vk7P8U19m0:Dz967C1Akbk0
R20
R21
R22
Z34 !s100 AMfjh:;COKIUMWYOS[cBn1
Cvga_conf_pos
R12
R13
R14
R15
R26
DAx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 10 vga_pos_tb 9 structure 22 2H0Zl8k[9mYf8bN=NCbeH0
Z35 DPx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
Z36 DPx17 __model_tech/ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z37 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R16
Z38 DEx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 10 vga_pos_tb 0 22 WYVDk8:IlXF:G=gkK18_k0
32
Z39 Mx9 17 __model_tech/ieee 14 std_logic_1164
Z40 Mx8 17 __model_tech/ieee 18 std_logic_unsigned
Z41 Mx7 17 __model_tech/ieee 15 std_logic_arith
Z42 Mx6 58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 7 vga_pak
R28
R29
R30
R31
R32
Z43 astructure
Z44 evga_pos_tb
Z45 w1255952276
Z46 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
Z47 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
l0
L190
Z48 V0i2Wgcf;160Sh<_O1]Yd91
R20
R21
R22
Z49 !s100 5AFP2EDWmkBg2TkYkScac0
Pvga_pak
R36
R37
R16
32
Z50 Mx3 17 __model_tech/ieee 14 std_logic_1164
Mx2 17 __model_tech/ieee 18 std_logic_unsigned
Z51 Mx1 17 __model_tech/ieee 15 std_logic_arith
R45
Z52 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
Z53 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
l0
L35
Z54 VHkmzP=gd;mD@MOhh4AYKl3
R20
R21
R22
Z55 !s100 VL:Z2?FJISz9N5>XaK:5k0
Evga_pos_tb
R45
R35
R36
R37
R16
32
R46
R47
l0
L37
Z56 VWYVDk8:IlXF:G=gkK18_k0
R20
R21
R22
Z57 !s100 ?:YH_R3N79K7J0L`IT49_0
Astructure
R12
R13
R14
R15
R26
R35
R36
R37
R16
R38
32
R39
R40
R41
R42
R28
R29
R30
R31
R32
l101
L45
Z58 V2H0Zl8k[9mYf8bN=NCbeH0
R20
R21
R22
Z59 !s100 T_8dcPYGCmK@^6g;3L5;b0