m255
K3
13
cModel Technology
Z0 d/homes/burban/didelu/dide_16/bsp2/Designflow/sim/post
T_opt
Z1 Vb_bYkEddIfG5^Q]G^IlDX2
Z2 04 12 0 work vga_conf_pos 1
Z3 =1-0015609ecc30-4ae84603-b3cb8-6ed0
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5b;42
Evga
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32
Z13 8/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho
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l0
L33
Z15 Va^A3`oj7W2X29O[KC68:E3
Z16 OE;C;6.5b;42
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Astructure
Z20 DEx20 __model_tech/stratix 22 stratix_lcell_register 0 22 CWH?gQ078^87jkOg?o7Z63
Z21 DEx20 __model_tech/stratix 20 stratix_asynch_lcell 0 22 8j4Kk3oSOGiVF;kHH9H=I1
Z22 DEx20 __model_tech/stratix 13 stratix_lcell 0 22 aWl_l1>i5>lzY<SO57h5o1
Z23 DEx20 __model_tech/stratix 10 stratix_io 0 22 8g8W4@DX]PW8dgJFjd5lT1
R8
R9
R10
R11
R12
Z24 DEx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 3 vga 0 22 a^A3`oj7W2X29O[KC68:E3
32
Z25 Mx6 17 __model_tech/ieee 14 std_logic_1164
Z26 Mx5 20 __model_tech/stratix 18 stratix_components
Z27 Mx4 17 __model_tech/ieee 12 vital_timing
Z28 Mx3 16 __model_tech/std 6 textio
Z29 Mx2 20 __model_tech/stratix 17 stratix_atom_pack
Z30 Mx1 17 __model_tech/ieee 16 vital_primitives
l339
L71
Z31 Vk7P8U19m0:Dz967C1Akbk0
R16
R17
R18
Z32 !s100 AMfjh:;COKIUMWYOS[cBn1
Cvga_conf_pos
R8
R9
R10
R11
R24
DAx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 10 vga_pos_tb 9 structure 22 2H0Zl8k[9mYf8bN=NCbeH0
Z33 DPx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
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Z35 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R12
Z36 DEx58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 10 vga_pos_tb 0 22 WYVDk8:IlXF:G=gkK18_k0
32
Z37 Mx9 17 __model_tech/ieee 14 std_logic_1164
Z38 Mx8 17 __model_tech/ieee 18 std_logic_unsigned
Z39 Mx7 17 __model_tech/ieee 15 std_logic_arith
Z40 Mx6 58 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/post/work 7 vga_pak
R26
R27
R28
R29
R30
Z41 astructure
Z42 evga_pos_tb
Z43 w1255952276
Z44 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
Z45 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pos_tb.vhd
l0
L190
Z46 V0i2Wgcf;160Sh<_O1]Yd91
R16
R17
R18
Z47 !s100 5AFP2EDWmkBg2TkYkScac0
Pvga_pak
R34
R35
R12
32
Z48 Mx3 17 __model_tech/ieee 14 std_logic_1164
Mx2 17 __model_tech/ieee 18 std_logic_unsigned
Z49 Mx1 17 __model_tech/ieee 15 std_logic_arith
R43
Z50 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
Z51 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
l0
L35
Z52 VHkmzP=gd;mD@MOhh4AYKl3
R16
R17
R18
Z53 !s100 VL:Z2?FJISz9N5>XaK:5k0
Evga_pos_tb
R43
R33
R34
R35
R12
32
R44
R45
l0
L37
Z54 VWYVDk8:IlXF:G=gkK18_k0
R16
R17
R18
Z55 !s100 ?:YH_R3N79K7J0L`IT49_0
Astructure
R8
R9
R10
R11
R24
R33
R34
R35
R12
R36
32
R37
R38
R39
R40
R26
R27
R28
R29
R30
l101
L45
Z56 V2H0Zl8k[9mYf8bN=NCbeH0
R16
R17
R18
Z57 !s100 T_8dcPYGCmK@^6g;3L5;b0