bsp2/Designflow/syn/rev_1/vga.vqm

   1 //
   2 // Written by Synplify
   3 // Product Version "C-2009.06"
   4 // Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 // Wed Oct 21 17:26:36 2009
   6 //
   7 // Source file index table:
   8 // Object locations will have the form <file>:<line>
   9 // file 0 "noname"
  10 // file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd "
  11 // file 2 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd "
  12 // file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd "
  13 // file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd "
  14 // file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd "
  15 // file 6 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd "
  16 // file 7 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd "
  17 // file 8 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd "
  18 // file 9 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd "
  19 // file 10 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd "
  20 // file 11 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd "
  21 // file 12 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd "
  22 // file 13 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd "
  23
  24 // VQM4.1+
  25 module vga_driver (
  26   line_counter_sig_0,
  27   line_counter_sig_1,
  28   line_counter_sig_2,
  29   line_counter_sig_3,
  30   line_counter_sig_4,
  31   line_counter_sig_5,
  32   line_counter_sig_6,
  33   line_counter_sig_7,
  34   line_counter_sig_8,
  35   dly_counter_1,
  36   dly_counter_0,
  37   vsync_state_2,
  38   vsync_state_5,
  39   vsync_state_3,
  40   vsync_state_6,
  41   vsync_state_4,
  42   vsync_state_1,
  43   vsync_state_0,
  44   hsync_state_2,
  45   hsync_state_4,
  46   hsync_state_0,
  47   hsync_state_5,
  48   hsync_state_1,
  49   hsync_state_3,
  50   hsync_state_6,
  51   column_counter_sig_0,
  52   column_counter_sig_1,
  53   column_counter_sig_2,
  54   column_counter_sig_3,
  55   column_counter_sig_4,
  56   column_counter_sig_5,
  57   column_counter_sig_6,
  58   column_counter_sig_7,
  59   column_counter_sig_8,
  60   column_counter_sig_9,
  61   vsync_counter_9,
  62   vsync_counter_8,
  63   vsync_counter_7,
  64   vsync_counter_6,
  65   vsync_counter_5,
  66   vsync_counter_4,
  67   vsync_counter_3,
  68   vsync_counter_2,
  69   vsync_counter_1,
  70   vsync_counter_0,
  71   hsync_counter_9,
  72   hsync_counter_8,
  73   hsync_counter_7,
  74   hsync_counter_6,
  75   hsync_counter_5,
  76   hsync_counter_4,
  77   hsync_counter_3,
  78   hsync_counter_2,
  79   hsync_counter_1,
  80   hsync_counter_0,
  81   d_set_vsync_counter,
  82   v_sync,
  83   h_sync,
  84   h_enable_sig,
  85   v_enable_sig,
  86   reset_pin_c,
  87   un6_dly_counter_0_x,
  88   d_set_hsync_counter,
  89   clk_pin_c
  90 )
  91 ;
  92 output line_counter_sig_0 ;
  93 output line_counter_sig_1 ;
  94 output line_counter_sig_2 ;
  95 output line_counter_sig_3 ;
  96 output line_counter_sig_4 ;
  97 output line_counter_sig_5 ;
  98 output line_counter_sig_6 ;
  99 output line_counter_sig_7 ;
 100 output line_counter_sig_8 ;
 101 input dly_counter_1 ;
 102 input dly_counter_0 ;
 103 output vsync_state_2 ;
 104 output vsync_state_5 ;
 105 output vsync_state_3 ;
 106 output vsync_state_6 ;
 107 output vsync_state_4 ;
 108 output vsync_state_1 ;
 109 output vsync_state_0 ;
 110 output hsync_state_2 ;
 111 output hsync_state_4 ;
 112 output hsync_state_0 ;
 113 output hsync_state_5 ;
 114 output hsync_state_1 ;
 115 output hsync_state_3 ;
 116 output hsync_state_6 ;
 117 output column_counter_sig_0 ;
 118 output column_counter_sig_1 ;
 119 output column_counter_sig_2 ;
 120 output column_counter_sig_3 ;
 121 output column_counter_sig_4 ;
 122 output column_counter_sig_5 ;
 123 output column_counter_sig_6 ;
 124 output column_counter_sig_7 ;
 125 output column_counter_sig_8 ;
 126 output column_counter_sig_9 ;
 127 output vsync_counter_9 ;
 128 output vsync_counter_8 ;
 129 output vsync_counter_7 ;
 130 output vsync_counter_6 ;
 131 output vsync_counter_5 ;
 132 output vsync_counter_4 ;
 133 output vsync_counter_3 ;
 134 output vsync_counter_2 ;
 135 output vsync_counter_1 ;
 136 output vsync_counter_0 ;
 137 output hsync_counter_9 ;
 138 output hsync_counter_8 ;
 139 output hsync_counter_7 ;
 140 output hsync_counter_6 ;
 141 output hsync_counter_5 ;
 142 output hsync_counter_4 ;
 143 output hsync_counter_3 ;
 144 output hsync_counter_2 ;
 145 output hsync_counter_1 ;
 146 output hsync_counter_0 ;
 147 output d_set_vsync_counter ;
 148 output v_sync ;
 149 output h_sync ;
 150 output h_enable_sig ;
 151 output v_enable_sig ;
 152 input reset_pin_c ;
 153 output un6_dly_counter_0_x ;
 154 output d_set_hsync_counter ;
 155 input clk_pin_c ;
 156 wire line_counter_sig_0 ;
 157 wire line_counter_sig_1 ;
 158 wire line_counter_sig_2 ;
 159 wire line_counter_sig_3 ;
 160 wire line_counter_sig_4 ;
 161 wire line_counter_sig_5 ;
 162 wire line_counter_sig_6 ;
 163 wire line_counter_sig_7 ;
 164 wire line_counter_sig_8 ;
 165 wire dly_counter_1 ;
 166 wire dly_counter_0 ;
 167 wire vsync_state_2 ;
 168 wire vsync_state_5 ;
 169 wire vsync_state_3 ;
 170 wire vsync_state_6 ;
 171 wire vsync_state_4 ;
 172 wire vsync_state_1 ;
 173 wire vsync_state_0 ;
 174 wire hsync_state_2 ;
 175 wire hsync_state_4 ;
 176 wire hsync_state_0 ;
 177 wire hsync_state_5 ;
 178 wire hsync_state_1 ;
 179 wire hsync_state_3 ;
 180 wire hsync_state_6 ;
 181 wire column_counter_sig_0 ;
 182 wire column_counter_sig_1 ;
 183 wire column_counter_sig_2 ;
 184 wire column_counter_sig_3 ;
 185 wire column_counter_sig_4 ;
 186 wire column_counter_sig_5 ;
 187 wire column_counter_sig_6 ;
 188 wire column_counter_sig_7 ;
 189 wire column_counter_sig_8 ;
 190 wire column_counter_sig_9 ;
 191 wire vsync_counter_9 ;
 192 wire vsync_counter_8 ;
 193 wire vsync_counter_7 ;
 194 wire vsync_counter_6 ;
 195 wire vsync_counter_5 ;
 196 wire vsync_counter_4 ;
 197 wire vsync_counter_3 ;
 198 wire vsync_counter_2 ;
 199 wire vsync_counter_1 ;
 200 wire vsync_counter_0 ;
 201 wire hsync_counter_9 ;
 202 wire hsync_counter_8 ;
 203 wire hsync_counter_7 ;
 204 wire hsync_counter_6 ;
 205 wire hsync_counter_5 ;
 206 wire hsync_counter_4 ;
 207 wire hsync_counter_3 ;
 208 wire hsync_counter_2 ;
 209 wire hsync_counter_1 ;
 210 wire hsync_counter_0 ;
 211 wire d_set_vsync_counter ;
 212 wire v_sync ;
 213 wire h_sync ;
 214 wire h_enable_sig ;
 215 wire v_enable_sig ;
 216 wire reset_pin_c ;
 217 wire un6_dly_counter_0_x ;
 218 wire d_set_hsync_counter ;
 219 wire clk_pin_c ;
 220 wire [8:0] hsync_counter_cout;
 221 wire [8:0] vsync_counter_cout;
 222 wire [9:1] un2_column_counter_next_combout;
 223 wire [9:1] un1_line_counter_sig_combout;
 224 wire [7:1] un1_line_counter_sig_cout;
 225 wire [1:1] un1_line_counter_sig_a_cout;
 226 wire [7:0] un2_column_counter_next_cout;
 227 wire hsync_counter_next_1_sqmuxa ;
 228 wire G_2_i ;
 229 wire un9_hsync_counterlt9 ;
 230 wire vsync_counter_next_1_sqmuxa ;
 231 wire G_16_i ;
 232 wire un9_vsync_counterlt9 ;
 233 wire un10_column_counter_siglto9 ;
 234 wire column_counter_next_0_sqmuxa_1_1 ;
 235 wire vsync_state_3_iv_0_0__g0_0_a3_0 ;
 236 wire vsync_state_next_2_sqmuxa ;
 237 wire un12_vsync_counter_7 ;
 238 wire un13_vsync_counter_4 ;
 239 wire un10_line_counter_siglto8 ;
 240 wire line_counter_next_0_sqmuxa_1_1 ;
 241 wire v_enable_sig_1_0_0_0_g0_i_o4 ;
 242 wire h_enable_sig_1_0_0_0_g0_i_o4 ;
 243 wire h_sync_1_0_0_0_g1 ;
 244 wire v_sync_1_0_0_0_g1 ;
 245 wire un14_vsync_counter_8 ;
 246 wire hsync_state_3_0_0_0__g0_0 ;
 247 wire un10_hsync_counter_3 ;
 248 wire un10_hsync_counter_1 ;
 249 wire un10_hsync_counter_4 ;
 250 wire un12_hsync_counter ;
 251 wire un11_hsync_counter_2 ;
 252 wire un11_hsync_counter_3 ;
 253 wire un13_hsync_counter ;
 254 wire vsync_state_next_1_sqmuxa_1 ;
 255 wire vsync_state_next_1_sqmuxa_3 ;
 256 wire un1_vsync_state_next_1_sqmuxa_0 ;
 257 wire hsync_state_next_1_sqmuxa_1 ;
 258 wire hsync_state_next_1_sqmuxa_2 ;
 259 wire un1_hsync_state_next_1_sqmuxa_0 ;
 260 wire un12_vsync_counter_6 ;
 261 wire un15_vsync_counter_4 ;
 262 wire vsync_state_next_1_sqmuxa_2 ;
 263 wire un10_line_counter_siglto5 ;
 264 wire un10_column_counter_siglt6 ;
 265 wire un13_hsync_counter_2 ;
 266 wire un13_hsync_counter_7 ;
 267 wire un9_hsync_counterlt9_3 ;
 268 wire un9_vsync_counterlt9_5 ;
 269 wire un9_vsync_counterlt9_6 ;
 270 wire un12_hsync_counter_3 ;
 271 wire un12_hsync_counter_4 ;
 272 wire un10_line_counter_siglt4_2 ;
 273 wire un15_vsync_counter_3 ;
 274 wire un13_vsync_counter_3 ;
 275 wire un10_column_counter_siglt6_4 ;
 276 wire un1_vsync_state_2_0 ;
 277 wire un1_hsync_state_3_0 ;
 278 wire VCC ;
 279 wire GND ;
 280 wire line_counter_next_0_sqmuxa_1_1_i ;
 281 wire column_counter_next_0_sqmuxa_1_1_i ;
 282 wire un9_vsync_counterlt9_i ;
 283 wire G_16_i_i ;
 284 wire un9_hsync_counterlt9_i ;
 285 wire G_2_i_i ;
 286 //@1:1
 287   assign VCC = 1'b1;
 288   assign GND = 1'b0;
 289 // @13:158
 290   stratix_lcell hsync_counter_0_ (
 291         .regout(hsync_counter_0),
 292         .cout(hsync_counter_cout[0]),
 293         .clk(clk_pin_c),
 294         .dataa(hsync_counter_0),
 295         .datab(VCC),
 296         .datac(hsync_counter_next_1_sqmuxa),
 297         .datad(VCC),
 298         .aclr(GND),
 299         .sclr(G_2_i_i),
 300         .sload(un9_hsync_counterlt9_i),
 301         .ena(VCC),
 302         .inverta(GND),
 303         .aload(GND),
 304         .regcascin(GND)
 305 );
 306 defparam hsync_counter_0_.operation_mode="arithmetic";
 307 defparam hsync_counter_0_.output_mode="reg_only";
 308 defparam hsync_counter_0_.lut_mask="55aa";
 309 defparam hsync_counter_0_.synch_mode="on";
 310 defparam hsync_counter_0_.sum_lutc_input="datac";
 311 // @13:158
 312   stratix_lcell hsync_counter_1_ (
 313         .regout(hsync_counter_1),
 314         .cout(hsync_counter_cout[1]),
 315         .clk(clk_pin_c),
 316         .dataa(hsync_counter_1),
 317         .datab(VCC),
 318         .datac(hsync_counter_next_1_sqmuxa),
 319         .datad(VCC),
 320         .aclr(GND),
 321         .sclr(G_2_i_i),
 322         .sload(un9_hsync_counterlt9_i),
 323         .ena(VCC),
 324         .cin(hsync_counter_cout[0]),
 325         .inverta(GND),
 326         .aload(GND),
 327         .regcascin(GND)
 328 );
 329 defparam hsync_counter_1_.cin_used="true";
 330 defparam hsync_counter_1_.operation_mode="arithmetic";
 331 defparam hsync_counter_1_.output_mode="reg_only";
 332 defparam hsync_counter_1_.lut_mask="5aa0";
 333 defparam hsync_counter_1_.synch_mode="on";
 334 defparam hsync_counter_1_.sum_lutc_input="cin";
 335 // @13:158
 336   stratix_lcell hsync_counter_2_ (
 337         .regout(hsync_counter_2),
 338         .cout(hsync_counter_cout[2]),
 339         .clk(clk_pin_c),
 340         .dataa(hsync_counter_2),
 341         .datab(VCC),
 342         .datac(hsync_counter_next_1_sqmuxa),
 343         .datad(VCC),
 344         .aclr(GND),
 345         .sclr(G_2_i_i),
 346         .sload(un9_hsync_counterlt9_i),
 347         .ena(VCC),
 348         .cin(hsync_counter_cout[1]),
 349         .inverta(GND),
 350         .aload(GND),
 351         .regcascin(GND)
 352 );
 353 defparam hsync_counter_2_.cin_used="true";
 354 defparam hsync_counter_2_.operation_mode="arithmetic";
 355 defparam hsync_counter_2_.output_mode="reg_only";
 356 defparam hsync_counter_2_.lut_mask="5aa0";
 357 defparam hsync_counter_2_.synch_mode="on";
 358 defparam hsync_counter_2_.sum_lutc_input="cin";
 359 // @13:158
 360   stratix_lcell hsync_counter_3_ (
 361         .regout(hsync_counter_3),
 362         .cout(hsync_counter_cout[3]),
 363         .clk(clk_pin_c),
 364         .dataa(hsync_counter_3),
 365         .datab(VCC),
 366         .datac(hsync_counter_next_1_sqmuxa),
 367         .datad(VCC),
 368         .aclr(GND),
 369         .sclr(G_2_i_i),
 370         .sload(un9_hsync_counterlt9_i),
 371         .ena(VCC),
 372         .cin(hsync_counter_cout[2]),
 373         .inverta(GND),
 374         .aload(GND),
 375         .regcascin(GND)
 376 );
 377 defparam hsync_counter_3_.cin_used="true";
 378 defparam hsync_counter_3_.operation_mode="arithmetic";
 379 defparam hsync_counter_3_.output_mode="reg_only";
 380 defparam hsync_counter_3_.lut_mask="5aa0";
 381 defparam hsync_counter_3_.synch_mode="on";
 382 defparam hsync_counter_3_.sum_lutc_input="cin";
 383 // @13:158
 384   stratix_lcell hsync_counter_4_ (
 385         .regout(hsync_counter_4),
 386         .cout(hsync_counter_cout[4]),
 387         .clk(clk_pin_c),
 388         .dataa(hsync_counter_4),
 389         .datab(VCC),
 390         .datac(hsync_counter_next_1_sqmuxa),
 391         .datad(VCC),
 392         .aclr(GND),
 393         .sclr(G_2_i_i),
 394         .sload(un9_hsync_counterlt9_i),
 395         .ena(VCC),
 396         .cin(hsync_counter_cout[3]),
 397         .inverta(GND),
 398         .aload(GND),
 399         .regcascin(GND)
 400 );
 401 defparam hsync_counter_4_.cin_used="true";
 402 defparam hsync_counter_4_.operation_mode="arithmetic";
 403 defparam hsync_counter_4_.output_mode="reg_only";
 404 defparam hsync_counter_4_.lut_mask="5aa0";
 405 defparam hsync_counter_4_.synch_mode="on";
 406 defparam hsync_counter_4_.sum_lutc_input="cin";
 407 // @13:158
 408   stratix_lcell hsync_counter_5_ (
 409         .regout(hsync_counter_5),
 410         .cout(hsync_counter_cout[5]),
 411         .clk(clk_pin_c),
 412         .dataa(hsync_counter_5),
 413         .datab(VCC),
 414         .datac(hsync_counter_next_1_sqmuxa),
 415         .datad(VCC),
 416         .aclr(GND),
 417         .sclr(G_2_i_i),
 418         .sload(un9_hsync_counterlt9_i),
 419         .ena(VCC),
 420         .cin(hsync_counter_cout[4]),
 421         .inverta(GND),
 422         .aload(GND),
 423         .regcascin(GND)
 424 );
 425 defparam hsync_counter_5_.cin_used="true";
 426 defparam hsync_counter_5_.operation_mode="arithmetic";
 427 defparam hsync_counter_5_.output_mode="reg_only";
 428 defparam hsync_counter_5_.lut_mask="5aa0";
 429 defparam hsync_counter_5_.synch_mode="on";
 430 defparam hsync_counter_5_.sum_lutc_input="cin";
 431 // @13:158
 432   stratix_lcell hsync_counter_6_ (
 433         .regout(hsync_counter_6),
 434         .cout(hsync_counter_cout[6]),
 435         .clk(clk_pin_c),
 436         .dataa(hsync_counter_6),
 437         .datab(VCC),
 438         .datac(hsync_counter_next_1_sqmuxa),
 439         .datad(VCC),
 440         .aclr(GND),
 441         .sclr(G_2_i_i),
 442         .sload(un9_hsync_counterlt9_i),
 443         .ena(VCC),
 444         .cin(hsync_counter_cout[5]),
 445         .inverta(GND),
 446         .aload(GND),
 447         .regcascin(GND)
 448 );
 449 defparam hsync_counter_6_.cin_used="true";
 450 defparam hsync_counter_6_.operation_mode="arithmetic";
 451 defparam hsync_counter_6_.output_mode="reg_only";
 452 defparam hsync_counter_6_.lut_mask="5aa0";
 453 defparam hsync_counter_6_.synch_mode="on";
 454 defparam hsync_counter_6_.sum_lutc_input="cin";
 455 // @13:158
 456   stratix_lcell hsync_counter_7_ (
 457         .regout(hsync_counter_7),
 458         .cout(hsync_counter_cout[7]),
 459         .clk(clk_pin_c),
 460         .dataa(hsync_counter_7),
 461         .datab(VCC),
 462         .datac(hsync_counter_next_1_sqmuxa),
 463         .datad(VCC),
 464         .aclr(GND),
 465         .sclr(G_2_i_i),
 466         .sload(un9_hsync_counterlt9_i),
 467         .ena(VCC),
 468         .cin(hsync_counter_cout[6]),
 469         .inverta(GND),
 470         .aload(GND),
 471         .regcascin(GND)
 472 );
 473 defparam hsync_counter_7_.cin_used="true";
 474 defparam hsync_counter_7_.operation_mode="arithmetic";
 475 defparam hsync_counter_7_.output_mode="reg_only";
 476 defparam hsync_counter_7_.lut_mask="5aa0";
 477 defparam hsync_counter_7_.synch_mode="on";
 478 defparam hsync_counter_7_.sum_lutc_input="cin";
 479 // @13:158
 480   stratix_lcell hsync_counter_8_ (
 481         .regout(hsync_counter_8),
 482         .cout(hsync_counter_cout[8]),
 483         .clk(clk_pin_c),
 484         .dataa(hsync_counter_8),
 485         .datab(VCC),
 486         .datac(hsync_counter_next_1_sqmuxa),
 487         .datad(VCC),
 488         .aclr(GND),
 489         .sclr(G_2_i_i),
 490         .sload(un9_hsync_counterlt9_i),
 491         .ena(VCC),
 492         .cin(hsync_counter_cout[7]),
 493         .inverta(GND),
 494         .aload(GND),
 495         .regcascin(GND)
 496 );
 497 defparam hsync_counter_8_.cin_used="true";
 498 defparam hsync_counter_8_.operation_mode="arithmetic";
 499 defparam hsync_counter_8_.output_mode="reg_only";
 500 defparam hsync_counter_8_.lut_mask="5aa0";
 501 defparam hsync_counter_8_.synch_mode="on";
 502 defparam hsync_counter_8_.sum_lutc_input="cin";
 503 // @13:158
 504   stratix_lcell hsync_counter_9_ (
 505         .regout(hsync_counter_9),
 506         .clk(clk_pin_c),
 507         .dataa(hsync_counter_9),
 508         .datab(VCC),
 509         .datac(hsync_counter_next_1_sqmuxa),
 510         .datad(VCC),
 511         .aclr(GND),
 512         .sclr(G_2_i_i),
 513         .sload(un9_hsync_counterlt9_i),
 514         .ena(VCC),
 515         .cin(hsync_counter_cout[8]),
 516         .inverta(GND),
 517         .aload(GND),
 518         .regcascin(GND)
 519 );
 520 defparam hsync_counter_9_.cin_used="true";
 521 defparam hsync_counter_9_.operation_mode="normal";
 522 defparam hsync_counter_9_.output_mode="reg_only";
 523 defparam hsync_counter_9_.lut_mask="5a5a";
 524 defparam hsync_counter_9_.synch_mode="on";
 525 defparam hsync_counter_9_.sum_lutc_input="cin";
 526 // @13:267
 527   stratix_lcell vsync_counter_0_ (
 528         .regout(vsync_counter_0),
 529         .cout(vsync_counter_cout[0]),
 530         .clk(clk_pin_c),
 531         .dataa(vsync_counter_0),
 532         .datab(d_set_hsync_counter),
 533         .datac(vsync_counter_next_1_sqmuxa),
 534         .datad(VCC),
 535         .aclr(GND),
 536         .sclr(G_16_i_i),
 537         .sload(un9_vsync_counterlt9_i),
 538         .ena(VCC),
 539         .inverta(GND),
 540         .aload(GND),
 541         .regcascin(GND)
 542 );
 543 defparam vsync_counter_0_.operation_mode="arithmetic";
 544 defparam vsync_counter_0_.output_mode="reg_only";
 545 defparam vsync_counter_0_.lut_mask="6688";
 546 defparam vsync_counter_0_.synch_mode="on";
 547 defparam vsync_counter_0_.sum_lutc_input="datac";
 548 // @13:267
 549   stratix_lcell vsync_counter_1_ (
 550         .regout(vsync_counter_1),
 551         .cout(vsync_counter_cout[1]),
 552         .clk(clk_pin_c),
 553         .dataa(vsync_counter_1),
 554         .datab(VCC),
 555         .datac(vsync_counter_next_1_sqmuxa),
 556         .datad(VCC),
 557         .aclr(GND),
 558         .sclr(G_16_i_i),
 559         .sload(un9_vsync_counterlt9_i),
 560         .ena(VCC),
 561         .cin(vsync_counter_cout[0]),
 562         .inverta(GND),
 563         .aload(GND),
 564         .regcascin(GND)
 565 );
 566 defparam vsync_counter_1_.cin_used="true";
 567 defparam vsync_counter_1_.operation_mode="arithmetic";
 568 defparam vsync_counter_1_.output_mode="reg_only";
 569 defparam vsync_counter_1_.lut_mask="5aa0";
 570 defparam vsync_counter_1_.synch_mode="on";
 571 defparam vsync_counter_1_.sum_lutc_input="cin";
 572 // @13:267
 573   stratix_lcell vsync_counter_2_ (
 574         .regout(vsync_counter_2),
 575         .cout(vsync_counter_cout[2]),
 576         .clk(clk_pin_c),
 577         .dataa(vsync_counter_2),
 578         .datab(VCC),
 579         .datac(vsync_counter_next_1_sqmuxa),
 580         .datad(VCC),
 581         .aclr(GND),
 582         .sclr(G_16_i_i),
 583         .sload(un9_vsync_counterlt9_i),
 584         .ena(VCC),
 585         .cin(vsync_counter_cout[1]),
 586         .inverta(GND),
 587         .aload(GND),
 588         .regcascin(GND)
 589 );
 590 defparam vsync_counter_2_.cin_used="true";
 591 defparam vsync_counter_2_.operation_mode="arithmetic";
 592 defparam vsync_counter_2_.output_mode="reg_only";
 593 defparam vsync_counter_2_.lut_mask="5aa0";
 594 defparam vsync_counter_2_.synch_mode="on";
 595 defparam vsync_counter_2_.sum_lutc_input="cin";
 596 // @13:267
 597   stratix_lcell vsync_counter_3_ (
 598         .regout(vsync_counter_3),
 599         .cout(vsync_counter_cout[3]),
 600         .clk(clk_pin_c),
 601         .dataa(vsync_counter_3),
 602         .datab(VCC),
 603         .datac(vsync_counter_next_1_sqmuxa),
 604         .datad(VCC),
 605         .aclr(GND),
 606         .sclr(G_16_i_i),
 607         .sload(un9_vsync_counterlt9_i),
 608         .ena(VCC),
 609         .cin(vsync_counter_cout[2]),
 610         .inverta(GND),
 611         .aload(GND),
 612         .regcascin(GND)
 613 );
 614 defparam vsync_counter_3_.cin_used="true";
 615 defparam vsync_counter_3_.operation_mode="arithmetic";
 616 defparam vsync_counter_3_.output_mode="reg_only";
 617 defparam vsync_counter_3_.lut_mask="5aa0";
 618 defparam vsync_counter_3_.synch_mode="on";
 619 defparam vsync_counter_3_.sum_lutc_input="cin";
 620 // @13:267
 621   stratix_lcell vsync_counter_4_ (
 622         .regout(vsync_counter_4),
 623         .cout(vsync_counter_cout[4]),
 624         .clk(clk_pin_c),
 625         .dataa(vsync_counter_4),
 626         .datab(VCC),
 627         .datac(vsync_counter_next_1_sqmuxa),
 628         .datad(VCC),
 629         .aclr(GND),
 630         .sclr(G_16_i_i),
 631         .sload(un9_vsync_counterlt9_i),
 632         .ena(VCC),
 633         .cin(vsync_counter_cout[3]),
 634         .inverta(GND),
 635         .aload(GND),
 636         .regcascin(GND)
 637 );
 638 defparam vsync_counter_4_.cin_used="true";
 639 defparam vsync_counter_4_.operation_mode="arithmetic";
 640 defparam vsync_counter_4_.output_mode="reg_only";
 641 defparam vsync_counter_4_.lut_mask="5aa0";
 642 defparam vsync_counter_4_.synch_mode="on";
 643 defparam vsync_counter_4_.sum_lutc_input="cin";
 644 // @13:267
 645   stratix_lcell vsync_counter_5_ (
 646         .regout(vsync_counter_5),
 647         .cout(vsync_counter_cout[5]),
 648         .clk(clk_pin_c),
 649         .dataa(vsync_counter_5),
 650         .datab(VCC),
 651         .datac(vsync_counter_next_1_sqmuxa),
 652         .datad(VCC),
 653         .aclr(GND),
 654         .sclr(G_16_i_i),
 655         .sload(un9_vsync_counterlt9_i),
 656         .ena(VCC),
 657         .cin(vsync_counter_cout[4]),
 658         .inverta(GND),
 659         .aload(GND),
 660         .regcascin(GND)
 661 );
 662 defparam vsync_counter_5_.cin_used="true";
 663 defparam vsync_counter_5_.operation_mode="arithmetic";
 664 defparam vsync_counter_5_.output_mode="reg_only";
 665 defparam vsync_counter_5_.lut_mask="5aa0";
 666 defparam vsync_counter_5_.synch_mode="on";
 667 defparam vsync_counter_5_.sum_lutc_input="cin";
 668 // @13:267
 669   stratix_lcell vsync_counter_6_ (
 670         .regout(vsync_counter_6),
 671         .cout(vsync_counter_cout[6]),
 672         .clk(clk_pin_c),
 673         .dataa(vsync_counter_6),
 674         .datab(VCC),
 675         .datac(vsync_counter_next_1_sqmuxa),
 676         .datad(VCC),
 677         .aclr(GND),
 678         .sclr(G_16_i_i),
 679         .sload(un9_vsync_counterlt9_i),
 680         .ena(VCC),
 681         .cin(vsync_counter_cout[5]),
 682         .inverta(GND),
 683         .aload(GND),
 684         .regcascin(GND)
 685 );
 686 defparam vsync_counter_6_.cin_used="true";
 687 defparam vsync_counter_6_.operation_mode="arithmetic";
 688 defparam vsync_counter_6_.output_mode="reg_only";
 689 defparam vsync_counter_6_.lut_mask="5aa0";
 690 defparam vsync_counter_6_.synch_mode="on";
 691 defparam vsync_counter_6_.sum_lutc_input="cin";
 692 // @13:267
 693   stratix_lcell vsync_counter_7_ (
 694         .regout(vsync_counter_7),
 695         .cout(vsync_counter_cout[7]),
 696         .clk(clk_pin_c),
 697         .dataa(vsync_counter_7),
 698         .datab(VCC),
 699         .datac(vsync_counter_next_1_sqmuxa),
 700         .datad(VCC),
 701         .aclr(GND),
 702         .sclr(G_16_i_i),
 703         .sload(un9_vsync_counterlt9_i),
 704         .ena(VCC),
 705         .cin(vsync_counter_cout[6]),
 706         .inverta(GND),
 707         .aload(GND),
 708         .regcascin(GND)
 709 );
 710 defparam vsync_counter_7_.cin_used="true";
 711 defparam vsync_counter_7_.operation_mode="arithmetic";
 712 defparam vsync_counter_7_.output_mode="reg_only";
 713 defparam vsync_counter_7_.lut_mask="5aa0";
 714 defparam vsync_counter_7_.synch_mode="on";
 715 defparam vsync_counter_7_.sum_lutc_input="cin";
 716 // @13:267
 717   stratix_lcell vsync_counter_8_ (
 718         .regout(vsync_counter_8),
 719         .cout(vsync_counter_cout[8]),
 720         .clk(clk_pin_c),
 721         .dataa(vsync_counter_8),
 722         .datab(VCC),
 723         .datac(vsync_counter_next_1_sqmuxa),
 724         .datad(VCC),
 725         .aclr(GND),
 726         .sclr(G_16_i_i),
 727         .sload(un9_vsync_counterlt9_i),
 728         .ena(VCC),
 729         .cin(vsync_counter_cout[7]),
 730         .inverta(GND),
 731         .aload(GND),
 732         .regcascin(GND)
 733 );
 734 defparam vsync_counter_8_.cin_used="true";
 735 defparam vsync_counter_8_.operation_mode="arithmetic";
 736 defparam vsync_counter_8_.output_mode="reg_only";
 737 defparam vsync_counter_8_.lut_mask="5aa0";
 738 defparam vsync_counter_8_.synch_mode="on";
 739 defparam vsync_counter_8_.sum_lutc_input="cin";
 740 // @13:267
 741   stratix_lcell vsync_counter_9_ (
 742         .regout(vsync_counter_9),
 743         .clk(clk_pin_c),
 744         .dataa(vsync_counter_9),
 745         .datab(VCC),
 746         .datac(vsync_counter_next_1_sqmuxa),
 747         .datad(VCC),
 748         .aclr(GND),
 749         .sclr(G_16_i_i),
 750         .sload(un9_vsync_counterlt9_i),
 751         .ena(VCC),
 752         .cin(vsync_counter_cout[8]),
 753         .inverta(GND),
 754         .aload(GND),
 755         .regcascin(GND)
 756 );
 757 defparam vsync_counter_9_.cin_used="true";
 758 defparam vsync_counter_9_.operation_mode="normal";
 759 defparam vsync_counter_9_.output_mode="reg_only";
 760 defparam vsync_counter_9_.lut_mask="5a5a";
 761 defparam vsync_counter_9_.synch_mode="on";
 762 defparam vsync_counter_9_.sum_lutc_input="cin";
 763 // @13:97
 764   stratix_lcell column_counter_sig_9_ (
 765         .regout(column_counter_sig_9),
 766         .clk(clk_pin_c),
 767         .dataa(un2_column_counter_next_combout[9]),
 768         .datab(un10_column_counter_siglto9),
 769         .datac(VCC),
 770         .datad(VCC),
 771         .aclr(GND),
 772         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 773         .sload(GND),
 774         .ena(VCC),
 775         .inverta(GND),
 776         .aload(GND),
 777         .regcascin(GND)
 778 );
 779 defparam column_counter_sig_9_.operation_mode="normal";
 780 defparam column_counter_sig_9_.output_mode="reg_only";
 781 defparam column_counter_sig_9_.lut_mask="bbbb";
 782 defparam column_counter_sig_9_.synch_mode="on";
 783 defparam column_counter_sig_9_.sum_lutc_input="datac";
 784 // @13:97
 785   stratix_lcell column_counter_sig_8_ (
 786         .regout(column_counter_sig_8),
 787         .clk(clk_pin_c),
 788         .dataa(un2_column_counter_next_combout[8]),
 789         .datab(un10_column_counter_siglto9),
 790         .datac(column_counter_next_0_sqmuxa_1_1),
 791         .datad(VCC),
 792         .aclr(GND),
 793         .sclr(GND),
 794         .sload(GND),
 795         .ena(VCC),
 796         .inverta(GND),
 797         .aload(GND),
 798         .regcascin(GND)
 799 );
 800 defparam column_counter_sig_8_.operation_mode="normal";
 801 defparam column_counter_sig_8_.output_mode="reg_only";
 802 defparam column_counter_sig_8_.lut_mask="8080";
 803 defparam column_counter_sig_8_.synch_mode="off";
 804 defparam column_counter_sig_8_.sum_lutc_input="datac";
 805 // @13:97
 806   stratix_lcell column_counter_sig_7_ (
 807         .regout(column_counter_sig_7),
 808         .clk(clk_pin_c),
 809         .dataa(un2_column_counter_next_combout[7]),
 810         .datab(un10_column_counter_siglto9),
 811         .datac(column_counter_next_0_sqmuxa_1_1),
 812         .datad(VCC),
 813         .aclr(GND),
 814         .sclr(GND),
 815         .sload(GND),
 816         .ena(VCC),
 817         .inverta(GND),
 818         .aload(GND),
 819         .regcascin(GND)
 820 );
 821 defparam column_counter_sig_7_.operation_mode="normal";
 822 defparam column_counter_sig_7_.output_mode="reg_only";
 823 defparam column_counter_sig_7_.lut_mask="8080";
 824 defparam column_counter_sig_7_.synch_mode="off";
 825 defparam column_counter_sig_7_.sum_lutc_input="datac";
 826 // @13:97
 827   stratix_lcell column_counter_sig_6_ (
 828         .regout(column_counter_sig_6),
 829         .clk(clk_pin_c),
 830         .dataa(un2_column_counter_next_combout[6]),
 831         .datab(un10_column_counter_siglto9),
 832         .datac(VCC),
 833         .datad(VCC),
 834         .aclr(GND),
 835         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 836         .sload(GND),
 837         .ena(VCC),
 838         .inverta(GND),
 839         .aload(GND),
 840         .regcascin(GND)
 841 );
 842 defparam column_counter_sig_6_.operation_mode="normal";
 843 defparam column_counter_sig_6_.output_mode="reg_only";
 844 defparam column_counter_sig_6_.lut_mask="bbbb";
 845 defparam column_counter_sig_6_.synch_mode="on";
 846 defparam column_counter_sig_6_.sum_lutc_input="datac";
 847 // @13:97
 848   stratix_lcell column_counter_sig_5_ (
 849         .regout(column_counter_sig_5),
 850         .clk(clk_pin_c),
 851         .dataa(un2_column_counter_next_combout[5]),
 852         .datab(un10_column_counter_siglto9),
 853         .datac(VCC),
 854         .datad(VCC),
 855         .aclr(GND),
 856         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 857         .sload(GND),
 858         .ena(VCC),
 859         .inverta(GND),
 860         .aload(GND),
 861         .regcascin(GND)
 862 );
 863 defparam column_counter_sig_5_.operation_mode="normal";
 864 defparam column_counter_sig_5_.output_mode="reg_only";
 865 defparam column_counter_sig_5_.lut_mask="bbbb";
 866 defparam column_counter_sig_5_.synch_mode="on";
 867 defparam column_counter_sig_5_.sum_lutc_input="datac";
 868 // @13:97
 869   stratix_lcell column_counter_sig_4_ (
 870         .regout(column_counter_sig_4),
 871         .clk(clk_pin_c),
 872         .dataa(un2_column_counter_next_combout[4]),
 873         .datab(un10_column_counter_siglto9),
 874         .datac(VCC),
 875         .datad(VCC),
 876         .aclr(GND),
 877         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 878         .sload(GND),
 879         .ena(VCC),
 880         .inverta(GND),
 881         .aload(GND),
 882         .regcascin(GND)
 883 );
 884 defparam column_counter_sig_4_.operation_mode="normal";
 885 defparam column_counter_sig_4_.output_mode="reg_only";
 886 defparam column_counter_sig_4_.lut_mask="bbbb";
 887 defparam column_counter_sig_4_.synch_mode="on";
 888 defparam column_counter_sig_4_.sum_lutc_input="datac";
 889 // @13:97
 890   stratix_lcell column_counter_sig_3_ (
 891         .regout(column_counter_sig_3),
 892         .clk(clk_pin_c),
 893         .dataa(un2_column_counter_next_combout[3]),
 894         .datab(un10_column_counter_siglto9),
 895         .datac(VCC),
 896         .datad(VCC),
 897         .aclr(GND),
 898         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 899         .sload(GND),
 900         .ena(VCC),
 901         .inverta(GND),
 902         .aload(GND),
 903         .regcascin(GND)
 904 );
 905 defparam column_counter_sig_3_.operation_mode="normal";
 906 defparam column_counter_sig_3_.output_mode="reg_only";
 907 defparam column_counter_sig_3_.lut_mask="bbbb";
 908 defparam column_counter_sig_3_.synch_mode="on";
 909 defparam column_counter_sig_3_.sum_lutc_input="datac";
 910 // @13:97
 911   stratix_lcell column_counter_sig_2_ (
 912         .regout(column_counter_sig_2),
 913         .clk(clk_pin_c),
 914         .dataa(un2_column_counter_next_combout[2]),
 915         .datab(un10_column_counter_siglto9),
 916         .datac(VCC),
 917         .datad(VCC),
 918         .aclr(GND),
 919         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 920         .sload(GND),
 921         .ena(VCC),
 922         .inverta(GND),
 923         .aload(GND),
 924         .regcascin(GND)
 925 );
 926 defparam column_counter_sig_2_.operation_mode="normal";
 927 defparam column_counter_sig_2_.output_mode="reg_only";
 928 defparam column_counter_sig_2_.lut_mask="bbbb";
 929 defparam column_counter_sig_2_.synch_mode="on";
 930 defparam column_counter_sig_2_.sum_lutc_input="datac";
 931 // @13:97
 932   stratix_lcell column_counter_sig_1_ (
 933         .regout(column_counter_sig_1),
 934         .clk(clk_pin_c),
 935         .dataa(un2_column_counter_next_combout[1]),
 936         .datab(un10_column_counter_siglto9),
 937         .datac(VCC),
 938         .datad(VCC),
 939         .aclr(GND),
 940         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 941         .sload(GND),
 942         .ena(VCC),
 943         .inverta(GND),
 944         .aload(GND),
 945         .regcascin(GND)
 946 );
 947 defparam column_counter_sig_1_.operation_mode="normal";
 948 defparam column_counter_sig_1_.output_mode="reg_only";
 949 defparam column_counter_sig_1_.lut_mask="bbbb";
 950 defparam column_counter_sig_1_.synch_mode="on";
 951 defparam column_counter_sig_1_.sum_lutc_input="datac";
 952 // @13:97
 953   stratix_lcell column_counter_sig_0_ (
 954         .regout(column_counter_sig_0),
 955         .clk(clk_pin_c),
 956         .dataa(column_counter_sig_0),
 957         .datab(un10_column_counter_siglto9),
 958         .datac(VCC),
 959         .datad(VCC),
 960         .aclr(GND),
 961         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 962         .sload(GND),
 963         .ena(VCC),
 964         .inverta(GND),
 965         .aload(GND),
 966         .regcascin(GND)
 967 );
 968 defparam column_counter_sig_0_.operation_mode="normal";
 969 defparam column_counter_sig_0_.output_mode="reg_only";
 970 defparam column_counter_sig_0_.lut_mask="7777";
 971 defparam column_counter_sig_0_.synch_mode="on";
 972 defparam column_counter_sig_0_.sum_lutc_input="datac";
 973 // @13:187
 974   stratix_lcell hsync_state_6_ (
 975         .regout(hsync_state_6),
 976         .clk(clk_pin_c),
 977         .dataa(VCC),
 978         .datab(VCC),
 979         .datac(VCC),
 980         .datad(un6_dly_counter_0_x),
 981         .aclr(GND),
 982         .sclr(GND),
 983         .sload(GND),
 984         .ena(VCC),
 985         .inverta(GND),
 986         .aload(GND),
 987         .regcascin(GND)
 988 );
 989 defparam hsync_state_6_.operation_mode="normal";
 990 defparam hsync_state_6_.output_mode="reg_only";
 991 defparam hsync_state_6_.lut_mask="ff00";
 992 defparam hsync_state_6_.synch_mode="off";
 993 defparam hsync_state_6_.sum_lutc_input="datac";
 994 // @13:300
 995   stratix_lcell vsync_state_0_ (
 996         .regout(vsync_state_0),
 997         .clk(clk_pin_c),
 998         .dataa(vsync_state_0),
 999         .datab(vsync_state_3_iv_0_0__g0_0_a3_0),
1000         .datac(un6_dly_counter_0_x),
1001         .datad(vsync_state_next_2_sqmuxa),
1002         .aclr(GND),
1003         .sclr(GND),
1004         .sload(GND),
1005         .ena(VCC),
1006         .inverta(GND),
1007         .aload(GND),
1008         .regcascin(GND)
1009 );
1010 defparam vsync_state_0_.operation_mode="normal";
1011 defparam vsync_state_0_.output_mode="reg_only";
1012 defparam vsync_state_0_.lut_mask="0cae";
1013 defparam vsync_state_0_.synch_mode="off";
1014 defparam vsync_state_0_.sum_lutc_input="datac";
1015 // @13:300
1016   stratix_lcell vsync_state_1_ (
1017         .regout(vsync_state_1),
1018         .clk(clk_pin_c),
1019         .dataa(vsync_state_4),
1020         .datab(un12_vsync_counter_7),
1021         .datac(un13_vsync_counter_4),
1022         .datad(un6_dly_counter_0_x),
1023         .aclr(GND),
1024         .sclr(GND),
1025         .sload(GND),
1026         .ena(VCC),
1027         .inverta(GND),
1028         .aload(GND),
1029         .regcascin(GND)
1030 );
1031 defparam vsync_state_1_.operation_mode="normal";
1032 defparam vsync_state_1_.output_mode="reg_only";
1033 defparam vsync_state_1_.lut_mask="0080";
1034 defparam vsync_state_1_.synch_mode="off";
1035 defparam vsync_state_1_.sum_lutc_input="datac";
1036 // @13:300
1037   stratix_lcell vsync_state_6_ (
1038         .combout(un6_dly_counter_0_x),
1039         .regout(vsync_state_6),
1040         .clk(clk_pin_c),
1041         .dataa(reset_pin_c),
1042         .datab(dly_counter_0),
1043         .datac(dly_counter_1),
1044         .datad(VCC),
1045         .aclr(GND),
1046         .sclr(GND),
1047         .sload(GND),
1048         .ena(VCC),
1049         .inverta(GND),
1050         .aload(GND),
1051         .regcascin(GND)
1052 );
1053 defparam vsync_state_6_.operation_mode="normal";
1054 defparam vsync_state_6_.output_mode="reg_and_comb";
1055 defparam vsync_state_6_.lut_mask="7f7f";
1056 defparam vsync_state_6_.synch_mode="off";
1057 defparam vsync_state_6_.sum_lutc_input="datac";
1058 // @13:125
1059   stratix_lcell line_counter_sig_8_ (
1060         .regout(line_counter_sig_8),
1061         .clk(clk_pin_c),
1062         .dataa(un10_line_counter_siglto8),
1063         .datab(un1_line_counter_sig_combout[9]),
1064         .datac(VCC),
1065         .datad(VCC),
1066         .aclr(GND),
1067         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1068         .sload(GND),
1069         .ena(VCC),
1070         .inverta(GND),
1071         .aload(GND),
1072         .regcascin(GND)
1073 );
1074 defparam line_counter_sig_8_.operation_mode="normal";
1075 defparam line_counter_sig_8_.output_mode="reg_only";
1076 defparam line_counter_sig_8_.lut_mask="dddd";
1077 defparam line_counter_sig_8_.synch_mode="on";
1078 defparam line_counter_sig_8_.sum_lutc_input="datac";
1079 // @13:125
1080   stratix_lcell line_counter_sig_7_ (
1081         .regout(line_counter_sig_7),
1082         .clk(clk_pin_c),
1083         .dataa(un10_line_counter_siglto8),
1084         .datab(un1_line_counter_sig_combout[8]),
1085         .datac(VCC),
1086         .datad(VCC),
1087         .aclr(GND),
1088         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1089         .sload(GND),
1090         .ena(VCC),
1091         .inverta(GND),
1092         .aload(GND),
1093         .regcascin(GND)
1094 );
1095 defparam line_counter_sig_7_.operation_mode="normal";
1096 defparam line_counter_sig_7_.output_mode="reg_only";
1097 defparam line_counter_sig_7_.lut_mask="dddd";
1098 defparam line_counter_sig_7_.synch_mode="on";
1099 defparam line_counter_sig_7_.sum_lutc_input="datac";
1100 // @13:125
1101   stratix_lcell line_counter_sig_6_ (
1102         .regout(line_counter_sig_6),
1103         .clk(clk_pin_c),
1104         .dataa(un10_line_counter_siglto8),
1105         .datab(un1_line_counter_sig_combout[7]),
1106         .datac(VCC),
1107         .datad(VCC),
1108         .aclr(GND),
1109         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1110         .sload(GND),
1111         .ena(VCC),
1112         .inverta(GND),
1113         .aload(GND),
1114         .regcascin(GND)
1115 );
1116 defparam line_counter_sig_6_.operation_mode="normal";
1117 defparam line_counter_sig_6_.output_mode="reg_only";
1118 defparam line_counter_sig_6_.lut_mask="dddd";
1119 defparam line_counter_sig_6_.synch_mode="on";
1120 defparam line_counter_sig_6_.sum_lutc_input="datac";
1121 // @13:125
1122   stratix_lcell line_counter_sig_5_ (
1123         .regout(line_counter_sig_5),
1124         .clk(clk_pin_c),
1125         .dataa(un10_line_counter_siglto8),
1126         .datab(un1_line_counter_sig_combout[6]),
1127         .datac(line_counter_next_0_sqmuxa_1_1),
1128         .datad(VCC),
1129         .aclr(GND),
1130         .sclr(GND),
1131         .sload(GND),
1132         .ena(VCC),
1133         .inverta(GND),
1134         .aload(GND),
1135         .regcascin(GND)
1136 );
1137 defparam line_counter_sig_5_.operation_mode="normal";
1138 defparam line_counter_sig_5_.output_mode="reg_only";
1139 defparam line_counter_sig_5_.lut_mask="8080";
1140 defparam line_counter_sig_5_.synch_mode="off";
1141 defparam line_counter_sig_5_.sum_lutc_input="datac";
1142 // @13:125
1143   stratix_lcell line_counter_sig_4_ (
1144         .regout(line_counter_sig_4),
1145         .clk(clk_pin_c),
1146         .dataa(un10_line_counter_siglto8),
1147         .datab(un1_line_counter_sig_combout[5]),
1148         .datac(VCC),
1149         .datad(VCC),
1150         .aclr(GND),
1151         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1152         .sload(GND),
1153         .ena(VCC),
1154         .inverta(GND),
1155         .aload(GND),
1156         .regcascin(GND)
1157 );
1158 defparam line_counter_sig_4_.operation_mode="normal";
1159 defparam line_counter_sig_4_.output_mode="reg_only";
1160 defparam line_counter_sig_4_.lut_mask="dddd";
1161 defparam line_counter_sig_4_.synch_mode="on";
1162 defparam line_counter_sig_4_.sum_lutc_input="datac";
1163 // @13:125
1164   stratix_lcell line_counter_sig_3_ (
1165         .regout(line_counter_sig_3),
1166         .clk(clk_pin_c),
1167         .dataa(un10_line_counter_siglto8),
1168         .datab(un1_line_counter_sig_combout[4]),
1169         .datac(VCC),
1170         .datad(VCC),
1171         .aclr(GND),
1172         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1173         .sload(GND),
1174         .ena(VCC),
1175         .inverta(GND),
1176         .aload(GND),
1177         .regcascin(GND)
1178 );
1179 defparam line_counter_sig_3_.operation_mode="normal";
1180 defparam line_counter_sig_3_.output_mode="reg_only";
1181 defparam line_counter_sig_3_.lut_mask="dddd";
1182 defparam line_counter_sig_3_.synch_mode="on";
1183 defparam line_counter_sig_3_.sum_lutc_input="datac";
1184 // @13:125
1185   stratix_lcell line_counter_sig_2_ (
1186         .regout(line_counter_sig_2),
1187         .clk(clk_pin_c),
1188         .dataa(un10_line_counter_siglto8),
1189         .datab(un1_line_counter_sig_combout[3]),
1190         .datac(VCC),
1191         .datad(VCC),
1192         .aclr(GND),
1193         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1194         .sload(GND),
1195         .ena(VCC),
1196         .inverta(GND),
1197         .aload(GND),
1198         .regcascin(GND)
1199 );
1200 defparam line_counter_sig_2_.operation_mode="normal";
1201 defparam line_counter_sig_2_.output_mode="reg_only";
1202 defparam line_counter_sig_2_.lut_mask="dddd";
1203 defparam line_counter_sig_2_.synch_mode="on";
1204 defparam line_counter_sig_2_.sum_lutc_input="datac";
1205 // @13:125
1206   stratix_lcell line_counter_sig_1_ (
1207         .regout(line_counter_sig_1),
1208         .clk(clk_pin_c),
1209         .dataa(un10_line_counter_siglto8),
1210         .datab(un1_line_counter_sig_combout[2]),
1211         .datac(VCC),
1212         .datad(VCC),
1213         .aclr(GND),
1214         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1215         .sload(GND),
1216         .ena(VCC),
1217         .inverta(GND),
1218         .aload(GND),
1219         .regcascin(GND)
1220 );
1221 defparam line_counter_sig_1_.operation_mode="normal";
1222 defparam line_counter_sig_1_.output_mode="reg_only";
1223 defparam line_counter_sig_1_.lut_mask="dddd";
1224 defparam line_counter_sig_1_.synch_mode="on";
1225 defparam line_counter_sig_1_.sum_lutc_input="datac";
1226 // @13:125
1227   stratix_lcell line_counter_sig_0_ (
1228         .regout(line_counter_sig_0),
1229         .clk(clk_pin_c),
1230         .dataa(un1_line_counter_sig_combout[1]),
1231         .datab(un10_line_counter_siglto8),
1232         .datac(VCC),
1233         .datad(VCC),
1234         .aclr(GND),
1235         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1236         .sload(GND),
1237         .ena(VCC),
1238         .inverta(GND),
1239         .aload(GND),
1240         .regcascin(GND)
1241 );
1242 defparam line_counter_sig_0_.operation_mode="normal";
1243 defparam line_counter_sig_0_.output_mode="reg_only";
1244 defparam line_counter_sig_0_.lut_mask="bbbb";
1245 defparam line_counter_sig_0_.synch_mode="on";
1246 defparam line_counter_sig_0_.sum_lutc_input="datac";
1247 // @13:187
1248   stratix_lcell v_enable_sig_Z (
1249         .regout(v_enable_sig),
1250         .clk(clk_pin_c),
1251         .dataa(hsync_state_3),
1252         .datab(hsync_state_1),
1253         .datac(VCC),
1254         .datad(VCC),
1255         .aclr(GND),
1256         .sclr(un6_dly_counter_0_x),
1257         .sload(GND),
1258         .ena(v_enable_sig_1_0_0_0_g0_i_o4),
1259         .inverta(GND),
1260         .aload(GND),
1261         .regcascin(GND)
1262 );
1263 defparam v_enable_sig_Z.operation_mode="normal";
1264 defparam v_enable_sig_Z.output_mode="reg_only";
1265 defparam v_enable_sig_Z.lut_mask="eeee";
1266 defparam v_enable_sig_Z.synch_mode="on";
1267 defparam v_enable_sig_Z.sum_lutc_input="datac";
1268 // @13:300
1269   stratix_lcell h_enable_sig_Z (
1270         .regout(h_enable_sig),
1271         .clk(clk_pin_c),
1272         .dataa(vsync_state_3),
1273         .datab(vsync_state_1),
1274         .datac(VCC),
1275         .datad(VCC),
1276         .aclr(GND),
1277         .sclr(un6_dly_counter_0_x),
1278         .sload(GND),
1279         .ena(h_enable_sig_1_0_0_0_g0_i_o4),
1280         .inverta(GND),
1281         .aload(GND),
1282         .regcascin(GND)
1283 );
1284 defparam h_enable_sig_Z.operation_mode="normal";
1285 defparam h_enable_sig_Z.output_mode="reg_only";
1286 defparam h_enable_sig_Z.lut_mask="eeee";
1287 defparam h_enable_sig_Z.synch_mode="on";
1288 defparam h_enable_sig_Z.sum_lutc_input="datac";
1289 // @13:187
1290   stratix_lcell h_sync_Z (
1291         .regout(h_sync),
1292         .clk(clk_pin_c),
1293         .dataa(reset_pin_c),
1294         .datab(dly_counter_0),
1295         .datac(dly_counter_1),
1296         .datad(h_sync_1_0_0_0_g1),
1297         .aclr(GND),
1298         .sclr(GND),
1299         .sload(GND),
1300         .ena(VCC),
1301         .inverta(GND),
1302         .aload(GND),
1303         .regcascin(GND)
1304 );
1305 defparam h_sync_Z.operation_mode="normal";
1306 defparam h_sync_Z.output_mode="reg_only";
1307 defparam h_sync_Z.lut_mask="ff7f";
1308 defparam h_sync_Z.synch_mode="off";
1309 defparam h_sync_Z.sum_lutc_input="datac";
1310 // @13:300
1311   stratix_lcell v_sync_Z (
1312         .regout(v_sync),
1313         .clk(clk_pin_c),
1314         .dataa(reset_pin_c),
1315         .datab(dly_counter_0),
1316         .datac(dly_counter_1),
1317         .datad(v_sync_1_0_0_0_g1),
1318         .aclr(GND),
1319         .sclr(GND),
1320         .sload(GND),
1321         .ena(VCC),
1322         .inverta(GND),
1323         .aload(GND),
1324         .regcascin(GND)
1325 );
1326 defparam v_sync_Z.operation_mode="normal";
1327 defparam v_sync_Z.output_mode="reg_only";
1328 defparam v_sync_Z.lut_mask="ff7f";
1329 defparam v_sync_Z.synch_mode="off";
1330 defparam v_sync_Z.sum_lutc_input="datac";
1331 // @13:300
1332   stratix_lcell vsync_state_5_ (
1333         .regout(vsync_state_5),
1334         .clk(clk_pin_c),
1335         .dataa(vsync_state_6),
1336         .datab(vsync_state_0),
1337         .datac(VCC),
1338         .datad(VCC),
1339         .aclr(GND),
1340         .sclr(un6_dly_counter_0_x),
1341         .sload(GND),
1342         .ena(vsync_state_next_2_sqmuxa),
1343         .inverta(GND),
1344         .aload(GND),
1345         .regcascin(GND)
1346 );
1347 defparam vsync_state_5_.operation_mode="normal";
1348 defparam vsync_state_5_.output_mode="reg_only";
1349 defparam vsync_state_5_.lut_mask="eeee";
1350 defparam vsync_state_5_.synch_mode="on";
1351 defparam vsync_state_5_.sum_lutc_input="datac";
1352 // @13:300
1353   stratix_lcell vsync_state_4_ (
1354         .regout(vsync_state_4),
1355         .clk(clk_pin_c),
1356         .dataa(vsync_counter_0),
1357         .datab(vsync_counter_9),
1358         .datac(vsync_state_5),
1359         .datad(un14_vsync_counter_8),
1360         .aclr(GND),
1361         .sclr(un6_dly_counter_0_x),
1362         .sload(GND),
1363         .ena(vsync_state_next_2_sqmuxa),
1364         .inverta(GND),
1365         .aload(GND),
1366         .regcascin(GND)
1367 );
1368 defparam vsync_state_4_.operation_mode="normal";
1369 defparam vsync_state_4_.output_mode="reg_only";
1370 defparam vsync_state_4_.lut_mask="2000";
1371 defparam vsync_state_4_.synch_mode="on";
1372 defparam vsync_state_4_.sum_lutc_input="datac";
1373 // @13:300
1374   stratix_lcell vsync_state_3_ (
1375         .regout(vsync_state_3),
1376         .clk(clk_pin_c),
1377         .dataa(vsync_state_1),
1378         .datab(VCC),
1379         .datac(VCC),
1380         .datad(VCC),
1381         .aclr(GND),
1382         .sclr(un6_dly_counter_0_x),
1383         .sload(GND),
1384         .ena(vsync_state_next_2_sqmuxa),
1385         .inverta(GND),
1386         .aload(GND),
1387         .regcascin(GND)
1388 );
1389 defparam vsync_state_3_.operation_mode="normal";
1390 defparam vsync_state_3_.output_mode="reg_only";
1391 defparam vsync_state_3_.lut_mask="aaaa";
1392 defparam vsync_state_3_.synch_mode="on";
1393 defparam vsync_state_3_.sum_lutc_input="datac";
1394 // @13:300
1395   stratix_lcell vsync_state_2_ (
1396         .regout(vsync_state_2),
1397         .clk(clk_pin_c),
1398         .dataa(vsync_counter_0),
1399         .datab(vsync_counter_9),
1400         .datac(vsync_state_3),
1401         .datad(un14_vsync_counter_8),
1402         .aclr(GND),
1403         .sclr(un6_dly_counter_0_x),
1404         .sload(GND),
1405         .ena(vsync_state_next_2_sqmuxa),
1406         .inverta(GND),
1407         .aload(GND),
1408         .regcascin(GND)
1409 );
1410 defparam vsync_state_2_.operation_mode="normal";
1411 defparam vsync_state_2_.output_mode="reg_only";
1412 defparam vsync_state_2_.lut_mask="8000";
1413 defparam vsync_state_2_.synch_mode="on";
1414 defparam vsync_state_2_.sum_lutc_input="datac";
1415 // @13:187
1416   stratix_lcell hsync_state_5_ (
1417         .regout(hsync_state_5),
1418         .clk(clk_pin_c),
1419         .dataa(hsync_state_6),
1420         .datab(hsync_state_0),
1421         .datac(VCC),
1422         .datad(VCC),
1423         .aclr(GND),
1424         .sclr(un6_dly_counter_0_x),
1425         .sload(GND),
1426         .ena(hsync_state_3_0_0_0__g0_0),
1427         .inverta(GND),
1428         .aload(GND),
1429         .regcascin(GND)
1430 );
1431 defparam hsync_state_5_.operation_mode="normal";
1432 defparam hsync_state_5_.output_mode="reg_only";
1433 defparam hsync_state_5_.lut_mask="eeee";
1434 defparam hsync_state_5_.synch_mode="on";
1435 defparam hsync_state_5_.sum_lutc_input="datac";
1436 // @13:187
1437   stratix_lcell hsync_state_4_ (
1438         .regout(hsync_state_4),
1439         .clk(clk_pin_c),
1440         .dataa(hsync_state_5),
1441         .datab(un10_hsync_counter_3),
1442         .datac(un10_hsync_counter_1),
1443         .datad(un10_hsync_counter_4),
1444         .aclr(GND),
1445         .sclr(un6_dly_counter_0_x),
1446         .sload(GND),
1447         .ena(hsync_state_3_0_0_0__g0_0),
1448         .inverta(GND),
1449         .aload(GND),
1450         .regcascin(GND)
1451 );
1452 defparam hsync_state_4_.operation_mode="normal";
1453 defparam hsync_state_4_.output_mode="reg_only";
1454 defparam hsync_state_4_.lut_mask="8000";
1455 defparam hsync_state_4_.synch_mode="on";
1456 defparam hsync_state_4_.sum_lutc_input="datac";
1457 // @13:187
1458   stratix_lcell hsync_state_3_ (
1459         .regout(hsync_state_3),
1460         .clk(clk_pin_c),
1461         .dataa(hsync_state_1),
1462         .datab(VCC),
1463         .datac(VCC),
1464         .datad(VCC),
1465         .aclr(GND),
1466         .sclr(un6_dly_counter_0_x),
1467         .sload(GND),
1468         .ena(hsync_state_3_0_0_0__g0_0),
1469         .inverta(GND),
1470         .aload(GND),
1471         .regcascin(GND)
1472 );
1473 defparam hsync_state_3_.operation_mode="normal";
1474 defparam hsync_state_3_.output_mode="reg_only";
1475 defparam hsync_state_3_.lut_mask="aaaa";
1476 defparam hsync_state_3_.synch_mode="on";
1477 defparam hsync_state_3_.sum_lutc_input="datac";
1478 // @13:187
1479   stratix_lcell hsync_state_2_ (
1480         .regout(hsync_state_2),
1481         .clk(clk_pin_c),
1482         .dataa(hsync_state_3),
1483         .datab(un12_hsync_counter),
1484         .datac(VCC),
1485         .datad(VCC),
1486         .aclr(GND),
1487         .sclr(un6_dly_counter_0_x),
1488         .sload(GND),
1489         .ena(hsync_state_3_0_0_0__g0_0),
1490         .inverta(GND),
1491         .aload(GND),
1492         .regcascin(GND)
1493 );
1494 defparam hsync_state_2_.operation_mode="normal";
1495 defparam hsync_state_2_.output_mode="reg_only";
1496 defparam hsync_state_2_.lut_mask="8888";
1497 defparam hsync_state_2_.synch_mode="on";
1498 defparam hsync_state_2_.sum_lutc_input="datac";
1499 // @13:187
1500   stratix_lcell hsync_state_1_ (
1501         .regout(hsync_state_1),
1502         .clk(clk_pin_c),
1503         .dataa(hsync_state_4),
1504         .datab(un11_hsync_counter_2),
1505         .datac(un10_hsync_counter_1),
1506         .datad(un11_hsync_counter_3),
1507         .aclr(GND),
1508         .sclr(un6_dly_counter_0_x),
1509         .sload(GND),
1510         .ena(hsync_state_3_0_0_0__g0_0),
1511         .inverta(GND),
1512         .aload(GND),
1513         .regcascin(GND)
1514 );
1515 defparam hsync_state_1_.operation_mode="normal";
1516 defparam hsync_state_1_.output_mode="reg_only";
1517 defparam hsync_state_1_.lut_mask="8000";
1518 defparam hsync_state_1_.synch_mode="on";
1519 defparam hsync_state_1_.sum_lutc_input="datac";
1520 // @13:187
1521   stratix_lcell hsync_state_0_ (
1522         .regout(hsync_state_0),
1523         .clk(clk_pin_c),
1524         .dataa(hsync_state_2),
1525         .datab(un13_hsync_counter),
1526         .datac(VCC),
1527         .datad(VCC),
1528         .aclr(GND),
1529         .sclr(un6_dly_counter_0_x),
1530         .sload(GND),
1531         .ena(hsync_state_3_0_0_0__g0_0),
1532         .inverta(GND),
1533         .aload(GND),
1534         .regcascin(GND)
1535 );
1536 defparam hsync_state_0_.operation_mode="normal";
1537 defparam hsync_state_0_.output_mode="reg_only";
1538 defparam hsync_state_0_.lut_mask="8888";
1539 defparam hsync_state_0_.synch_mode="on";
1540 defparam hsync_state_0_.sum_lutc_input="datac";
1541 // @13:97
1542   stratix_lcell vsync_state_next_2_sqmuxa_cZ (
1543         .combout(vsync_state_next_2_sqmuxa),
1544         .clk(GND),
1545         .dataa(un6_dly_counter_0_x),
1546         .datab(vsync_state_next_1_sqmuxa_1),
1547         .datac(vsync_state_next_1_sqmuxa_3),
1548         .datad(un1_vsync_state_next_1_sqmuxa_0),
1549         .aclr(GND),
1550         .sclr(GND),
1551         .sload(GND),
1552         .ena(VCC),
1553         .inverta(GND),
1554         .aload(GND),
1555         .regcascin(GND)
1556 );
1557 defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal";
1558 defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only";
1559 defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab";
1560 defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off";
1561 defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac";
1562   stratix_lcell hsync_state_3_0_0_0__g0_0_cZ (
1563         .combout(hsync_state_3_0_0_0__g0_0),
1564         .clk(GND),
1565         .dataa(hsync_state_next_1_sqmuxa_1),
1566         .datab(hsync_state_next_1_sqmuxa_2),
1567         .datac(un6_dly_counter_0_x),
1568         .datad(un1_hsync_state_next_1_sqmuxa_0),
1569         .aclr(GND),
1570         .sclr(GND),
1571         .sload(GND),
1572         .ena(VCC),
1573         .inverta(GND),
1574         .aload(GND),
1575         .regcascin(GND)
1576 );
1577 defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal";
1578 defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only";
1579 defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1";
1580 defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off";
1581 defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac";
1582 // @13:206
1583   stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ (
1584         .combout(un1_hsync_state_next_1_sqmuxa_0),
1585         .clk(GND),
1586         .dataa(hsync_state_2),
1587         .datab(hsync_state_3),
1588         .datac(un13_hsync_counter),
1589         .datad(un12_hsync_counter),
1590         .aclr(GND),
1591         .sclr(GND),
1592         .sload(GND),
1593         .ena(VCC),
1594         .inverta(GND),
1595         .aload(GND),
1596         .regcascin(GND)
1597 );
1598 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1599 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1600 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace";
1601 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1602 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1603 // @13:319
1604   stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ (
1605         .combout(un1_vsync_state_next_1_sqmuxa_0),
1606         .clk(GND),
1607         .dataa(vsync_state_2),
1608         .datab(un12_vsync_counter_6),
1609         .datac(un15_vsync_counter_4),
1610         .datad(vsync_state_next_1_sqmuxa_2),
1611         .aclr(GND),
1612         .sclr(GND),
1613         .sload(GND),
1614         .ena(VCC),
1615         .inverta(GND),
1616         .aload(GND),
1617         .regcascin(GND)
1618 );
1619 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1620 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1621 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a";
1622 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1623 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1624   stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
1625         .combout(vsync_state_3_iv_0_0__g0_0_a3_0),
1626         .clk(GND),
1627         .dataa(vsync_state_2),
1628         .datab(un12_vsync_counter_6),
1629         .datac(un15_vsync_counter_4),
1630         .datad(VCC),
1631         .aclr(GND),
1632         .sclr(GND),
1633         .sload(GND),
1634         .ena(VCC),
1635         .inverta(GND),
1636         .aload(GND),
1637         .regcascin(GND)
1638 );
1639 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal";
1640 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only";
1641 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080";
1642 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off";
1643 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac";
1644 // @13:139
1645   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 (
1646         .combout(un10_line_counter_siglto8),
1647         .clk(GND),
1648         .dataa(line_counter_sig_6),
1649         .datab(line_counter_sig_7),
1650         .datac(line_counter_sig_8),
1651         .datad(un10_line_counter_siglto5),
1652         .aclr(GND),
1653         .sclr(GND),
1654         .sload(GND),
1655         .ena(VCC),
1656         .inverta(GND),
1657         .aload(GND),
1658         .regcascin(GND)
1659 );
1660 defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal";
1661 defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only";
1662 defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f";
1663 defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off";
1664 defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac";
1665 // @10:161
1666   stratix_lcell G_2 (
1667         .combout(G_2_i),
1668         .clk(GND),
1669         .dataa(hsync_state_0),
1670         .datab(hsync_state_6),
1671         .datac(un9_hsync_counterlt9),
1672         .datad(un6_dly_counter_0_x),
1673         .aclr(GND),
1674         .sclr(GND),
1675         .sload(GND),
1676         .ena(VCC),
1677         .inverta(GND),
1678         .aload(GND),
1679         .regcascin(GND)
1680 );
1681 defparam G_2.operation_mode="normal";
1682 defparam G_2.output_mode="comb_only";
1683 defparam G_2.lut_mask="0f1f";
1684 defparam G_2.synch_mode="off";
1685 defparam G_2.sum_lutc_input="datac";
1686 // @13:326
1687   stratix_lcell vsync_state_next_1_sqmuxa_1_cZ (
1688         .combout(vsync_state_next_1_sqmuxa_1),
1689         .clk(GND),
1690         .dataa(vsync_counter_0),
1691         .datab(vsync_counter_9),
1692         .datac(vsync_state_5),
1693         .datad(un14_vsync_counter_8),
1694         .aclr(GND),
1695         .sclr(GND),
1696         .sload(GND),
1697         .ena(VCC),
1698         .inverta(GND),
1699         .aload(GND),
1700         .regcascin(GND)
1701 );
1702 defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1703 defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1704 defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0";
1705 defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1706 defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1707 // @13:331
1708   stratix_lcell vsync_state_next_1_sqmuxa_2_cZ (
1709         .combout(vsync_state_next_1_sqmuxa_2),
1710         .clk(GND),
1711         .dataa(vsync_state_4),
1712         .datab(un12_vsync_counter_7),
1713         .datac(un13_vsync_counter_4),
1714         .datad(VCC),
1715         .aclr(GND),
1716         .sclr(GND),
1717         .sload(GND),
1718         .ena(VCC),
1719         .inverta(GND),
1720         .aload(GND),
1721         .regcascin(GND)
1722 );
1723 defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1724 defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1725 defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a";
1726 defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1727 defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1728 // @13:339
1729   stratix_lcell vsync_state_next_1_sqmuxa_3_cZ (
1730         .combout(vsync_state_next_1_sqmuxa_3),
1731         .clk(GND),
1732         .dataa(vsync_counter_0),
1733         .datab(vsync_counter_9),
1734         .datac(vsync_state_3),
1735         .datad(un14_vsync_counter_8),
1736         .aclr(GND),
1737         .sclr(GND),
1738         .sload(GND),
1739         .ena(VCC),
1740         .inverta(GND),
1741         .aload(GND),
1742         .regcascin(GND)
1743 );
1744 defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal";
1745 defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only";
1746 defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0";
1747 defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off";
1748 defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac";
1749 // @10:161
1750   stratix_lcell G_16 (
1751         .combout(G_16_i),
1752         .clk(GND),
1753         .dataa(vsync_state_0),
1754         .datab(vsync_state_6),
1755         .datac(un9_vsync_counterlt9),
1756         .datad(un6_dly_counter_0_x),
1757         .aclr(GND),
1758         .sclr(GND),
1759         .sload(GND),
1760         .ena(VCC),
1761         .inverta(GND),
1762         .aload(GND),
1763         .regcascin(GND)
1764 );
1765 defparam G_16.operation_mode="normal";
1766 defparam G_16.output_mode="comb_only";
1767 defparam G_16.lut_mask="0f1f";
1768 defparam G_16.synch_mode="off";
1769 defparam G_16.sum_lutc_input="datac";
1770 // @13:111
1771   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 (
1772         .combout(un10_column_counter_siglto9),
1773         .clk(GND),
1774         .dataa(column_counter_sig_7),
1775         .datab(column_counter_sig_8),
1776         .datac(column_counter_sig_9),
1777         .datad(un10_column_counter_siglt6),
1778         .aclr(GND),
1779         .sclr(GND),
1780         .sload(GND),
1781         .ena(VCC),
1782         .inverta(GND),
1783         .aload(GND),
1784         .regcascin(GND)
1785 );
1786 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal";
1787 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only";
1788 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f";
1789 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off";
1790 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac";
1791 // @13:218
1792   stratix_lcell hsync_state_next_1_sqmuxa_2_cZ (
1793         .combout(hsync_state_next_1_sqmuxa_2),
1794         .clk(GND),
1795         .dataa(hsync_state_4),
1796         .datab(un11_hsync_counter_2),
1797         .datac(un10_hsync_counter_1),
1798         .datad(un11_hsync_counter_3),
1799         .aclr(GND),
1800         .sclr(GND),
1801         .sload(GND),
1802         .ena(VCC),
1803         .inverta(GND),
1804         .aload(GND),
1805         .regcascin(GND)
1806 );
1807 defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1808 defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1809 defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa";
1810 defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1811 defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1812 // @13:213
1813   stratix_lcell hsync_state_next_1_sqmuxa_1_cZ (
1814         .combout(hsync_state_next_1_sqmuxa_1),
1815         .clk(GND),
1816         .dataa(hsync_state_5),
1817         .datab(un10_hsync_counter_3),
1818         .datac(un10_hsync_counter_1),
1819         .datad(un10_hsync_counter_4),
1820         .aclr(GND),
1821         .sclr(GND),
1822         .sload(GND),
1823         .ena(VCC),
1824         .inverta(GND),
1825         .aload(GND),
1826         .regcascin(GND)
1827 );
1828 defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1829 defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1830 defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa";
1831 defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1832 defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1833 // @13:231
1834   stratix_lcell HSYNC_FSM_next_un13_hsync_counter (
1835         .combout(un13_hsync_counter),
1836         .clk(GND),
1837         .dataa(hsync_counter_6),
1838         .datab(hsync_counter_7),
1839         .datac(un13_hsync_counter_2),
1840         .datad(un13_hsync_counter_7),
1841         .aclr(GND),
1842         .sclr(GND),
1843         .sload(GND),
1844         .ena(VCC),
1845         .inverta(GND),
1846         .aload(GND),
1847         .regcascin(GND)
1848 );
1849 defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal";
1850 defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only";
1851 defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000";
1852 defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off";
1853 defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac";
1854 // @13:172
1855   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 (
1856         .combout(un9_hsync_counterlt9),
1857         .clk(GND),
1858         .dataa(hsync_counter_8),
1859         .datab(hsync_counter_9),
1860         .datac(un9_hsync_counterlt9_3),
1861         .datad(un13_hsync_counter_7),
1862         .aclr(GND),
1863         .sclr(GND),
1864         .sload(GND),
1865         .ena(VCC),
1866         .inverta(GND),
1867         .aload(GND),
1868         .regcascin(GND)
1869 );
1870 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal";
1871 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only";
1872 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff";
1873 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off";
1874 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac";
1875 // @13:281
1876   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 (
1877         .combout(un9_vsync_counterlt9),
1878         .clk(GND),
1879         .dataa(vsync_counter_4),
1880         .datab(vsync_counter_5),
1881         .datac(un9_vsync_counterlt9_5),
1882         .datad(un9_vsync_counterlt9_6),
1883         .aclr(GND),
1884         .sclr(GND),
1885         .sload(GND),
1886         .ena(VCC),
1887         .inverta(GND),
1888         .aload(GND),
1889         .regcascin(GND)
1890 );
1891 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal";
1892 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only";
1893 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7";
1894 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off";
1895 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac";
1896 // @13:226
1897   stratix_lcell HSYNC_FSM_next_un12_hsync_counter (
1898         .combout(un12_hsync_counter),
1899         .clk(GND),
1900         .dataa(hsync_counter_0),
1901         .datab(hsync_counter_1),
1902         .datac(un12_hsync_counter_3),
1903         .datad(un12_hsync_counter_4),
1904         .aclr(GND),
1905         .sclr(GND),
1906         .sload(GND),
1907         .ena(VCC),
1908         .inverta(GND),
1909         .aload(GND),
1910         .regcascin(GND)
1911 );
1912 defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal";
1913 defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only";
1914 defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000";
1915 defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off";
1916 defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac";
1917 // @13:139
1918   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 (
1919         .combout(un10_line_counter_siglto5),
1920         .clk(GND),
1921         .dataa(line_counter_sig_1),
1922         .datab(line_counter_sig_2),
1923         .datac(line_counter_sig_5),
1924         .datad(un10_line_counter_siglt4_2),
1925         .aclr(GND),
1926         .sclr(GND),
1927         .sload(GND),
1928         .ena(VCC),
1929         .inverta(GND),
1930         .aload(GND),
1931         .regcascin(GND)
1932 );
1933 defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal";
1934 defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only";
1935 defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07";
1936 defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off";
1937 defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac";
1938 // @13:344
1939   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 (
1940         .combout(un15_vsync_counter_4),
1941         .clk(GND),
1942         .dataa(vsync_counter_1),
1943         .datab(vsync_counter_4),
1944         .datac(un15_vsync_counter_3),
1945         .datad(VCC),
1946         .aclr(GND),
1947         .sclr(GND),
1948         .sload(GND),
1949         .ena(VCC),
1950         .inverta(GND),
1951         .aload(GND),
1952         .regcascin(GND)
1953 );
1954 defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal";
1955 defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only";
1956 defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010";
1957 defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off";
1958 defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac";
1959 // @13:331
1960   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 (
1961         .combout(un13_vsync_counter_4),
1962         .clk(GND),
1963         .dataa(vsync_counter_0),
1964         .datab(vsync_counter_5),
1965         .datac(un13_vsync_counter_3),
1966         .datad(VCC),
1967         .aclr(GND),
1968         .sclr(GND),
1969         .sload(GND),
1970         .ena(VCC),
1971         .inverta(GND),
1972         .aload(GND),
1973         .regcascin(GND)
1974 );
1975 defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal";
1976 defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only";
1977 defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080";
1978 defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off";
1979 defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac";
1980 // @13:111
1981   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 (
1982         .combout(un10_column_counter_siglt6),
1983         .clk(GND),
1984         .dataa(column_counter_sig_4),
1985         .datab(column_counter_sig_6),
1986         .datac(column_counter_sig_5),
1987         .datad(un10_column_counter_siglt6_4),
1988         .aclr(GND),
1989         .sclr(GND),
1990         .sload(GND),
1991         .ena(VCC),
1992         .inverta(GND),
1993         .aload(GND),
1994         .regcascin(GND)
1995 );
1996 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal";
1997 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only";
1998 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="ff7f";
1999 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off";
2000 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac";
2001 // @13:169
2002   stratix_lcell hsync_counter_next_1_sqmuxa_cZ (
2003         .combout(hsync_counter_next_1_sqmuxa),
2004         .clk(GND),
2005         .dataa(reset_pin_c),
2006         .datab(dly_counter_0),
2007         .datac(dly_counter_1),
2008         .datad(d_set_hsync_counter),
2009         .aclr(GND),
2010         .sclr(GND),
2011         .sload(GND),
2012         .ena(VCC),
2013         .inverta(GND),
2014         .aload(GND),
2015         .regcascin(GND)
2016 );
2017 defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2018 defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2019 defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2020 defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2021 defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2022 // @13:339
2023   stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 (
2024         .combout(un14_vsync_counter_8),
2025         .clk(GND),
2026         .dataa(un12_vsync_counter_6),
2027         .datab(un12_vsync_counter_7),
2028         .datac(VCC),
2029         .datad(VCC),
2030         .aclr(GND),
2031         .sclr(GND),
2032         .sload(GND),
2033         .ena(VCC),
2034         .inverta(GND),
2035         .aload(GND),
2036         .regcascin(GND)
2037 );
2038 defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal";
2039 defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only";
2040 defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888";
2041 defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off";
2042 defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac";
2043 // @13:139
2044   stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ (
2045         .combout(line_counter_next_0_sqmuxa_1_1),
2046         .clk(GND),
2047         .dataa(reset_pin_c),
2048         .datab(dly_counter_0),
2049         .datac(dly_counter_1),
2050         .datad(vsync_state_1),
2051         .aclr(GND),
2052         .sclr(GND),
2053         .sload(GND),
2054         .ena(VCC),
2055         .inverta(GND),
2056         .aload(GND),
2057         .regcascin(GND)
2058 );
2059 defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2060 defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2061 defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2062 defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2063 defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2064   stratix_lcell v_sync_1_0_0_0_g1_cZ (
2065         .combout(v_sync_1_0_0_0_g1),
2066         .clk(GND),
2067         .dataa(vsync_state_2),
2068         .datab(v_sync),
2069         .datac(vsync_state_4),
2070         .datad(un1_vsync_state_2_0),
2071         .aclr(GND),
2072         .sclr(GND),
2073         .sload(GND),
2074         .ena(VCC),
2075         .inverta(GND),
2076         .aload(GND),
2077         .regcascin(GND)
2078 );
2079 defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2080 defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2081 defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2082 defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off";
2083 defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2084   stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ (
2085         .combout(h_enable_sig_1_0_0_0_g0_i_o4),
2086         .clk(GND),
2087         .dataa(vsync_state_4),
2088         .datab(vsync_state_5),
2089         .datac(un6_dly_counter_0_x),
2090         .datad(VCC),
2091         .aclr(GND),
2092         .sclr(GND),
2093         .sload(GND),
2094         .ena(VCC),
2095         .inverta(GND),
2096         .aload(GND),
2097         .regcascin(GND)
2098 );
2099 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2100 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2101 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2102 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2103 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2104 // @13:278
2105   stratix_lcell vsync_counter_next_1_sqmuxa_cZ (
2106         .combout(vsync_counter_next_1_sqmuxa),
2107         .clk(GND),
2108         .dataa(reset_pin_c),
2109         .datab(dly_counter_0),
2110         .datac(dly_counter_1),
2111         .datad(d_set_vsync_counter),
2112         .aclr(GND),
2113         .sclr(GND),
2114         .sload(GND),
2115         .ena(VCC),
2116         .inverta(GND),
2117         .aload(GND),
2118         .regcascin(GND)
2119 );
2120 defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2121 defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2122 defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2123 defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2124 defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2125   stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ (
2126         .combout(v_enable_sig_1_0_0_0_g0_i_o4),
2127         .clk(GND),
2128         .dataa(hsync_state_4),
2129         .datab(hsync_state_5),
2130         .datac(un6_dly_counter_0_x),
2131         .datad(VCC),
2132         .aclr(GND),
2133         .sclr(GND),
2134         .sload(GND),
2135         .ena(VCC),
2136         .inverta(GND),
2137         .aload(GND),
2138         .regcascin(GND)
2139 );
2140 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2141 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2142 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2143 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2144 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2145   stratix_lcell h_sync_1_0_0_0_g1_cZ (
2146         .combout(h_sync_1_0_0_0_g1),
2147         .clk(GND),
2148         .dataa(hsync_state_2),
2149         .datab(h_sync),
2150         .datac(hsync_state_4),
2151         .datad(un1_hsync_state_3_0),
2152         .aclr(GND),
2153         .sclr(GND),
2154         .sload(GND),
2155         .ena(VCC),
2156         .inverta(GND),
2157         .aload(GND),
2158         .regcascin(GND)
2159 );
2160 defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2161 defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2162 defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2163 defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off";
2164 defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2165 // @13:111
2166   stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ (
2167         .combout(column_counter_next_0_sqmuxa_1_1),
2168         .clk(GND),
2169         .dataa(reset_pin_c),
2170         .datab(dly_counter_0),
2171         .datac(dly_counter_1),
2172         .datad(hsync_state_1),
2173         .aclr(GND),
2174         .sclr(GND),
2175         .sload(GND),
2176         .ena(VCC),
2177         .inverta(GND),
2178         .aload(GND),
2179         .regcascin(GND)
2180 );
2181 defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2182 defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2183 defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2184 defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2185 defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2186 // @13:226
2187   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 (
2188         .combout(un12_hsync_counter_4),
2189         .clk(GND),
2190         .dataa(hsync_counter_6),
2191         .datab(hsync_counter_7),
2192         .datac(hsync_counter_9),
2193         .datad(hsync_counter_3),
2194         .aclr(GND),
2195         .sclr(GND),
2196         .sload(GND),
2197         .ena(VCC),
2198         .inverta(GND),
2199         .aload(GND),
2200         .regcascin(GND)
2201 );
2202 defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal";
2203 defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only";
2204 defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010";
2205 defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off";
2206 defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac";
2207 // @13:226
2208   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 (
2209         .combout(un12_hsync_counter_3),
2210         .clk(GND),
2211         .dataa(hsync_counter_2),
2212         .datab(hsync_counter_8),
2213         .datac(hsync_counter_4),
2214         .datad(hsync_counter_5),
2215         .aclr(GND),
2216         .sclr(GND),
2217         .sload(GND),
2218         .ena(VCC),
2219         .inverta(GND),
2220         .aload(GND),
2221         .regcascin(GND)
2222 );
2223 defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal";
2224 defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only";
2225 defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0008";
2226 defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off";
2227 defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac";
2228 // @13:218
2229   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 (
2230         .combout(un11_hsync_counter_3),
2231         .clk(GND),
2232         .dataa(hsync_counter_0),
2233         .datab(hsync_counter_1),
2234         .datac(hsync_counter_3),
2235         .datad(hsync_counter_4),
2236         .aclr(GND),
2237         .sclr(GND),
2238         .sload(GND),
2239         .ena(VCC),
2240         .inverta(GND),
2241         .aload(GND),
2242         .regcascin(GND)
2243 );
2244 defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal";
2245 defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only";
2246 defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008";
2247 defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off";
2248 defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac";
2249 // @13:218
2250   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 (
2251         .combout(un11_hsync_counter_2),
2252         .clk(GND),
2253         .dataa(hsync_counter_2),
2254         .datab(hsync_counter_7),
2255         .datac(hsync_counter_6),
2256         .datad(VCC),
2257         .aclr(GND),
2258         .sclr(GND),
2259         .sload(GND),
2260         .ena(VCC),
2261         .inverta(GND),
2262         .aload(GND),
2263         .regcascin(GND)
2264 );
2265 defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal";
2266 defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only";
2267 defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808";
2268 defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off";
2269 defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac";
2270 // @13:172
2271   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
2272         .combout(un9_hsync_counterlt9_3),
2273         .clk(GND),
2274         .dataa(hsync_counter_6),
2275         .datab(hsync_counter_7),
2276         .datac(hsync_counter_4),
2277         .datad(hsync_counter_5),
2278         .aclr(GND),
2279         .sclr(GND),
2280         .sload(GND),
2281         .ena(VCC),
2282         .inverta(GND),
2283         .aload(GND),
2284         .regcascin(GND)
2285 );
2286 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal";
2287 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only";
2288 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff";
2289 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off";
2290 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac";
2291 // @13:231
2292   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 (
2293         .combout(un13_hsync_counter_2),
2294         .clk(GND),
2295         .dataa(hsync_counter_8),
2296         .datab(hsync_counter_9),
2297         .datac(hsync_counter_4),
2298         .datad(hsync_counter_5),
2299         .aclr(GND),
2300         .sclr(GND),
2301         .sload(GND),
2302         .ena(VCC),
2303         .inverta(GND),
2304         .aload(GND),
2305         .regcascin(GND)
2306 );
2307 defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal";
2308 defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only";
2309 defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080";
2310 defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off";
2311 defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac";
2312 // @13:281
2313   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
2314         .combout(un9_vsync_counterlt9_6),
2315         .clk(GND),
2316         .dataa(vsync_counter_2),
2317         .datab(vsync_counter_3),
2318         .datac(vsync_counter_0),
2319         .datad(vsync_counter_1),
2320         .aclr(GND),
2321         .sclr(GND),
2322         .sload(GND),
2323         .ena(VCC),
2324         .inverta(GND),
2325         .aload(GND),
2326         .regcascin(GND)
2327 );
2328 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal";
2329 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only";
2330 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff";
2331 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off";
2332 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac";
2333 // @13:281
2334   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
2335         .combout(un9_vsync_counterlt9_5),
2336         .clk(GND),
2337         .dataa(vsync_counter_8),
2338         .datab(vsync_counter_9),
2339         .datac(vsync_counter_6),
2340         .datad(vsync_counter_7),
2341         .aclr(GND),
2342         .sclr(GND),
2343         .sload(GND),
2344         .ena(VCC),
2345         .inverta(GND),
2346         .aload(GND),
2347         .regcascin(GND)
2348 );
2349 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal";
2350 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only";
2351 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff";
2352 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off";
2353 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac";
2354 // @13:213
2355   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 (
2356         .combout(un10_hsync_counter_4),
2357         .clk(GND),
2358         .dataa(hsync_counter_4),
2359         .datab(hsync_counter_6),
2360         .datac(hsync_counter_1),
2361         .datad(hsync_counter_3),
2362         .aclr(GND),
2363         .sclr(GND),
2364         .sload(GND),
2365         .ena(VCC),
2366         .inverta(GND),
2367         .aload(GND),
2368         .regcascin(GND)
2369 );
2370 defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal";
2371 defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only";
2372 defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000";
2373 defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off";
2374 defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac";
2375 // @13:213
2376   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 (
2377         .combout(un10_hsync_counter_3),
2378         .clk(GND),
2379         .dataa(hsync_counter_0),
2380         .datab(hsync_counter_7),
2381         .datac(hsync_counter_2),
2382         .datad(VCC),
2383         .aclr(GND),
2384         .sclr(GND),
2385         .sload(GND),
2386         .ena(VCC),
2387         .inverta(GND),
2388         .aload(GND),
2389         .regcascin(GND)
2390 );
2391 defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal";
2392 defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only";
2393 defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101";
2394 defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off";
2395 defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac";
2396 // @13:344
2397   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 (
2398         .combout(un15_vsync_counter_3),
2399         .clk(GND),
2400         .dataa(vsync_counter_9),
2401         .datab(vsync_counter_2),
2402         .datac(vsync_counter_3),
2403         .datad(vsync_counter_0),
2404         .aclr(GND),
2405         .sclr(GND),
2406         .sload(GND),
2407         .ena(VCC),
2408         .inverta(GND),
2409         .aload(GND),
2410         .regcascin(GND)
2411 );
2412 defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal";
2413 defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only";
2414 defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0020";
2415 defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off";
2416 defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac";
2417 // @13:331
2418   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 (
2419         .combout(un13_vsync_counter_3),
2420         .clk(GND),
2421         .dataa(vsync_counter_6),
2422         .datab(vsync_counter_7),
2423         .datac(vsync_counter_8),
2424         .datad(vsync_counter_9),
2425         .aclr(GND),
2426         .sclr(GND),
2427         .sload(GND),
2428         .ena(VCC),
2429         .inverta(GND),
2430         .aload(GND),
2431         .regcascin(GND)
2432 );
2433 defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal";
2434 defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only";
2435 defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001";
2436 defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off";
2437 defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac";
2438 // @13:111
2439   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_4 (
2440         .combout(un10_column_counter_siglt6_4),
2441         .clk(GND),
2442         .dataa(column_counter_sig_2),
2443         .datab(column_counter_sig_3),
2444         .datac(column_counter_sig_0),
2445         .datad(column_counter_sig_1),
2446         .aclr(GND),
2447         .sclr(GND),
2448         .sload(GND),
2449         .ena(VCC),
2450         .inverta(GND),
2451         .aload(GND),
2452         .regcascin(GND)
2453 );
2454 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.operation_mode="normal";
2455 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.output_mode="comb_only";
2456 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.lut_mask="7fff";
2457 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.synch_mode="off";
2458 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.sum_lutc_input="datac";
2459 // @13:139
2460   stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 (
2461         .combout(un10_line_counter_siglt4_2),
2462         .clk(GND),
2463         .dataa(line_counter_sig_3),
2464         .datab(line_counter_sig_4),
2465         .datac(line_counter_sig_0),
2466         .datad(VCC),
2467         .aclr(GND),
2468         .sclr(GND),
2469         .sload(GND),
2470         .ena(VCC),
2471         .inverta(GND),
2472         .aload(GND),
2473         .regcascin(GND)
2474 );
2475 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal";
2476 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only";
2477 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f";
2478 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off";
2479 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac";
2480 // @13:213
2481   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 (
2482         .combout(un10_hsync_counter_1),
2483         .clk(GND),
2484         .dataa(hsync_counter_5),
2485         .datab(hsync_counter_8),
2486         .datac(hsync_counter_9),
2487         .datad(VCC),
2488         .aclr(GND),
2489         .sclr(GND),
2490         .sload(GND),
2491         .ena(VCC),
2492         .inverta(GND),
2493         .aload(GND),
2494         .regcascin(GND)
2495 );
2496 defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal";
2497 defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only";
2498 defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101";
2499 defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off";
2500 defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac";
2501 // @13:326
2502   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 (
2503         .combout(un12_vsync_counter_6),
2504         .clk(GND),
2505         .dataa(vsync_counter_7),
2506         .datab(vsync_counter_8),
2507         .datac(vsync_counter_5),
2508         .datad(vsync_counter_6),
2509         .aclr(GND),
2510         .sclr(GND),
2511         .sload(GND),
2512         .ena(VCC),
2513         .inverta(GND),
2514         .aload(GND),
2515         .regcascin(GND)
2516 );
2517 defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal";
2518 defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only";
2519 defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001";
2520 defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off";
2521 defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac";
2522 // @13:326
2523   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 (
2524         .combout(un12_vsync_counter_7),
2525         .clk(GND),
2526         .dataa(vsync_counter_3),
2527         .datab(vsync_counter_4),
2528         .datac(vsync_counter_1),
2529         .datad(vsync_counter_2),
2530         .aclr(GND),
2531         .sclr(GND),
2532         .sload(GND),
2533         .ena(VCC),
2534         .inverta(GND),
2535         .aload(GND),
2536         .regcascin(GND)
2537 );
2538 defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal";
2539 defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only";
2540 defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001";
2541 defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off";
2542 defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac";
2543 // @13:231
2544   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 (
2545         .combout(un13_hsync_counter_7),
2546         .clk(GND),
2547         .dataa(hsync_counter_2),
2548         .datab(hsync_counter_3),
2549         .datac(hsync_counter_0),
2550         .datad(hsync_counter_1),
2551         .aclr(GND),
2552         .sclr(GND),
2553         .sload(GND),
2554         .ena(VCC),
2555         .inverta(GND),
2556         .aload(GND),
2557         .regcascin(GND)
2558 );
2559 defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal";
2560 defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only";
2561 defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000";
2562 defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off";
2563 defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac";
2564 // @13:206
2565   stratix_lcell un1_hsync_state_3_0_cZ (
2566         .combout(un1_hsync_state_3_0),
2567         .clk(GND),
2568         .dataa(hsync_state_3),
2569         .datab(hsync_state_1),
2570         .datac(VCC),
2571         .datad(VCC),
2572         .aclr(GND),
2573         .sclr(GND),
2574         .sload(GND),
2575         .ena(VCC),
2576         .inverta(GND),
2577         .aload(GND),
2578         .regcascin(GND)
2579 );
2580 defparam un1_hsync_state_3_0_cZ.operation_mode="normal";
2581 defparam un1_hsync_state_3_0_cZ.output_mode="comb_only";
2582 defparam un1_hsync_state_3_0_cZ.lut_mask="eeee";
2583 defparam un1_hsync_state_3_0_cZ.synch_mode="off";
2584 defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac";
2585 // @13:319
2586   stratix_lcell un1_vsync_state_2_0_cZ (
2587         .combout(un1_vsync_state_2_0),
2588         .clk(GND),
2589         .dataa(vsync_state_3),
2590         .datab(vsync_state_1),
2591         .datac(VCC),
2592         .datad(VCC),
2593         .aclr(GND),
2594         .sclr(GND),
2595         .sload(GND),
2596         .ena(VCC),
2597         .inverta(GND),
2598         .aload(GND),
2599         .regcascin(GND)
2600 );
2601 defparam un1_vsync_state_2_0_cZ.operation_mode="normal";
2602 defparam un1_vsync_state_2_0_cZ.output_mode="comb_only";
2603 defparam un1_vsync_state_2_0_cZ.lut_mask="eeee";
2604 defparam un1_vsync_state_2_0_cZ.synch_mode="off";
2605 defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac";
2606 // @13:248
2607   stratix_lcell d_set_hsync_counter_cZ (
2608         .combout(d_set_hsync_counter),
2609         .clk(GND),
2610         .dataa(hsync_state_6),
2611         .datab(hsync_state_0),
2612         .datac(VCC),
2613         .datad(VCC),
2614         .aclr(GND),
2615         .sclr(GND),
2616         .sload(GND),
2617         .ena(VCC),
2618         .inverta(GND),
2619         .aload(GND),
2620         .regcascin(GND)
2621 );
2622 defparam d_set_hsync_counter_cZ.operation_mode="normal";
2623 defparam d_set_hsync_counter_cZ.output_mode="comb_only";
2624 defparam d_set_hsync_counter_cZ.lut_mask="eeee";
2625 defparam d_set_hsync_counter_cZ.synch_mode="off";
2626 defparam d_set_hsync_counter_cZ.sum_lutc_input="datac";
2627 // @13:361
2628   stratix_lcell d_set_vsync_counter_cZ (
2629         .combout(d_set_vsync_counter),
2630         .clk(GND),
2631         .dataa(vsync_state_6),
2632         .datab(vsync_state_0),
2633         .datac(VCC),
2634         .datad(VCC),
2635         .aclr(GND),
2636         .sclr(GND),
2637         .sload(GND),
2638         .ena(VCC),
2639         .inverta(GND),
2640         .aload(GND),
2641         .regcascin(GND)
2642 );
2643 defparam d_set_vsync_counter_cZ.operation_mode="normal";
2644 defparam d_set_vsync_counter_cZ.output_mode="comb_only";
2645 defparam d_set_vsync_counter_cZ.lut_mask="eeee";
2646 defparam d_set_vsync_counter_cZ.synch_mode="off";
2647 defparam d_set_vsync_counter_cZ.sum_lutc_input="datac";
2648 // @13:141
2649   stratix_lcell un1_line_counter_sig_9_ (
2650         .combout(un1_line_counter_sig_combout[9]),
2651         .clk(GND),
2652         .dataa(line_counter_sig_7),
2653         .datab(line_counter_sig_8),
2654         .datac(VCC),
2655         .datad(VCC),
2656         .aclr(GND),
2657         .sclr(GND),
2658         .sload(GND),
2659         .ena(VCC),
2660         .cin(un1_line_counter_sig_cout[7]),
2661         .inverta(GND),
2662         .aload(GND),
2663         .regcascin(GND)
2664 );
2665 defparam un1_line_counter_sig_9_.cin_used="true";
2666 defparam un1_line_counter_sig_9_.operation_mode="normal";
2667 defparam un1_line_counter_sig_9_.output_mode="comb_only";
2668 defparam un1_line_counter_sig_9_.lut_mask="6c6c";
2669 defparam un1_line_counter_sig_9_.synch_mode="off";
2670 defparam un1_line_counter_sig_9_.sum_lutc_input="cin";
2671 // @13:141
2672   stratix_lcell un1_line_counter_sig_8_ (
2673         .combout(un1_line_counter_sig_combout[8]),
2674         .clk(GND),
2675         .dataa(line_counter_sig_7),
2676         .datab(VCC),
2677         .datac(VCC),
2678         .datad(VCC),
2679         .aclr(GND),
2680         .sclr(GND),
2681         .sload(GND),
2682         .ena(VCC),
2683         .cin(un1_line_counter_sig_cout[6]),
2684         .inverta(GND),
2685         .aload(GND),
2686         .regcascin(GND)
2687 );
2688 defparam un1_line_counter_sig_8_.cin_used="true";
2689 defparam un1_line_counter_sig_8_.operation_mode="normal";
2690 defparam un1_line_counter_sig_8_.output_mode="comb_only";
2691 defparam un1_line_counter_sig_8_.lut_mask="5a5a";
2692 defparam un1_line_counter_sig_8_.synch_mode="off";
2693 defparam un1_line_counter_sig_8_.sum_lutc_input="cin";
2694 // @13:141
2695   stratix_lcell un1_line_counter_sig_7_ (
2696         .combout(un1_line_counter_sig_combout[7]),
2697         .cout(un1_line_counter_sig_cout[7]),
2698         .clk(GND),
2699         .dataa(line_counter_sig_5),
2700         .datab(line_counter_sig_6),
2701         .datac(VCC),
2702         .datad(VCC),
2703         .aclr(GND),
2704         .sclr(GND),
2705         .sload(GND),
2706         .ena(VCC),
2707         .cin(un1_line_counter_sig_cout[5]),
2708         .inverta(GND),
2709         .aload(GND),
2710         .regcascin(GND)
2711 );
2712 defparam un1_line_counter_sig_7_.cin_used="true";
2713 defparam un1_line_counter_sig_7_.operation_mode="arithmetic";
2714 defparam un1_line_counter_sig_7_.output_mode="comb_only";
2715 defparam un1_line_counter_sig_7_.lut_mask="6c80";
2716 defparam un1_line_counter_sig_7_.synch_mode="off";
2717 defparam un1_line_counter_sig_7_.sum_lutc_input="cin";
2718 // @13:141
2719   stratix_lcell un1_line_counter_sig_6_ (
2720         .combout(un1_line_counter_sig_combout[6]),
2721         .cout(un1_line_counter_sig_cout[6]),
2722         .clk(GND),
2723         .dataa(line_counter_sig_5),
2724         .datab(line_counter_sig_6),
2725         .datac(VCC),
2726         .datad(VCC),
2727         .aclr(GND),
2728         .sclr(GND),
2729         .sload(GND),
2730         .ena(VCC),
2731         .cin(un1_line_counter_sig_cout[4]),
2732         .inverta(GND),
2733         .aload(GND),
2734         .regcascin(GND)
2735 );
2736 defparam un1_line_counter_sig_6_.cin_used="true";
2737 defparam un1_line_counter_sig_6_.operation_mode="arithmetic";
2738 defparam un1_line_counter_sig_6_.output_mode="comb_only";
2739 defparam un1_line_counter_sig_6_.lut_mask="5a80";
2740 defparam un1_line_counter_sig_6_.synch_mode="off";
2741 defparam un1_line_counter_sig_6_.sum_lutc_input="cin";
2742 // @13:141
2743   stratix_lcell un1_line_counter_sig_5_ (
2744         .combout(un1_line_counter_sig_combout[5]),
2745         .cout(un1_line_counter_sig_cout[5]),
2746         .clk(GND),
2747         .dataa(line_counter_sig_3),
2748         .datab(line_counter_sig_4),
2749         .datac(VCC),
2750         .datad(VCC),
2751         .aclr(GND),
2752         .sclr(GND),
2753         .sload(GND),
2754         .ena(VCC),
2755         .cin(un1_line_counter_sig_cout[3]),
2756         .inverta(GND),
2757         .aload(GND),
2758         .regcascin(GND)
2759 );
2760 defparam un1_line_counter_sig_5_.cin_used="true";
2761 defparam un1_line_counter_sig_5_.operation_mode="arithmetic";
2762 defparam un1_line_counter_sig_5_.output_mode="comb_only";
2763 defparam un1_line_counter_sig_5_.lut_mask="6c80";
2764 defparam un1_line_counter_sig_5_.synch_mode="off";
2765 defparam un1_line_counter_sig_5_.sum_lutc_input="cin";
2766 // @13:141
2767   stratix_lcell un1_line_counter_sig_4_ (
2768         .combout(un1_line_counter_sig_combout[4]),
2769         .cout(un1_line_counter_sig_cout[4]),
2770         .clk(GND),
2771         .dataa(line_counter_sig_3),
2772         .datab(line_counter_sig_4),
2773         .datac(VCC),
2774         .datad(VCC),
2775         .aclr(GND),
2776         .sclr(GND),
2777         .sload(GND),
2778         .ena(VCC),
2779         .cin(un1_line_counter_sig_cout[2]),
2780         .inverta(GND),
2781         .aload(GND),
2782         .regcascin(GND)
2783 );
2784 defparam un1_line_counter_sig_4_.cin_used="true";
2785 defparam un1_line_counter_sig_4_.operation_mode="arithmetic";
2786 defparam un1_line_counter_sig_4_.output_mode="comb_only";
2787 defparam un1_line_counter_sig_4_.lut_mask="5a80";
2788 defparam un1_line_counter_sig_4_.synch_mode="off";
2789 defparam un1_line_counter_sig_4_.sum_lutc_input="cin";
2790 // @13:141
2791   stratix_lcell un1_line_counter_sig_3_ (
2792         .combout(un1_line_counter_sig_combout[3]),
2793         .cout(un1_line_counter_sig_cout[3]),
2794         .clk(GND),
2795         .dataa(line_counter_sig_1),
2796         .datab(line_counter_sig_2),
2797         .datac(VCC),
2798         .datad(VCC),
2799         .aclr(GND),
2800         .sclr(GND),
2801         .sload(GND),
2802         .ena(VCC),
2803         .cin(un1_line_counter_sig_cout[1]),
2804         .inverta(GND),
2805         .aload(GND),
2806         .regcascin(GND)
2807 );
2808 defparam un1_line_counter_sig_3_.cin_used="true";
2809 defparam un1_line_counter_sig_3_.operation_mode="arithmetic";
2810 defparam un1_line_counter_sig_3_.output_mode="comb_only";
2811 defparam un1_line_counter_sig_3_.lut_mask="6c80";
2812 defparam un1_line_counter_sig_3_.synch_mode="off";
2813 defparam un1_line_counter_sig_3_.sum_lutc_input="cin";
2814 // @13:141
2815   stratix_lcell un1_line_counter_sig_2_ (
2816         .combout(un1_line_counter_sig_combout[2]),
2817         .cout(un1_line_counter_sig_cout[2]),
2818         .clk(GND),
2819         .dataa(line_counter_sig_1),
2820         .datab(line_counter_sig_2),
2821         .datac(VCC),
2822         .datad(VCC),
2823         .aclr(GND),
2824         .sclr(GND),
2825         .sload(GND),
2826         .ena(VCC),
2827         .cin(un1_line_counter_sig_a_cout[1]),
2828         .inverta(GND),
2829         .aload(GND),
2830         .regcascin(GND)
2831 );
2832 defparam un1_line_counter_sig_2_.cin_used="true";
2833 defparam un1_line_counter_sig_2_.operation_mode="arithmetic";
2834 defparam un1_line_counter_sig_2_.output_mode="comb_only";
2835 defparam un1_line_counter_sig_2_.lut_mask="5a80";
2836 defparam un1_line_counter_sig_2_.synch_mode="off";
2837 defparam un1_line_counter_sig_2_.sum_lutc_input="cin";
2838 // @13:141
2839   stratix_lcell un1_line_counter_sig_a_1_ (
2840         .cout(un1_line_counter_sig_a_cout[1]),
2841         .clk(GND),
2842         .dataa(d_set_hsync_counter),
2843         .datab(line_counter_sig_0),
2844         .datac(VCC),
2845         .datad(VCC),
2846         .aclr(GND),
2847         .sclr(GND),
2848         .sload(GND),
2849         .ena(VCC),
2850         .inverta(GND),
2851         .aload(GND),
2852         .regcascin(GND)
2853 );
2854 defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic";
2855 defparam un1_line_counter_sig_a_1_.output_mode="comb_only";
2856 defparam un1_line_counter_sig_a_1_.lut_mask="0088";
2857 defparam un1_line_counter_sig_a_1_.synch_mode="off";
2858 defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac";
2859 // @13:141
2860   stratix_lcell un1_line_counter_sig_1_ (
2861         .combout(un1_line_counter_sig_combout[1]),
2862         .cout(un1_line_counter_sig_cout[1]),
2863         .clk(GND),
2864         .dataa(d_set_hsync_counter),
2865         .datab(line_counter_sig_0),
2866         .datac(VCC),
2867         .datad(VCC),
2868         .aclr(GND),
2869         .sclr(GND),
2870         .sload(GND),
2871         .ena(VCC),
2872         .inverta(GND),
2873         .aload(GND),
2874         .regcascin(GND)
2875 );
2876 defparam un1_line_counter_sig_1_.operation_mode="arithmetic";
2877 defparam un1_line_counter_sig_1_.output_mode="comb_only";
2878 defparam un1_line_counter_sig_1_.lut_mask="6688";
2879 defparam un1_line_counter_sig_1_.synch_mode="off";
2880 defparam un1_line_counter_sig_1_.sum_lutc_input="datac";
2881 // @13:112
2882   stratix_lcell un2_column_counter_next_9_ (
2883         .combout(un2_column_counter_next_combout[9]),
2884         .clk(GND),
2885         .dataa(column_counter_sig_8),
2886         .datab(column_counter_sig_9),
2887         .datac(VCC),
2888         .datad(VCC),
2889         .aclr(GND),
2890         .sclr(GND),
2891         .sload(GND),
2892         .ena(VCC),
2893         .cin(un2_column_counter_next_cout[7]),
2894         .inverta(GND),
2895         .aload(GND),
2896         .regcascin(GND)
2897 );
2898 defparam un2_column_counter_next_9_.cin_used="true";
2899 defparam un2_column_counter_next_9_.operation_mode="normal";
2900 defparam un2_column_counter_next_9_.output_mode="comb_only";
2901 defparam un2_column_counter_next_9_.lut_mask="6c6c";
2902 defparam un2_column_counter_next_9_.synch_mode="off";
2903 defparam un2_column_counter_next_9_.sum_lutc_input="cin";
2904 // @13:112
2905   stratix_lcell un2_column_counter_next_8_ (
2906         .combout(un2_column_counter_next_combout[8]),
2907         .clk(GND),
2908         .dataa(column_counter_sig_8),
2909         .datab(VCC),
2910         .datac(VCC),
2911         .datad(VCC),
2912         .aclr(GND),
2913         .sclr(GND),
2914         .sload(GND),
2915         .ena(VCC),
2916         .cin(un2_column_counter_next_cout[6]),
2917         .inverta(GND),
2918         .aload(GND),
2919         .regcascin(GND)
2920 );
2921 defparam un2_column_counter_next_8_.cin_used="true";
2922 defparam un2_column_counter_next_8_.operation_mode="normal";
2923 defparam un2_column_counter_next_8_.output_mode="comb_only";
2924 defparam un2_column_counter_next_8_.lut_mask="5a5a";
2925 defparam un2_column_counter_next_8_.synch_mode="off";
2926 defparam un2_column_counter_next_8_.sum_lutc_input="cin";
2927 // @13:112
2928   stratix_lcell un2_column_counter_next_7_ (
2929         .combout(un2_column_counter_next_combout[7]),
2930         .cout(un2_column_counter_next_cout[7]),
2931         .clk(GND),
2932         .dataa(column_counter_sig_6),
2933         .datab(column_counter_sig_7),
2934         .datac(VCC),
2935         .datad(VCC),
2936         .aclr(GND),
2937         .sclr(GND),
2938         .sload(GND),
2939         .ena(VCC),
2940         .cin(un2_column_counter_next_cout[5]),
2941         .inverta(GND),
2942         .aload(GND),
2943         .regcascin(GND)
2944 );
2945 defparam un2_column_counter_next_7_.cin_used="true";
2946 defparam un2_column_counter_next_7_.operation_mode="arithmetic";
2947 defparam un2_column_counter_next_7_.output_mode="comb_only";
2948 defparam un2_column_counter_next_7_.lut_mask="6c80";
2949 defparam un2_column_counter_next_7_.synch_mode="off";
2950 defparam un2_column_counter_next_7_.sum_lutc_input="cin";
2951 // @13:112
2952   stratix_lcell un2_column_counter_next_6_ (
2953         .combout(un2_column_counter_next_combout[6]),
2954         .cout(un2_column_counter_next_cout[6]),
2955         .clk(GND),
2956         .dataa(column_counter_sig_6),
2957         .datab(column_counter_sig_7),
2958         .datac(VCC),
2959         .datad(VCC),
2960         .aclr(GND),
2961         .sclr(GND),
2962         .sload(GND),
2963         .ena(VCC),
2964         .cin(un2_column_counter_next_cout[4]),
2965         .inverta(GND),
2966         .aload(GND),
2967         .regcascin(GND)
2968 );
2969 defparam un2_column_counter_next_6_.cin_used="true";
2970 defparam un2_column_counter_next_6_.operation_mode="arithmetic";
2971 defparam un2_column_counter_next_6_.output_mode="comb_only";
2972 defparam un2_column_counter_next_6_.lut_mask="5a80";
2973 defparam un2_column_counter_next_6_.synch_mode="off";
2974 defparam un2_column_counter_next_6_.sum_lutc_input="cin";
2975 // @13:112
2976   stratix_lcell un2_column_counter_next_5_ (
2977         .combout(un2_column_counter_next_combout[5]),
2978         .cout(un2_column_counter_next_cout[5]),
2979         .clk(GND),
2980         .dataa(column_counter_sig_4),
2981         .datab(column_counter_sig_5),
2982         .datac(VCC),
2983         .datad(VCC),
2984         .aclr(GND),
2985         .sclr(GND),
2986         .sload(GND),
2987         .ena(VCC),
2988         .cin(un2_column_counter_next_cout[3]),
2989         .inverta(GND),
2990         .aload(GND),
2991         .regcascin(GND)
2992 );
2993 defparam un2_column_counter_next_5_.cin_used="true";
2994 defparam un2_column_counter_next_5_.operation_mode="arithmetic";
2995 defparam un2_column_counter_next_5_.output_mode="comb_only";
2996 defparam un2_column_counter_next_5_.lut_mask="6c80";
2997 defparam un2_column_counter_next_5_.synch_mode="off";
2998 defparam un2_column_counter_next_5_.sum_lutc_input="cin";
2999 // @13:112
3000   stratix_lcell un2_column_counter_next_4_ (
3001         .combout(un2_column_counter_next_combout[4]),
3002         .cout(un2_column_counter_next_cout[4]),
3003         .clk(GND),
3004         .dataa(column_counter_sig_4),
3005         .datab(column_counter_sig_5),
3006         .datac(VCC),
3007         .datad(VCC),
3008         .aclr(GND),
3009         .sclr(GND),
3010         .sload(GND),
3011         .ena(VCC),
3012         .cin(un2_column_counter_next_cout[2]),
3013         .inverta(GND),
3014         .aload(GND),
3015         .regcascin(GND)
3016 );
3017 defparam un2_column_counter_next_4_.cin_used="true";
3018 defparam un2_column_counter_next_4_.operation_mode="arithmetic";
3019 defparam un2_column_counter_next_4_.output_mode="comb_only";
3020 defparam un2_column_counter_next_4_.lut_mask="5a80";
3021 defparam un2_column_counter_next_4_.synch_mode="off";
3022 defparam un2_column_counter_next_4_.sum_lutc_input="cin";
3023 // @13:112
3024   stratix_lcell un2_column_counter_next_3_ (
3025         .combout(un2_column_counter_next_combout[3]),
3026         .cout(un2_column_counter_next_cout[3]),
3027         .clk(GND),
3028         .dataa(column_counter_sig_2),
3029         .datab(column_counter_sig_3),
3030         .datac(VCC),
3031         .datad(VCC),
3032         .aclr(GND),
3033         .sclr(GND),
3034         .sload(GND),
3035         .ena(VCC),
3036         .cin(un2_column_counter_next_cout[1]),
3037         .inverta(GND),
3038         .aload(GND),
3039         .regcascin(GND)
3040 );
3041 defparam un2_column_counter_next_3_.cin_used="true";
3042 defparam un2_column_counter_next_3_.operation_mode="arithmetic";
3043 defparam un2_column_counter_next_3_.output_mode="comb_only";
3044 defparam un2_column_counter_next_3_.lut_mask="6c80";
3045 defparam un2_column_counter_next_3_.synch_mode="off";
3046 defparam un2_column_counter_next_3_.sum_lutc_input="cin";
3047 // @13:112
3048   stratix_lcell un2_column_counter_next_2_ (
3049         .combout(un2_column_counter_next_combout[2]),
3050         .cout(un2_column_counter_next_cout[2]),
3051         .clk(GND),
3052         .dataa(column_counter_sig_2),
3053         .datab(column_counter_sig_3),
3054         .datac(VCC),
3055         .datad(VCC),
3056         .aclr(GND),
3057         .sclr(GND),
3058         .sload(GND),
3059         .ena(VCC),
3060         .cin(un2_column_counter_next_cout[0]),
3061         .inverta(GND),
3062         .aload(GND),
3063         .regcascin(GND)
3064 );
3065 defparam un2_column_counter_next_2_.cin_used="true";
3066 defparam un2_column_counter_next_2_.operation_mode="arithmetic";
3067 defparam un2_column_counter_next_2_.output_mode="comb_only";
3068 defparam un2_column_counter_next_2_.lut_mask="5a80";
3069 defparam un2_column_counter_next_2_.synch_mode="off";
3070 defparam un2_column_counter_next_2_.sum_lutc_input="cin";
3071 // @13:112
3072   stratix_lcell un2_column_counter_next_1_ (
3073         .combout(un2_column_counter_next_combout[1]),
3074         .cout(un2_column_counter_next_cout[1]),
3075         .clk(GND),
3076         .dataa(column_counter_sig_0),
3077         .datab(column_counter_sig_1),
3078         .datac(VCC),
3079         .datad(VCC),
3080         .aclr(GND),
3081         .sclr(GND),
3082         .sload(GND),
3083         .ena(VCC),
3084         .inverta(GND),
3085         .aload(GND),
3086         .regcascin(GND)
3087 );
3088 defparam un2_column_counter_next_1_.operation_mode="arithmetic";
3089 defparam un2_column_counter_next_1_.output_mode="comb_only";
3090 defparam un2_column_counter_next_1_.lut_mask="6688";
3091 defparam un2_column_counter_next_1_.synch_mode="off";
3092 defparam un2_column_counter_next_1_.sum_lutc_input="datac";
3093 // @13:112
3094   stratix_lcell un2_column_counter_next_0_ (
3095         .cout(un2_column_counter_next_cout[0]),
3096         .clk(GND),
3097         .dataa(column_counter_sig_0),
3098         .datab(column_counter_sig_1),
3099         .datac(VCC),
3100         .datad(VCC),
3101         .aclr(GND),
3102         .sclr(GND),
3103         .sload(GND),
3104         .ena(VCC),
3105         .inverta(GND),
3106         .aload(GND),
3107         .regcascin(GND)
3108 );
3109 defparam un2_column_counter_next_0_.operation_mode="arithmetic";
3110 defparam un2_column_counter_next_0_.output_mode="comb_only";
3111 defparam un2_column_counter_next_0_.lut_mask="5588";
3112 defparam un2_column_counter_next_0_.synch_mode="off";
3113 defparam un2_column_counter_next_0_.sum_lutc_input="datac";
3114   assign  line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1;
3115   assign  column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1;
3116   assign  un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9;
3117   assign  G_16_i_i = ~ G_16_i;
3118   assign  un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9;
3119   assign  G_2_i_i = ~ G_2_i;
3120 endmodule /* vga_driver */
3121
3122 // VQM4.1+
3123 module vga_control (
3124   line_counter_sig_0,
3125   line_counter_sig_2,
3126   line_counter_sig_1,
3127   line_counter_sig_3,
3128   line_counter_sig_6,
3129   line_counter_sig_5,
3130   line_counter_sig_4,
3131   line_counter_sig_7,
3132   line_counter_sig_8,
3133   column_counter_sig_0,
3134   column_counter_sig_1,
3135   column_counter_sig_2,
3136   column_counter_sig_8,
3137   column_counter_sig_3,
3138   column_counter_sig_5,
3139   column_counter_sig_4,
3140   column_counter_sig_9,
3141   column_counter_sig_7,
3142   column_counter_sig_6,
3143   toggle_counter_sig_0,
3144   toggle_counter_sig_1,
3145   toggle_counter_sig_2,
3146   toggle_counter_sig_3,
3147   toggle_counter_sig_4,
3148   toggle_counter_sig_5,
3149   toggle_counter_sig_6,
3150   toggle_counter_sig_7,
3151   toggle_counter_sig_8,
3152   toggle_counter_sig_9,
3153   toggle_counter_sig_10,
3154   toggle_counter_sig_11,
3155   toggle_counter_sig_12,
3156   toggle_counter_sig_13,
3157   toggle_counter_sig_14,
3158   toggle_counter_sig_15,
3159   toggle_counter_sig_16,
3160   toggle_counter_sig_17,
3161   toggle_counter_sig_18,
3162   toggle_counter_sig_19,
3163   toggle_counter_sig_20,
3164   toggle_counter_sig_21,
3165   toggle_counter_sig_22,
3166   toggle_counter_sig_23,
3167   toggle_counter_sig_24,
3168   h_enable_sig,
3169   g,
3170   b,
3171   v_enable_sig,
3172   r,
3173   toggle_sig,
3174   un6_dly_counter_0_x,
3175   clk_pin_c
3176 )
3177 ;
3178 input line_counter_sig_0 ;
3179 input line_counter_sig_2 ;
3180 input line_counter_sig_1 ;
3181 input line_counter_sig_3 ;
3182 input line_counter_sig_6 ;
3183 input line_counter_sig_5 ;
3184 input line_counter_sig_4 ;
3185 input line_counter_sig_7 ;
3186 input line_counter_sig_8 ;
3187 input column_counter_sig_0 ;
3188 input column_counter_sig_1 ;
3189 input column_counter_sig_2 ;
3190 input column_counter_sig_8 ;
3191 input column_counter_sig_3 ;
3192 input column_counter_sig_5 ;
3193 input column_counter_sig_4 ;
3194 input column_counter_sig_9 ;
3195 input column_counter_sig_7 ;
3196 input column_counter_sig_6 ;
3197 output toggle_counter_sig_0 ;
3198 output toggle_counter_sig_1 ;
3199 output toggle_counter_sig_2 ;
3200 output toggle_counter_sig_3 ;
3201 output toggle_counter_sig_4 ;
3202 output toggle_counter_sig_5 ;
3203 output toggle_counter_sig_6 ;
3204 output toggle_counter_sig_7 ;
3205 output toggle_counter_sig_8 ;
3206 output toggle_counter_sig_9 ;
3207 output toggle_counter_sig_10 ;
3208 output toggle_counter_sig_11 ;
3209 output toggle_counter_sig_12 ;
3210 output toggle_counter_sig_13 ;
3211 output toggle_counter_sig_14 ;
3212 output toggle_counter_sig_15 ;
3213 output toggle_counter_sig_16 ;
3214 output toggle_counter_sig_17 ;
3215 output toggle_counter_sig_18 ;
3216 output toggle_counter_sig_19 ;
3217 output toggle_counter_sig_20 ;
3218 output toggle_counter_sig_21 ;
3219 output toggle_counter_sig_22 ;
3220 output toggle_counter_sig_23 ;
3221 output toggle_counter_sig_24 ;
3222 input h_enable_sig ;
3223 output g ;
3224 output b ;
3225 input v_enable_sig ;
3226 output r ;
3227 output toggle_sig ;
3228 input un6_dly_counter_0_x ;
3229 input clk_pin_c ;
3230 wire line_counter_sig_0 ;
3231 wire line_counter_sig_2 ;
3232 wire line_counter_sig_1 ;
3233 wire line_counter_sig_3 ;
3234 wire line_counter_sig_6 ;
3235 wire line_counter_sig_5 ;
3236 wire line_counter_sig_4 ;
3237 wire line_counter_sig_7 ;
3238 wire line_counter_sig_8 ;
3239 wire column_counter_sig_0 ;
3240 wire column_counter_sig_1 ;
3241 wire column_counter_sig_2 ;
3242 wire column_counter_sig_8 ;
3243 wire column_counter_sig_3 ;
3244 wire column_counter_sig_5 ;
3245 wire column_counter_sig_4 ;
3246 wire column_counter_sig_9 ;
3247 wire column_counter_sig_7 ;
3248 wire column_counter_sig_6 ;
3249 wire toggle_counter_sig_0 ;
3250 wire toggle_counter_sig_1 ;
3251 wire toggle_counter_sig_2 ;
3252 wire toggle_counter_sig_3 ;
3253 wire toggle_counter_sig_4 ;
3254 wire toggle_counter_sig_5 ;
3255 wire toggle_counter_sig_6 ;
3256 wire toggle_counter_sig_7 ;
3257 wire toggle_counter_sig_8 ;
3258 wire toggle_counter_sig_9 ;
3259 wire toggle_counter_sig_10 ;
3260 wire toggle_counter_sig_11 ;
3261 wire toggle_counter_sig_12 ;
3262 wire toggle_counter_sig_13 ;
3263 wire toggle_counter_sig_14 ;
3264 wire toggle_counter_sig_15 ;
3265 wire toggle_counter_sig_16 ;
3266 wire toggle_counter_sig_17 ;
3267 wire toggle_counter_sig_18 ;
3268 wire toggle_counter_sig_19 ;
3269 wire toggle_counter_sig_20 ;
3270 wire toggle_counter_sig_21 ;
3271 wire toggle_counter_sig_22 ;
3272 wire toggle_counter_sig_23 ;
3273 wire toggle_counter_sig_24 ;
3274 wire h_enable_sig ;
3275 wire g ;
3276 wire b ;
3277 wire v_enable_sig ;
3278 wire r ;
3279 wire toggle_sig ;
3280 wire un6_dly_counter_0_x ;
3281 wire clk_pin_c ;
3282 wire [18:1] toggle_counter_sig_cout;
3283 wire [0:0] un2_toggle_counter_next_cout;
3284 wire GND ;
3285 wire toggle_sig_0_0_0_g1 ;
3286 wire b_next_0_sqmuxa_7_4 ;
3287 wire b_next_0_sqmuxa_7_5 ;
3288 wire toggle_sig_0_0_0_g1_2 ;
3289 wire un1_toggle_counter_siglto18 ;
3290 wire un1_toggle_counter_siglto15 ;
3291 wire un5_v_enablelto5 ;
3292 wire b_next_0_sqmuxa_7_3 ;
3293 wire un13_v_enablelto6 ;
3294 wire b_next_0_sqmuxa_7_4_a ;
3295 wire un17_v_enablelto3 ;
3296 wire b_next_0_sqmuxa_7_2 ;
3297 wire un9_v_enablelto6 ;
3298 wire un1_toggle_counter_siglto12 ;
3299 wire un5_v_enablelt2 ;
3300 wire un1_toggle_counter_siglto9 ;
3301 wire un13_v_enablelto4_0 ;
3302 wire un9_v_enablelto4 ;
3303 wire un1_toggle_counter_siglt6 ;
3304 wire VCC ;
3305 wire toggle_sig_0_0_0_g1_i ;
3306   assign VCC = 1'b1;
3307 //@1:1
3308   assign GND = 1'b0;
3309 // @12:99
3310   stratix_lcell toggle_counter_sig_24_ (
3311         .regout(toggle_counter_sig_24),
3312         .clk(clk_pin_c),
3313         .dataa(VCC),
3314         .datab(VCC),
3315         .datac(VCC),
3316         .datad(GND),
3317         .aclr(un6_dly_counter_0_x),
3318         .sclr(GND),
3319         .sload(GND),
3320         .ena(VCC),
3321         .inverta(GND),
3322         .aload(GND),
3323         .regcascin(GND)
3324 );
3325 defparam toggle_counter_sig_24_.operation_mode="normal";
3326 defparam toggle_counter_sig_24_.output_mode="reg_only";
3327 defparam toggle_counter_sig_24_.lut_mask="ff00";
3328 defparam toggle_counter_sig_24_.synch_mode="off";
3329 defparam toggle_counter_sig_24_.sum_lutc_input="datac";
3330 // @12:99
3331   stratix_lcell toggle_counter_sig_23_ (
3332         .regout(toggle_counter_sig_23),
3333         .clk(clk_pin_c),
3334         .dataa(VCC),
3335         .datab(VCC),
3336         .datac(VCC),
3337         .datad(GND),
3338         .aclr(un6_dly_counter_0_x),
3339         .sclr(GND),
3340         .sload(GND),
3341         .ena(VCC),
3342         .inverta(GND),
3343         .aload(GND),
3344         .regcascin(GND)
3345 );
3346 defparam toggle_counter_sig_23_.operation_mode="normal";
3347 defparam toggle_counter_sig_23_.output_mode="reg_only";
3348 defparam toggle_counter_sig_23_.lut_mask="ff00";
3349 defparam toggle_counter_sig_23_.synch_mode="off";
3350 defparam toggle_counter_sig_23_.sum_lutc_input="datac";
3351 // @12:99
3352   stratix_lcell toggle_counter_sig_22_ (
3353         .regout(toggle_counter_sig_22),
3354         .clk(clk_pin_c),
3355         .dataa(VCC),
3356         .datab(VCC),
3357         .datac(VCC),
3358         .datad(GND),
3359         .aclr(un6_dly_counter_0_x),
3360         .sclr(GND),
3361         .sload(GND),
3362         .ena(VCC),
3363         .inverta(GND),
3364         .aload(GND),
3365         .regcascin(GND)
3366 );
3367 defparam toggle_counter_sig_22_.operation_mode="normal";
3368 defparam toggle_counter_sig_22_.output_mode="reg_only";
3369 defparam toggle_counter_sig_22_.lut_mask="ff00";
3370 defparam toggle_counter_sig_22_.synch_mode="off";
3371 defparam toggle_counter_sig_22_.sum_lutc_input="datac";
3372 // @12:99
3373   stratix_lcell toggle_counter_sig_21_ (
3374         .regout(toggle_counter_sig_21),
3375         .clk(clk_pin_c),
3376         .dataa(VCC),
3377         .datab(VCC),
3378         .datac(VCC),
3379         .datad(GND),
3380         .aclr(un6_dly_counter_0_x),
3381         .sclr(GND),
3382         .sload(GND),
3383         .ena(VCC),
3384         .inverta(GND),
3385         .aload(GND),
3386         .regcascin(GND)
3387 );
3388 defparam toggle_counter_sig_21_.operation_mode="normal";
3389 defparam toggle_counter_sig_21_.output_mode="reg_only";
3390 defparam toggle_counter_sig_21_.lut_mask="ff00";
3391 defparam toggle_counter_sig_21_.synch_mode="off";
3392 defparam toggle_counter_sig_21_.sum_lutc_input="datac";
3393 // @12:99
3394   stratix_lcell toggle_counter_sig_20_ (
3395         .regout(toggle_counter_sig_20),
3396         .clk(clk_pin_c),
3397         .dataa(toggle_counter_sig_20),
3398         .datab(VCC),
3399         .datac(VCC),
3400         .datad(VCC),
3401         .aclr(un6_dly_counter_0_x),
3402         .sclr(toggle_sig_0_0_0_g1_i),
3403         .sload(GND),
3404         .ena(VCC),
3405         .cin(toggle_counter_sig_cout[18]),
3406         .inverta(GND),
3407         .aload(GND),
3408         .regcascin(GND)
3409 );
3410 defparam toggle_counter_sig_20_.cin_used="true";
3411 defparam toggle_counter_sig_20_.operation_mode="normal";
3412 defparam toggle_counter_sig_20_.output_mode="reg_only";
3413 defparam toggle_counter_sig_20_.lut_mask="5a5a";
3414 defparam toggle_counter_sig_20_.synch_mode="on";
3415 defparam toggle_counter_sig_20_.sum_lutc_input="cin";
3416 // @12:99
3417   stratix_lcell toggle_counter_sig_19_ (
3418         .regout(toggle_counter_sig_19),
3419         .clk(clk_pin_c),
3420         .dataa(toggle_counter_sig_18),
3421         .datab(toggle_counter_sig_19),
3422         .datac(VCC),
3423         .datad(VCC),
3424         .aclr(un6_dly_counter_0_x),
3425         .sclr(toggle_sig_0_0_0_g1_i),
3426         .sload(GND),
3427         .ena(VCC),
3428         .cin(toggle_counter_sig_cout[17]),
3429         .inverta(GND),
3430         .aload(GND),
3431         .regcascin(GND)
3432 );
3433 defparam toggle_counter_sig_19_.cin_used="true";
3434 defparam toggle_counter_sig_19_.operation_mode="normal";
3435 defparam toggle_counter_sig_19_.output_mode="reg_only";
3436 defparam toggle_counter_sig_19_.lut_mask="6c6c";
3437 defparam toggle_counter_sig_19_.synch_mode="on";
3438 defparam toggle_counter_sig_19_.sum_lutc_input="cin";
3439 // @12:99
3440   stratix_lcell toggle_counter_sig_18_ (
3441         .regout(toggle_counter_sig_18),
3442         .cout(toggle_counter_sig_cout[18]),
3443         .clk(clk_pin_c),
3444         .dataa(toggle_counter_sig_18),
3445         .datab(toggle_counter_sig_19),
3446         .datac(VCC),
3447         .datad(VCC),
3448         .aclr(un6_dly_counter_0_x),
3449         .sclr(toggle_sig_0_0_0_g1_i),
3450         .sload(GND),
3451         .ena(VCC),
3452         .cin(toggle_counter_sig_cout[16]),
3453         .inverta(GND),
3454         .aload(GND),
3455         .regcascin(GND)
3456 );
3457 defparam toggle_counter_sig_18_.cin_used="true";
3458 defparam toggle_counter_sig_18_.operation_mode="arithmetic";
3459 defparam toggle_counter_sig_18_.output_mode="reg_only";
3460 defparam toggle_counter_sig_18_.lut_mask="5a80";
3461 defparam toggle_counter_sig_18_.synch_mode="on";
3462 defparam toggle_counter_sig_18_.sum_lutc_input="cin";
3463 // @12:99
3464   stratix_lcell toggle_counter_sig_17_ (
3465         .regout(toggle_counter_sig_17),
3466         .cout(toggle_counter_sig_cout[17]),
3467         .clk(clk_pin_c),
3468         .dataa(toggle_counter_sig_16),
3469         .datab(toggle_counter_sig_17),
3470         .datac(VCC),
3471         .datad(VCC),
3472         .aclr(un6_dly_counter_0_x),
3473         .sclr(toggle_sig_0_0_0_g1_i),
3474         .sload(GND),
3475         .ena(VCC),
3476         .cin(toggle_counter_sig_cout[15]),
3477         .inverta(GND),
3478         .aload(GND),
3479         .regcascin(GND)
3480 );
3481 defparam toggle_counter_sig_17_.cin_used="true";
3482 defparam toggle_counter_sig_17_.operation_mode="arithmetic";
3483 defparam toggle_counter_sig_17_.output_mode="reg_only";
3484 defparam toggle_counter_sig_17_.lut_mask="6c80";
3485 defparam toggle_counter_sig_17_.synch_mode="on";
3486 defparam toggle_counter_sig_17_.sum_lutc_input="cin";
3487 // @12:99
3488   stratix_lcell toggle_counter_sig_16_ (
3489         .regout(toggle_counter_sig_16),
3490         .cout(toggle_counter_sig_cout[16]),
3491         .clk(clk_pin_c),
3492         .dataa(toggle_counter_sig_16),
3493         .datab(toggle_counter_sig_17),
3494         .datac(VCC),
3495         .datad(VCC),
3496         .aclr(un6_dly_counter_0_x),
3497         .sclr(toggle_sig_0_0_0_g1_i),
3498         .sload(GND),
3499         .ena(VCC),
3500         .cin(toggle_counter_sig_cout[14]),
3501         .inverta(GND),
3502         .aload(GND),
3503         .regcascin(GND)
3504 );
3505 defparam toggle_counter_sig_16_.cin_used="true";
3506 defparam toggle_counter_sig_16_.operation_mode="arithmetic";
3507 defparam toggle_counter_sig_16_.output_mode="reg_only";
3508 defparam toggle_counter_sig_16_.lut_mask="5a80";
3509 defparam toggle_counter_sig_16_.synch_mode="on";
3510 defparam toggle_counter_sig_16_.sum_lutc_input="cin";
3511 // @12:99
3512   stratix_lcell toggle_counter_sig_15_ (
3513         .regout(toggle_counter_sig_15),
3514         .cout(toggle_counter_sig_cout[15]),
3515         .clk(clk_pin_c),
3516         .dataa(toggle_counter_sig_14),
3517         .datab(toggle_counter_sig_15),
3518         .datac(VCC),
3519         .datad(VCC),
3520         .aclr(un6_dly_counter_0_x),
3521         .sclr(toggle_sig_0_0_0_g1_i),
3522         .sload(GND),
3523         .ena(VCC),
3524         .cin(toggle_counter_sig_cout[13]),
3525         .inverta(GND),
3526         .aload(GND),
3527         .regcascin(GND)
3528 );
3529 defparam toggle_counter_sig_15_.cin_used="true";
3530 defparam toggle_counter_sig_15_.operation_mode="arithmetic";
3531 defparam toggle_counter_sig_15_.output_mode="reg_only";
3532 defparam toggle_counter_sig_15_.lut_mask="6c80";
3533 defparam toggle_counter_sig_15_.synch_mode="on";
3534 defparam toggle_counter_sig_15_.sum_lutc_input="cin";
3535 // @12:99
3536   stratix_lcell toggle_counter_sig_14_ (
3537         .regout(toggle_counter_sig_14),
3538         .cout(toggle_counter_sig_cout[14]),
3539         .clk(clk_pin_c),
3540         .dataa(toggle_counter_sig_14),
3541         .datab(toggle_counter_sig_15),
3542         .datac(VCC),
3543         .datad(VCC),
3544         .aclr(un6_dly_counter_0_x),
3545         .sclr(toggle_sig_0_0_0_g1_i),
3546         .sload(GND),
3547         .ena(VCC),
3548         .cin(toggle_counter_sig_cout[12]),
3549         .inverta(GND),
3550         .aload(GND),
3551         .regcascin(GND)
3552 );
3553 defparam toggle_counter_sig_14_.cin_used="true";
3554 defparam toggle_counter_sig_14_.operation_mode="arithmetic";
3555 defparam toggle_counter_sig_14_.output_mode="reg_only";
3556 defparam toggle_counter_sig_14_.lut_mask="5a80";
3557 defparam toggle_counter_sig_14_.synch_mode="on";
3558 defparam toggle_counter_sig_14_.sum_lutc_input="cin";
3559 // @12:99
3560   stratix_lcell toggle_counter_sig_13_ (
3561         .regout(toggle_counter_sig_13),
3562         .cout(toggle_counter_sig_cout[13]),
3563         .clk(clk_pin_c),
3564         .dataa(toggle_counter_sig_12),
3565         .datab(toggle_counter_sig_13),
3566         .datac(VCC),
3567         .datad(VCC),
3568         .aclr(un6_dly_counter_0_x),
3569         .sclr(toggle_sig_0_0_0_g1_i),
3570         .sload(GND),
3571         .ena(VCC),
3572         .cin(toggle_counter_sig_cout[11]),
3573         .inverta(GND),
3574         .aload(GND),
3575         .regcascin(GND)
3576 );
3577 defparam toggle_counter_sig_13_.cin_used="true";
3578 defparam toggle_counter_sig_13_.operation_mode="arithmetic";
3579 defparam toggle_counter_sig_13_.output_mode="reg_only";
3580 defparam toggle_counter_sig_13_.lut_mask="6c80";
3581 defparam toggle_counter_sig_13_.synch_mode="on";
3582 defparam toggle_counter_sig_13_.sum_lutc_input="cin";
3583 // @12:99
3584   stratix_lcell toggle_counter_sig_12_ (
3585         .regout(toggle_counter_sig_12),
3586         .cout(toggle_counter_sig_cout[12]),
3587         .clk(clk_pin_c),
3588         .dataa(toggle_counter_sig_12),
3589         .datab(toggle_counter_sig_13),
3590         .datac(VCC),
3591         .datad(VCC),
3592         .aclr(un6_dly_counter_0_x),
3593         .sclr(toggle_sig_0_0_0_g1_i),
3594         .sload(GND),
3595         .ena(VCC),
3596         .cin(toggle_counter_sig_cout[10]),
3597         .inverta(GND),
3598         .aload(GND),
3599         .regcascin(GND)
3600 );
3601 defparam toggle_counter_sig_12_.cin_used="true";
3602 defparam toggle_counter_sig_12_.operation_mode="arithmetic";
3603 defparam toggle_counter_sig_12_.output_mode="reg_only";
3604 defparam toggle_counter_sig_12_.lut_mask="5a80";
3605 defparam toggle_counter_sig_12_.synch_mode="on";
3606 defparam toggle_counter_sig_12_.sum_lutc_input="cin";
3607 // @12:99
3608   stratix_lcell toggle_counter_sig_11_ (
3609         .regout(toggle_counter_sig_11),
3610         .cout(toggle_counter_sig_cout[11]),
3611         .clk(clk_pin_c),
3612         .dataa(toggle_counter_sig_10),
3613         .datab(toggle_counter_sig_11),
3614         .datac(VCC),
3615         .datad(VCC),
3616         .aclr(un6_dly_counter_0_x),
3617         .sclr(toggle_sig_0_0_0_g1_i),
3618         .sload(GND),
3619         .ena(VCC),
3620         .cin(toggle_counter_sig_cout[9]),
3621         .inverta(GND),
3622         .aload(GND),
3623         .regcascin(GND)
3624 );
3625 defparam toggle_counter_sig_11_.cin_used="true";
3626 defparam toggle_counter_sig_11_.operation_mode="arithmetic";
3627 defparam toggle_counter_sig_11_.output_mode="reg_only";
3628 defparam toggle_counter_sig_11_.lut_mask="6c80";
3629 defparam toggle_counter_sig_11_.synch_mode="on";
3630 defparam toggle_counter_sig_11_.sum_lutc_input="cin";
3631 // @12:99
3632   stratix_lcell toggle_counter_sig_10_ (
3633         .regout(toggle_counter_sig_10),
3634         .cout(toggle_counter_sig_cout[10]),
3635         .clk(clk_pin_c),
3636         .dataa(toggle_counter_sig_10),
3637         .datab(toggle_counter_sig_11),
3638         .datac(VCC),
3639         .datad(VCC),
3640         .aclr(un6_dly_counter_0_x),
3641         .sclr(toggle_sig_0_0_0_g1_i),
3642         .sload(GND),
3643         .ena(VCC),
3644         .cin(toggle_counter_sig_cout[8]),
3645         .inverta(GND),
3646         .aload(GND),
3647         .regcascin(GND)
3648 );
3649 defparam toggle_counter_sig_10_.cin_used="true";
3650 defparam toggle_counter_sig_10_.operation_mode="arithmetic";
3651 defparam toggle_counter_sig_10_.output_mode="reg_only";
3652 defparam toggle_counter_sig_10_.lut_mask="5a80";
3653 defparam toggle_counter_sig_10_.synch_mode="on";
3654 defparam toggle_counter_sig_10_.sum_lutc_input="cin";
3655 // @12:99
3656   stratix_lcell toggle_counter_sig_9_ (
3657         .regout(toggle_counter_sig_9),
3658         .cout(toggle_counter_sig_cout[9]),
3659         .clk(clk_pin_c),
3660         .dataa(toggle_counter_sig_8),
3661         .datab(toggle_counter_sig_9),
3662         .datac(VCC),
3663         .datad(VCC),
3664         .aclr(un6_dly_counter_0_x),
3665         .sclr(toggle_sig_0_0_0_g1_i),
3666         .sload(GND),
3667         .ena(VCC),
3668         .cin(toggle_counter_sig_cout[7]),
3669         .inverta(GND),
3670         .aload(GND),
3671         .regcascin(GND)
3672 );
3673 defparam toggle_counter_sig_9_.cin_used="true";
3674 defparam toggle_counter_sig_9_.operation_mode="arithmetic";
3675 defparam toggle_counter_sig_9_.output_mode="reg_only";
3676 defparam toggle_counter_sig_9_.lut_mask="6c80";
3677 defparam toggle_counter_sig_9_.synch_mode="on";
3678 defparam toggle_counter_sig_9_.sum_lutc_input="cin";
3679 // @12:99
3680   stratix_lcell toggle_counter_sig_8_ (
3681         .regout(toggle_counter_sig_8),
3682         .cout(toggle_counter_sig_cout[8]),
3683         .clk(clk_pin_c),
3684         .dataa(toggle_counter_sig_8),
3685         .datab(toggle_counter_sig_9),
3686         .datac(VCC),
3687         .datad(VCC),
3688         .aclr(un6_dly_counter_0_x),
3689         .sclr(toggle_sig_0_0_0_g1_i),
3690         .sload(GND),
3691         .ena(VCC),
3692         .cin(toggle_counter_sig_cout[6]),
3693         .inverta(GND),
3694         .aload(GND),
3695         .regcascin(GND)
3696 );
3697 defparam toggle_counter_sig_8_.cin_used="true";
3698 defparam toggle_counter_sig_8_.operation_mode="arithmetic";
3699 defparam toggle_counter_sig_8_.output_mode="reg_only";
3700 defparam toggle_counter_sig_8_.lut_mask="5a80";
3701 defparam toggle_counter_sig_8_.synch_mode="on";
3702 defparam toggle_counter_sig_8_.sum_lutc_input="cin";
3703 // @12:99
3704   stratix_lcell toggle_counter_sig_7_ (
3705         .regout(toggle_counter_sig_7),
3706         .cout(toggle_counter_sig_cout[7]),
3707         .clk(clk_pin_c),
3708         .dataa(toggle_counter_sig_6),
3709         .datab(toggle_counter_sig_7),
3710         .datac(VCC),
3711         .datad(VCC),
3712         .aclr(un6_dly_counter_0_x),
3713         .sclr(toggle_sig_0_0_0_g1_i),
3714         .sload(GND),
3715         .ena(VCC),
3716         .cin(toggle_counter_sig_cout[5]),
3717         .inverta(GND),
3718         .aload(GND),
3719         .regcascin(GND)
3720 );
3721 defparam toggle_counter_sig_7_.cin_used="true";
3722 defparam toggle_counter_sig_7_.operation_mode="arithmetic";
3723 defparam toggle_counter_sig_7_.output_mode="reg_only";
3724 defparam toggle_counter_sig_7_.lut_mask="6c80";
3725 defparam toggle_counter_sig_7_.synch_mode="on";
3726 defparam toggle_counter_sig_7_.sum_lutc_input="cin";
3727 // @12:99
3728   stratix_lcell toggle_counter_sig_6_ (
3729         .regout(toggle_counter_sig_6),
3730         .cout(toggle_counter_sig_cout[6]),
3731         .clk(clk_pin_c),
3732         .dataa(toggle_counter_sig_6),
3733         .datab(toggle_counter_sig_7),
3734         .datac(VCC),
3735         .datad(VCC),
3736         .aclr(un6_dly_counter_0_x),
3737         .sclr(toggle_sig_0_0_0_g1_i),
3738         .sload(GND),
3739         .ena(VCC),
3740         .cin(toggle_counter_sig_cout[4]),
3741         .inverta(GND),
3742         .aload(GND),
3743         .regcascin(GND)
3744 );
3745 defparam toggle_counter_sig_6_.cin_used="true";
3746 defparam toggle_counter_sig_6_.operation_mode="arithmetic";
3747 defparam toggle_counter_sig_6_.output_mode="reg_only";
3748 defparam toggle_counter_sig_6_.lut_mask="5a80";
3749 defparam toggle_counter_sig_6_.synch_mode="on";
3750 defparam toggle_counter_sig_6_.sum_lutc_input="cin";
3751 // @12:99
3752   stratix_lcell toggle_counter_sig_5_ (
3753         .regout(toggle_counter_sig_5),
3754         .cout(toggle_counter_sig_cout[5]),
3755         .clk(clk_pin_c),
3756         .dataa(toggle_counter_sig_4),
3757         .datab(toggle_counter_sig_5),
3758         .datac(VCC),
3759         .datad(VCC),
3760         .aclr(un6_dly_counter_0_x),
3761         .sclr(toggle_sig_0_0_0_g1_i),
3762         .sload(GND),
3763         .ena(VCC),
3764         .cin(toggle_counter_sig_cout[3]),
3765         .inverta(GND),
3766         .aload(GND),
3767         .regcascin(GND)
3768 );
3769 defparam toggle_counter_sig_5_.cin_used="true";
3770 defparam toggle_counter_sig_5_.operation_mode="arithmetic";
3771 defparam toggle_counter_sig_5_.output_mode="reg_only";
3772 defparam toggle_counter_sig_5_.lut_mask="6c80";
3773 defparam toggle_counter_sig_5_.synch_mode="on";
3774 defparam toggle_counter_sig_5_.sum_lutc_input="cin";
3775 // @12:99
3776   stratix_lcell toggle_counter_sig_4_ (
3777         .regout(toggle_counter_sig_4),
3778         .cout(toggle_counter_sig_cout[4]),
3779         .clk(clk_pin_c),
3780         .dataa(toggle_counter_sig_4),
3781         .datab(toggle_counter_sig_5),
3782         .datac(VCC),
3783         .datad(VCC),
3784         .aclr(un6_dly_counter_0_x),
3785         .sclr(toggle_sig_0_0_0_g1_i),
3786         .sload(GND),
3787         .ena(VCC),
3788         .cin(toggle_counter_sig_cout[2]),
3789         .inverta(GND),
3790         .aload(GND),
3791         .regcascin(GND)
3792 );
3793 defparam toggle_counter_sig_4_.cin_used="true";
3794 defparam toggle_counter_sig_4_.operation_mode="arithmetic";
3795 defparam toggle_counter_sig_4_.output_mode="reg_only";
3796 defparam toggle_counter_sig_4_.lut_mask="5a80";
3797 defparam toggle_counter_sig_4_.synch_mode="on";
3798 defparam toggle_counter_sig_4_.sum_lutc_input="cin";
3799 // @12:99
3800   stratix_lcell toggle_counter_sig_3_ (
3801         .regout(toggle_counter_sig_3),
3802         .cout(toggle_counter_sig_cout[3]),
3803         .clk(clk_pin_c),
3804         .dataa(toggle_counter_sig_2),
3805         .datab(toggle_counter_sig_3),
3806         .datac(VCC),
3807         .datad(VCC),
3808         .aclr(un6_dly_counter_0_x),
3809         .sclr(toggle_sig_0_0_0_g1_i),
3810         .sload(GND),
3811         .ena(VCC),
3812         .cin(toggle_counter_sig_cout[1]),
3813         .inverta(GND),
3814         .aload(GND),
3815         .regcascin(GND)
3816 );
3817 defparam toggle_counter_sig_3_.cin_used="true";
3818 defparam toggle_counter_sig_3_.operation_mode="arithmetic";
3819 defparam toggle_counter_sig_3_.output_mode="reg_only";
3820 defparam toggle_counter_sig_3_.lut_mask="6c80";
3821 defparam toggle_counter_sig_3_.synch_mode="on";
3822 defparam toggle_counter_sig_3_.sum_lutc_input="cin";
3823 // @12:99
3824   stratix_lcell toggle_counter_sig_2_ (
3825         .regout(toggle_counter_sig_2),
3826         .cout(toggle_counter_sig_cout[2]),
3827         .clk(clk_pin_c),
3828         .dataa(toggle_counter_sig_2),
3829         .datab(toggle_counter_sig_3),
3830         .datac(VCC),
3831         .datad(VCC),
3832         .aclr(un6_dly_counter_0_x),
3833         .sclr(toggle_sig_0_0_0_g1_i),
3834         .sload(GND),
3835         .ena(VCC),
3836         .cin(un2_toggle_counter_next_cout[0]),
3837         .inverta(GND),
3838         .aload(GND),
3839         .regcascin(GND)
3840 );
3841 defparam toggle_counter_sig_2_.cin_used="true";
3842 defparam toggle_counter_sig_2_.operation_mode="arithmetic";
3843 defparam toggle_counter_sig_2_.output_mode="reg_only";
3844 defparam toggle_counter_sig_2_.lut_mask="5a80";
3845 defparam toggle_counter_sig_2_.synch_mode="on";
3846 defparam toggle_counter_sig_2_.sum_lutc_input="cin";
3847 // @12:99
3848   stratix_lcell toggle_counter_sig_1_ (
3849         .regout(toggle_counter_sig_1),
3850         .cout(toggle_counter_sig_cout[1]),
3851         .clk(clk_pin_c),
3852         .dataa(toggle_counter_sig_0),
3853         .datab(toggle_counter_sig_1),
3854         .datac(VCC),
3855         .datad(VCC),
3856         .aclr(un6_dly_counter_0_x),
3857         .sclr(toggle_sig_0_0_0_g1_i),
3858         .sload(GND),
3859         .ena(VCC),
3860         .inverta(GND),
3861         .aload(GND),
3862         .regcascin(GND)
3863 );
3864 defparam toggle_counter_sig_1_.operation_mode="arithmetic";
3865 defparam toggle_counter_sig_1_.output_mode="reg_only";
3866 defparam toggle_counter_sig_1_.lut_mask="6688";
3867 defparam toggle_counter_sig_1_.synch_mode="on";
3868 defparam toggle_counter_sig_1_.sum_lutc_input="datac";
3869 // @12:99
3870   stratix_lcell toggle_counter_sig_0_ (
3871         .regout(toggle_counter_sig_0),
3872         .clk(clk_pin_c),
3873         .dataa(toggle_counter_sig_0),
3874         .datab(VCC),
3875         .datac(VCC),
3876         .datad(VCC),
3877         .aclr(un6_dly_counter_0_x),
3878         .sclr(toggle_sig_0_0_0_g1_i),
3879         .sload(GND),
3880         .ena(VCC),
3881         .inverta(GND),
3882         .aload(GND),
3883         .regcascin(GND)
3884 );
3885 defparam toggle_counter_sig_0_.operation_mode="normal";
3886 defparam toggle_counter_sig_0_.output_mode="reg_only";
3887 defparam toggle_counter_sig_0_.lut_mask="5555";
3888 defparam toggle_counter_sig_0_.synch_mode="on";
3889 defparam toggle_counter_sig_0_.sum_lutc_input="datac";
3890 // @12:99
3891   stratix_lcell toggle_sig_Z (
3892         .regout(toggle_sig),
3893         .clk(clk_pin_c),
3894         .dataa(toggle_sig),
3895         .datab(toggle_sig_0_0_0_g1),
3896         .datac(VCC),
3897         .datad(VCC),
3898         .aclr(un6_dly_counter_0_x),
3899         .sclr(GND),
3900         .sload(GND),
3901         .ena(VCC),
3902         .inverta(GND),
3903         .aload(GND),
3904         .regcascin(GND)
3905 );
3906 defparam toggle_sig_Z.operation_mode="normal";
3907 defparam toggle_sig_Z.output_mode="reg_only";
3908 defparam toggle_sig_Z.lut_mask="9999";
3909 defparam toggle_sig_Z.synch_mode="off";
3910 defparam toggle_sig_Z.sum_lutc_input="datac";
3911 // @12:60
3912   stratix_lcell r_Z (
3913         .regout(r),
3914         .clk(clk_pin_c),
3915         .dataa(toggle_sig),
3916         .datab(v_enable_sig),
3917         .datac(b_next_0_sqmuxa_7_4),
3918         .datad(b_next_0_sqmuxa_7_5),
3919         .aclr(un6_dly_counter_0_x),
3920         .sclr(GND),
3921         .sload(GND),
3922         .ena(VCC),
3923         .inverta(GND),
3924         .aload(GND),
3925         .regcascin(GND)
3926 );
3927 defparam r_Z.operation_mode="normal";
3928 defparam r_Z.output_mode="reg_only";
3929 defparam r_Z.lut_mask="8000";
3930 defparam r_Z.synch_mode="off";
3931 defparam r_Z.sum_lutc_input="datac";
3932 // @12:60
3933   stratix_lcell b_Z (
3934         .regout(b),
3935         .clk(clk_pin_c),
3936         .dataa(toggle_sig),
3937         .datab(v_enable_sig),
3938         .datac(b_next_0_sqmuxa_7_4),
3939         .datad(b_next_0_sqmuxa_7_5),
3940         .aclr(un6_dly_counter_0_x),
3941         .sclr(GND),
3942         .sload(GND),
3943         .ena(VCC),
3944         .inverta(GND),
3945         .aload(GND),
3946         .regcascin(GND)
3947 );
3948 defparam b_Z.operation_mode="normal";
3949 defparam b_Z.output_mode="reg_only";
3950 defparam b_Z.lut_mask="4000";
3951 defparam b_Z.synch_mode="off";
3952 defparam b_Z.sum_lutc_input="datac";
3953 // @12:60
3954   stratix_lcell g_Z (
3955         .regout(g),
3956         .clk(clk_pin_c),
3957         .dataa(VCC),
3958         .datab(VCC),
3959         .datac(VCC),
3960         .datad(GND),
3961         .aclr(un6_dly_counter_0_x),
3962         .sclr(GND),
3963         .sload(GND),
3964         .ena(VCC),
3965         .inverta(GND),
3966         .aload(GND),
3967         .regcascin(GND)
3968 );
3969 defparam g_Z.operation_mode="normal";
3970 defparam g_Z.output_mode="reg_only";
3971 defparam g_Z.lut_mask="ff00";
3972 defparam g_Z.synch_mode="off";
3973 defparam g_Z.sum_lutc_input="datac";
3974   stratix_lcell toggle_sig_0_0_0_g1_cZ (
3975         .combout(toggle_sig_0_0_0_g1),
3976         .clk(GND),
3977         .dataa(toggle_counter_sig_19),
3978         .datab(toggle_counter_sig_20),
3979         .datac(toggle_sig_0_0_0_g1_2),
3980         .datad(un1_toggle_counter_siglto18),
3981         .aclr(GND),
3982         .sclr(GND),
3983         .sload(GND),
3984         .ena(VCC),
3985         .inverta(GND),
3986         .aload(GND),
3987         .regcascin(GND)
3988 );
3989 defparam toggle_sig_0_0_0_g1_cZ.operation_mode="normal";
3990 defparam toggle_sig_0_0_0_g1_cZ.output_mode="comb_only";
3991 defparam toggle_sig_0_0_0_g1_cZ.lut_mask="0703";
3992 defparam toggle_sig_0_0_0_g1_cZ.synch_mode="off";
3993 defparam toggle_sig_0_0_0_g1_cZ.sum_lutc_input="datac";
3994 // @12:111
3995   stratix_lcell BLINKER_next_un1_toggle_counter_siglto18 (
3996         .combout(un1_toggle_counter_siglto18),
3997         .clk(GND),
3998         .dataa(toggle_counter_sig_17),
3999         .datab(toggle_counter_sig_18),
4000         .datac(toggle_counter_sig_16),
4001         .datad(un1_toggle_counter_siglto15),
4002         .aclr(GND),
4003         .sclr(GND),
4004         .sload(GND),
4005         .ena(VCC),
4006         .inverta(GND),
4007         .aload(GND),
4008         .regcascin(GND)
4009 );
4010 defparam BLINKER_next_un1_toggle_counter_siglto18.operation_mode="normal";
4011 defparam BLINKER_next_un1_toggle_counter_siglto18.output_mode="comb_only";
4012 defparam BLINKER_next_un1_toggle_counter_siglto18.lut_mask="7f77";
4013 defparam BLINKER_next_un1_toggle_counter_siglto18.synch_mode="off";
4014 defparam BLINKER_next_un1_toggle_counter_siglto18.sum_lutc_input="datac";
4015 // @12:75
4016   stratix_lcell b_next_0_sqmuxa_7_5_cZ (
4017         .combout(b_next_0_sqmuxa_7_5),
4018         .clk(GND),
4019         .dataa(column_counter_sig_6),
4020         .datab(column_counter_sig_7),
4021         .datac(un5_v_enablelto5),
4022         .datad(b_next_0_sqmuxa_7_3),
4023         .aclr(GND),
4024         .sclr(GND),
4025         .sload(GND),
4026         .ena(VCC),
4027         .inverta(GND),
4028         .aload(GND),
4029         .regcascin(GND)
4030 );
4031 defparam b_next_0_sqmuxa_7_5_cZ.operation_mode="normal";
4032 defparam b_next_0_sqmuxa_7_5_cZ.output_mode="comb_only";
4033 defparam b_next_0_sqmuxa_7_5_cZ.lut_mask="7f00";
4034 defparam b_next_0_sqmuxa_7_5_cZ.synch_mode="off";
4035 defparam b_next_0_sqmuxa_7_5_cZ.sum_lutc_input="datac";
4036 // @12:75
4037   stratix_lcell b_next_0_sqmuxa_7_4_cZ (
4038         .combout(b_next_0_sqmuxa_7_4),
4039         .clk(GND),
4040         .dataa(line_counter_sig_8),
4041         .datab(line_counter_sig_7),
4042         .datac(un13_v_enablelto6),
4043         .datad(b_next_0_sqmuxa_7_4_a),
4044         .aclr(GND),
4045         .sclr(GND),
4046         .sload(GND),
4047         .ena(VCC),
4048         .inverta(GND),
4049         .aload(GND),
4050         .regcascin(GND)
4051 );
4052 defparam b_next_0_sqmuxa_7_4_cZ.operation_mode="normal";
4053 defparam b_next_0_sqmuxa_7_4_cZ.output_mode="comb_only";
4054 defparam b_next_0_sqmuxa_7_4_cZ.lut_mask="ef23";
4055 defparam b_next_0_sqmuxa_7_4_cZ.synch_mode="off";
4056 defparam b_next_0_sqmuxa_7_4_cZ.sum_lutc_input="datac";
4057 // @12:75
4058   stratix_lcell b_next_0_sqmuxa_7_4_a_cZ (
4059         .combout(b_next_0_sqmuxa_7_4_a),
4060         .clk(GND),
4061         .dataa(line_counter_sig_4),
4062         .datab(line_counter_sig_5),
4063         .datac(line_counter_sig_6),
4064         .datad(un17_v_enablelto3),
4065         .aclr(GND),
4066         .sclr(GND),
4067         .sload(GND),
4068         .ena(VCC),
4069         .inverta(GND),
4070         .aload(GND),
4071         .regcascin(GND)
4072 );
4073 defparam b_next_0_sqmuxa_7_4_a_cZ.operation_mode="normal";
4074 defparam b_next_0_sqmuxa_7_4_a_cZ.output_mode="comb_only";
4075 defparam b_next_0_sqmuxa_7_4_a_cZ.lut_mask="0f1f";
4076 defparam b_next_0_sqmuxa_7_4_a_cZ.synch_mode="off";
4077 defparam b_next_0_sqmuxa_7_4_a_cZ.sum_lutc_input="datac";
4078 // @12:75
4079   stratix_lcell b_next_0_sqmuxa_7_3_cZ (
4080         .combout(b_next_0_sqmuxa_7_3),
4081         .clk(GND),
4082         .dataa(column_counter_sig_7),
4083         .datab(column_counter_sig_9),
4084         .datac(b_next_0_sqmuxa_7_2),
4085         .datad(un9_v_enablelto6),
4086         .aclr(GND),
4087         .sclr(GND),
4088         .sload(GND),
4089         .ena(VCC),
4090         .inverta(GND),
4091         .aload(GND),
4092         .regcascin(GND)
4093 );
4094 defparam b_next_0_sqmuxa_7_3_cZ.operation_mode="normal";
4095 defparam b_next_0_sqmuxa_7_3_cZ.output_mode="comb_only";
4096 defparam b_next_0_sqmuxa_7_3_cZ.lut_mask="e0f0";
4097 defparam b_next_0_sqmuxa_7_3_cZ.synch_mode="off";
4098 defparam b_next_0_sqmuxa_7_3_cZ.sum_lutc_input="datac";
4099 // @12:111
4100   stratix_lcell BLINKER_next_un1_toggle_counter_siglto15 (
4101         .combout(un1_toggle_counter_siglto15),
4102         .clk(GND),
4103         .dataa(toggle_counter_sig_13),
4104         .datab(toggle_counter_sig_14),
4105         .datac(toggle_counter_sig_15),
4106         .datad(un1_toggle_counter_siglto12),
4107         .aclr(GND),
4108         .sclr(GND),
4109         .sload(GND),
4110         .ena(VCC),
4111         .inverta(GND),
4112         .aload(GND),
4113         .regcascin(GND)
4114 );
4115 defparam BLINKER_next_un1_toggle_counter_siglto15.operation_mode="normal";
4116 defparam BLINKER_next_un1_toggle_counter_siglto15.output_mode="comb_only";
4117 defparam BLINKER_next_un1_toggle_counter_siglto15.lut_mask="ff7f";
4118 defparam BLINKER_next_un1_toggle_counter_siglto15.synch_mode="off";
4119 defparam BLINKER_next_un1_toggle_counter_siglto15.sum_lutc_input="datac";
4120 // @12:75
4121   stratix_lcell DRAW_SQUARE_next_un5_v_enablelto5 (
4122         .combout(un5_v_enablelto5),
4123         .clk(GND),
4124         .dataa(column_counter_sig_4),
4125         .datab(column_counter_sig_5),
4126         .datac(column_counter_sig_3),
4127         .datad(un5_v_enablelt2),
4128         .aclr(GND),
4129         .sclr(GND),
4130         .sload(GND),
4131         .ena(VCC),
4132         .inverta(GND),
4133         .aload(GND),
4134         .regcascin(GND)
4135 );
4136 defparam DRAW_SQUARE_next_un5_v_enablelto5.operation_mode="normal";
4137 defparam DRAW_SQUARE_next_un5_v_enablelto5.output_mode="comb_only";
4138 defparam DRAW_SQUARE_next_un5_v_enablelto5.lut_mask="feee";
4139 defparam DRAW_SQUARE_next_un5_v_enablelto5.synch_mode="off";
4140 defparam DRAW_SQUARE_next_un5_v_enablelto5.sum_lutc_input="datac";
4141 // @12:111
4142   stratix_lcell BLINKER_next_un1_toggle_counter_siglto12 (
4143         .combout(un1_toggle_counter_siglto12),
4144         .clk(GND),
4145         .dataa(toggle_counter_sig_10),
4146         .datab(toggle_counter_sig_11),
4147         .datac(toggle_counter_sig_12),
4148         .datad(un1_toggle_counter_siglto9),
4149         .aclr(GND),
4150         .sclr(GND),
4151         .sload(GND),
4152         .ena(VCC),
4153         .inverta(GND),
4154         .aload(GND),
4155         .regcascin(GND)
4156 );
4157 defparam BLINKER_next_un1_toggle_counter_siglto12.operation_mode="normal";
4158 defparam BLINKER_next_un1_toggle_counter_siglto12.output_mode="comb_only";
4159 defparam BLINKER_next_un1_toggle_counter_siglto12.lut_mask="0100";
4160 defparam BLINKER_next_un1_toggle_counter_siglto12.synch_mode="off";
4161 defparam BLINKER_next_un1_toggle_counter_siglto12.sum_lutc_input="datac";
4162 // @12:76
4163   stratix_lcell DRAW_SQUARE_next_un13_v_enablelto6 (
4164         .combout(un13_v_enablelto6),
4165         .clk(GND),
4166         .dataa(line_counter_sig_5),
4167         .datab(line_counter_sig_6),
4168         .datac(line_counter_sig_3),
4169         .datad(un13_v_enablelto4_0),
4170         .aclr(GND),
4171         .sclr(GND),
4172         .sload(GND),
4173         .ena(VCC),
4174         .inverta(GND),
4175         .aload(GND),
4176         .regcascin(GND)
4177 );
4178 defparam DRAW_SQUARE_next_un13_v_enablelto6.operation_mode="normal";
4179 defparam DRAW_SQUARE_next_un13_v_enablelto6.output_mode="comb_only";
4180 defparam DRAW_SQUARE_next_un13_v_enablelto6.lut_mask="7f77";
4181 defparam DRAW_SQUARE_next_un13_v_enablelto6.synch_mode="off";
4182 defparam DRAW_SQUARE_next_un13_v_enablelto6.sum_lutc_input="datac";
4183 // @12:75
4184   stratix_lcell DRAW_SQUARE_next_un9_v_enablelto6 (
4185         .combout(un9_v_enablelto6),
4186         .clk(GND),
4187         .dataa(column_counter_sig_5),
4188         .datab(column_counter_sig_6),
4189         .datac(un9_v_enablelto4),
4190         .datad(VCC),
4191         .aclr(GND),
4192         .sclr(GND),
4193         .sload(GND),
4194         .ena(VCC),
4195         .inverta(GND),
4196         .aload(GND),
4197         .regcascin(GND)
4198 );
4199 defparam DRAW_SQUARE_next_un9_v_enablelto6.operation_mode="normal";
4200 defparam DRAW_SQUARE_next_un9_v_enablelto6.output_mode="comb_only";
4201 defparam DRAW_SQUARE_next_un9_v_enablelto6.lut_mask="f7f7";
4202 defparam DRAW_SQUARE_next_un9_v_enablelto6.synch_mode="off";
4203 defparam DRAW_SQUARE_next_un9_v_enablelto6.sum_lutc_input="datac";
4204 // @12:111
4205   stratix_lcell BLINKER_next_un1_toggle_counter_siglto9 (
4206         .combout(un1_toggle_counter_siglto9),
4207         .clk(GND),
4208         .dataa(toggle_counter_sig_8),
4209         .datab(toggle_counter_sig_9),
4210         .datac(toggle_counter_sig_7),
4211         .datad(un1_toggle_counter_siglt6),
4212         .aclr(GND),
4213         .sclr(GND),
4214         .sload(GND),
4215         .ena(VCC),
4216         .inverta(GND),
4217         .aload(GND),
4218         .regcascin(GND)
4219 );
4220 defparam BLINKER_next_un1_toggle_counter_siglto9.operation_mode="normal";
4221 defparam BLINKER_next_un1_toggle_counter_siglto9.output_mode="comb_only";
4222 defparam BLINKER_next_un1_toggle_counter_siglto9.lut_mask="7f77";
4223 defparam BLINKER_next_un1_toggle_counter_siglto9.synch_mode="off";
4224 defparam BLINKER_next_un1_toggle_counter_siglto9.sum_lutc_input="datac";
4225 // @12:76
4226   stratix_lcell DRAW_SQUARE_next_un17_v_enablelto3 (
4227         .combout(un17_v_enablelto3),
4228         .clk(GND),
4229         .dataa(line_counter_sig_1),
4230         .datab(line_counter_sig_2),
4231         .datac(line_counter_sig_0),
4232         .datad(line_counter_sig_3),
4233         .aclr(GND),
4234         .sclr(GND),
4235         .sload(GND),
4236         .ena(VCC),
4237         .inverta(GND),
4238         .aload(GND),
4239         .regcascin(GND)
4240 );
4241 defparam DRAW_SQUARE_next_un17_v_enablelto3.operation_mode="normal";
4242 defparam DRAW_SQUARE_next_un17_v_enablelto3.output_mode="comb_only";
4243 defparam DRAW_SQUARE_next_un17_v_enablelto3.lut_mask="fe00";
4244 defparam DRAW_SQUARE_next_un17_v_enablelto3.synch_mode="off";
4245 defparam DRAW_SQUARE_next_un17_v_enablelto3.sum_lutc_input="datac";
4246   stratix_lcell toggle_sig_0_0_0_g1_2_cZ (
4247         .combout(toggle_sig_0_0_0_g1_2),
4248         .clk(GND),
4249         .dataa(toggle_counter_sig_23),
4250         .datab(toggle_counter_sig_24),
4251         .datac(toggle_counter_sig_21),
4252         .datad(toggle_counter_sig_22),
4253         .aclr(GND),
4254         .sclr(GND),
4255         .sload(GND),
4256         .ena(VCC),
4257         .inverta(GND),
4258         .aload(GND),
4259         .regcascin(GND)
4260 );
4261 defparam toggle_sig_0_0_0_g1_2_cZ.operation_mode="normal";
4262 defparam toggle_sig_0_0_0_g1_2_cZ.output_mode="comb_only";
4263 defparam toggle_sig_0_0_0_g1_2_cZ.lut_mask="fffe";
4264 defparam toggle_sig_0_0_0_g1_2_cZ.synch_mode="off";
4265 defparam toggle_sig_0_0_0_g1_2_cZ.sum_lutc_input="datac";
4266 // @12:75
4267   stratix_lcell b_next_0_sqmuxa_7_2_cZ (
4268         .combout(b_next_0_sqmuxa_7_2),
4269         .clk(GND),
4270         .dataa(column_counter_sig_8),
4271         .datab(h_enable_sig),
4272         .datac(column_counter_sig_9),
4273         .datad(line_counter_sig_8),
4274         .aclr(GND),
4275         .sclr(GND),
4276         .sload(GND),
4277         .ena(VCC),
4278         .inverta(GND),
4279         .aload(GND),
4280         .regcascin(GND)
4281 );
4282 defparam b_next_0_sqmuxa_7_2_cZ.operation_mode="normal";
4283 defparam b_next_0_sqmuxa_7_2_cZ.output_mode="comb_only";
4284 defparam b_next_0_sqmuxa_7_2_cZ.lut_mask="0004";
4285 defparam b_next_0_sqmuxa_7_2_cZ.synch_mode="off";
4286 defparam b_next_0_sqmuxa_7_2_cZ.sum_lutc_input="datac";
4287 // @12:75
4288   stratix_lcell DRAW_SQUARE_next_un9_v_enablelto4 (
4289         .combout(un9_v_enablelto4),
4290         .clk(GND),
4291         .dataa(column_counter_sig_3),
4292         .datab(column_counter_sig_4),
4293         .datac(column_counter_sig_2),
4294         .datad(VCC),
4295         .aclr(GND),
4296         .sclr(GND),
4297         .sload(GND),
4298         .ena(VCC),
4299         .inverta(GND),
4300         .aload(GND),
4301         .regcascin(GND)
4302 );
4303 defparam DRAW_SQUARE_next_un9_v_enablelto4.operation_mode="normal";
4304 defparam DRAW_SQUARE_next_un9_v_enablelto4.output_mode="comb_only";
4305 defparam DRAW_SQUARE_next_un9_v_enablelto4.lut_mask="0101";
4306 defparam DRAW_SQUARE_next_un9_v_enablelto4.synch_mode="off";
4307 defparam DRAW_SQUARE_next_un9_v_enablelto4.sum_lutc_input="datac";
4308 // @12:75
4309   stratix_lcell DRAW_SQUARE_next_un5_v_enablelt2 (
4310         .combout(un5_v_enablelt2),
4311         .clk(GND),
4312         .dataa(column_counter_sig_1),
4313         .datab(column_counter_sig_2),
4314         .datac(column_counter_sig_0),
4315         .datad(VCC),
4316         .aclr(GND),
4317         .sclr(GND),
4318         .sload(GND),
4319         .ena(VCC),
4320         .inverta(GND),
4321         .aload(GND),
4322         .regcascin(GND)
4323 );
4324 defparam DRAW_SQUARE_next_un5_v_enablelt2.operation_mode="normal";
4325 defparam DRAW_SQUARE_next_un5_v_enablelt2.output_mode="comb_only";
4326 defparam DRAW_SQUARE_next_un5_v_enablelt2.lut_mask="fefe";
4327 defparam DRAW_SQUARE_next_un5_v_enablelt2.synch_mode="off";
4328 defparam DRAW_SQUARE_next_un5_v_enablelt2.sum_lutc_input="datac";
4329 // @12:76
4330   stratix_lcell DRAW_SQUARE_next_un13_v_enablelto4_0 (
4331         .combout(un13_v_enablelto4_0),
4332         .clk(GND),
4333         .dataa(line_counter_sig_4),
4334         .datab(line_counter_sig_2),
4335         .datac(VCC),
4336         .datad(VCC),
4337         .aclr(GND),
4338         .sclr(GND),
4339         .sload(GND),
4340         .ena(VCC),
4341         .inverta(GND),
4342         .aload(GND),
4343         .regcascin(GND)
4344 );
4345 defparam DRAW_SQUARE_next_un13_v_enablelto4_0.operation_mode="normal";
4346 defparam DRAW_SQUARE_next_un13_v_enablelto4_0.output_mode="comb_only";
4347 defparam DRAW_SQUARE_next_un13_v_enablelto4_0.lut_mask="1111";
4348 defparam DRAW_SQUARE_next_un13_v_enablelto4_0.synch_mode="off";
4349 defparam DRAW_SQUARE_next_un13_v_enablelto4_0.sum_lutc_input="datac";
4350 // @12:111
4351   stratix_lcell BLINKER_next_un1_toggle_counter_siglt6 (
4352         .combout(un1_toggle_counter_siglt6),
4353         .clk(GND),
4354         .dataa(toggle_counter_sig_6),
4355         .datab(toggle_counter_sig_5),
4356         .datac(VCC),
4357         .datad(VCC),
4358         .aclr(GND),
4359         .sclr(GND),
4360         .sload(GND),
4361         .ena(VCC),
4362         .inverta(GND),
4363         .aload(GND),
4364         .regcascin(GND)
4365 );
4366 defparam BLINKER_next_un1_toggle_counter_siglt6.operation_mode="normal";
4367 defparam BLINKER_next_un1_toggle_counter_siglt6.output_mode="comb_only";
4368 defparam BLINKER_next_un1_toggle_counter_siglt6.lut_mask="7777";
4369 defparam BLINKER_next_un1_toggle_counter_siglt6.synch_mode="off";
4370 defparam BLINKER_next_un1_toggle_counter_siglt6.sum_lutc_input="datac";
4371 // @12:115
4372   stratix_lcell un2_toggle_counter_next_0_ (
4373         .cout(un2_toggle_counter_next_cout[0]),
4374         .clk(GND),
4375         .dataa(toggle_counter_sig_0),
4376         .datab(toggle_counter_sig_1),
4377         .datac(VCC),
4378         .datad(VCC),
4379         .aclr(GND),
4380         .sclr(GND),
4381         .sload(GND),
4382         .ena(VCC),
4383         .inverta(GND),
4384         .aload(GND),
4385         .regcascin(GND)
4386 );
4387 defparam un2_toggle_counter_next_0_.operation_mode="arithmetic";
4388 defparam un2_toggle_counter_next_0_.output_mode="comb_only";
4389 defparam un2_toggle_counter_next_0_.lut_mask="5588";
4390 defparam un2_toggle_counter_next_0_.synch_mode="off";
4391 defparam un2_toggle_counter_next_0_.sum_lutc_input="datac";
4392   assign  toggle_sig_0_0_0_g1_i = ~ toggle_sig_0_0_0_g1;
4393 endmodule /* vga_control */
4394
4395 // VQM4.1+
4396 module vga (
4397   clk_pin,
4398   reset_pin,
4399   r0_pin,
4400   r1_pin,
4401   r2_pin,
4402   g0_pin,
4403   g1_pin,
4404   g2_pin,
4405   b0_pin,
4406   b1_pin,
4407   hsync_pin,
4408   vsync_pin,
4409   seven_seg_pin,
4410   d_hsync,
4411   d_vsync,
4412   d_column_counter,
4413   d_line_counter,
4414   d_set_column_counter,
4415   d_set_line_counter,
4416   d_hsync_counter,
4417   d_vsync_counter,
4418   d_set_hsync_counter,
4419   d_set_vsync_counter,
4420   d_h_enable,
4421   d_v_enable,
4422   d_r,
4423   d_g,
4424   d_b,
4425   d_hsync_state,
4426   d_vsync_state,
4427   d_state_clk,
4428   d_toggle,
4429   d_toggle_counter
4430 )
4431 ;
4432 input clk_pin ;
4433 input reset_pin ;
4434 output r0_pin ;
4435 output r1_pin ;
4436 output r2_pin ;
4437 output g0_pin ;
4438 output g1_pin ;
4439 output g2_pin ;
4440 output b0_pin ;
4441 output b1_pin ;
4442 output hsync_pin ;
4443 output vsync_pin ;
4444 output [13:0] seven_seg_pin ;
4445 output d_hsync ;
4446 output d_vsync ;
4447 output [9:0] d_column_counter ;
4448 output [8:0] d_line_counter ;
4449 output d_set_column_counter ;
4450 output d_set_line_counter ;
4451 output [9:0] d_hsync_counter ;
4452 output [9:0] d_vsync_counter ;
4453 output d_set_hsync_counter ;
4454 output d_set_vsync_counter ;
4455 output d_h_enable ;
4456 output d_v_enable ;
4457 output d_r ;
4458 output d_g ;
4459 output d_b ;
4460 output [0:6] d_hsync_state ;
4461 output [0:6] d_vsync_state ;
4462 output d_state_clk ;
4463 output d_toggle ;
4464 output [24:0] d_toggle_counter ;
4465 wire clk_pin ;
4466 wire reset_pin ;
4467 wire r0_pin ;
4468 wire r1_pin ;
4469 wire r2_pin ;
4470 wire g0_pin ;
4471 wire g1_pin ;
4472 wire g2_pin ;
4473 wire b0_pin ;
4474 wire b1_pin ;
4475 wire hsync_pin ;
4476 wire vsync_pin ;
4477 wire d_hsync ;
4478 wire d_vsync ;
4479 wire d_set_column_counter ;
4480 wire d_set_line_counter ;
4481 wire d_set_hsync_counter ;
4482 wire d_set_vsync_counter ;
4483 wire d_h_enable ;
4484 wire d_v_enable ;
4485 wire d_r ;
4486 wire d_g ;
4487 wire d_b ;
4488 wire d_state_clk ;
4489 wire d_toggle ;
4490 wire [1:0] dly_counter;
4491 wire [9:0] vga_driver_unit_column_counter_sig;
4492 wire [8:0] vga_driver_unit_line_counter_sig;
4493 wire [9:0] vga_driver_unit_hsync_counter;
4494 wire [9:0] vga_driver_unit_vsync_counter;
4495 wire [6:0] vga_driver_unit_hsync_state;
4496 wire [6:0] vga_driver_unit_vsync_state;
4497 wire [24:0] vga_control_unit_toggle_counter_sig;
4498 wire VCC ;
4499 wire GND ;
4500 wire DELAY_RESET_next_un6_dly_counter_0_x ;
4501 wire vga_driver_unit_h_sync ;
4502 wire vga_driver_unit_v_sync ;
4503 wire vga_driver_unit_d_set_hsync_counter ;
4504 wire vga_driver_unit_d_set_vsync_counter ;
4505 wire vga_driver_unit_h_enable_sig ;
4506 wire vga_driver_unit_v_enable_sig ;
4507 wire vga_control_unit_r ;
4508 wire vga_control_unit_g ;
4509 wire vga_control_unit_b ;
4510 wire G_33 ;
4511 wire vga_control_unit_toggle_sig ;
4512 wire reset_pin_c ;
4513 //@1:1
4514   assign VCC = 1'b1;
4515 //@1:1
4516   assign GND = 1'b0;
4517 // @10:113
4518   stratix_lcell dly_counter_1_ (
4519         .regout(dly_counter[1]),
4520         .clk(G_33),
4521         .dataa(reset_pin_c),
4522         .datab(dly_counter[0]),
4523         .datac(dly_counter[1]),
4524         .datad(VCC),
4525         .aclr(GND),
4526         .sclr(GND),
4527         .sload(GND),
4528         .ena(VCC),
4529         .inverta(GND),
4530         .aload(GND),
4531         .regcascin(GND)
4532 );
4533 defparam dly_counter_1_.operation_mode="normal";
4534 defparam dly_counter_1_.output_mode="reg_only";
4535 defparam dly_counter_1_.lut_mask="a8a8";
4536 defparam dly_counter_1_.synch_mode="off";
4537 defparam dly_counter_1_.sum_lutc_input="datac";
4538 // @10:113
4539   stratix_lcell dly_counter_0_ (
4540         .regout(dly_counter[0]),
4541         .clk(G_33),
4542         .dataa(reset_pin_c),
4543         .datab(dly_counter[0]),
4544         .datac(dly_counter[1]),
4545         .datad(VCC),
4546         .aclr(GND),
4547         .sclr(GND),
4548         .sload(GND),
4549         .ena(VCC),
4550         .inverta(GND),
4551         .aload(GND),
4552         .regcascin(GND)
4553 );
4554 defparam dly_counter_0_.operation_mode="normal";
4555 defparam dly_counter_0_.output_mode="reg_only";
4556 defparam dly_counter_0_.lut_mask="a2a2";
4557 defparam dly_counter_0_.synch_mode="off";
4558 defparam dly_counter_0_.sum_lutc_input="datac";
4559 // @6:42
4560   stratix_io reset_pin_in (
4561         .padio(reset_pin),
4562         .combout(reset_pin_c),
4563         .datain(GND),
4564         .oe(GND),
4565         .outclk(GND),
4566         .outclkena(VCC),
4567         .inclk(GND),
4568         .inclkena(VCC),
4569         .areset(GND),
4570         .sreset(GND)
4571 );
4572 defparam reset_pin_in.operation_mode = "input";
4573 // @6:41
4574   stratix_io clk_pin_in (
4575         .padio(clk_pin),
4576         .combout(G_33),
4577         .datain(GND),
4578         .oe(GND),
4579         .outclk(GND),
4580         .outclkena(VCC),
4581         .inclk(GND),
4582         .inclkena(VCC),
4583         .areset(GND),
4584         .sreset(GND)
4585 );
4586 defparam clk_pin_in.operation_mode = "input";
4587 // @6:66
4588   stratix_io d_toggle_counter_out_24_ (
4589         .padio(d_toggle_counter[24]),
4590         .datain(vga_control_unit_toggle_counter_sig[24]),
4591         .oe(VCC),
4592         .outclk(GND),
4593         .outclkena(VCC),
4594         .inclk(GND),
4595         .inclkena(VCC),
4596         .areset(GND),
4597         .sreset(GND)
4598 );
4599 defparam d_toggle_counter_out_24_.operation_mode = "output";
4600 // @6:66
4601   stratix_io d_toggle_counter_out_23_ (
4602         .padio(d_toggle_counter[23]),
4603         .datain(vga_control_unit_toggle_counter_sig[23]),
4604         .oe(VCC),
4605         .outclk(GND),
4606         .outclkena(VCC),
4607         .inclk(GND),
4608         .inclkena(VCC),
4609         .areset(GND),
4610         .sreset(GND)
4611 );
4612 defparam d_toggle_counter_out_23_.operation_mode = "output";
4613 // @6:66
4614   stratix_io d_toggle_counter_out_22_ (
4615         .padio(d_toggle_counter[22]),
4616         .datain(vga_control_unit_toggle_counter_sig[22]),
4617         .oe(VCC),
4618         .outclk(GND),
4619         .outclkena(VCC),
4620         .inclk(GND),
4621         .inclkena(VCC),
4622         .areset(GND),
4623         .sreset(GND)
4624 );
4625 defparam d_toggle_counter_out_22_.operation_mode = "output";
4626 // @6:66
4627   stratix_io d_toggle_counter_out_21_ (
4628         .padio(d_toggle_counter[21]),
4629         .datain(vga_control_unit_toggle_counter_sig[21]),
4630         .oe(VCC),
4631         .outclk(GND),
4632         .outclkena(VCC),
4633         .inclk(GND),
4634         .inclkena(VCC),
4635         .areset(GND),
4636         .sreset(GND)
4637 );
4638 defparam d_toggle_counter_out_21_.operation_mode = "output";
4639 // @6:66
4640   stratix_io d_toggle_counter_out_20_ (
4641         .padio(d_toggle_counter[20]),
4642         .datain(vga_control_unit_toggle_counter_sig[20]),
4643         .oe(VCC),
4644         .outclk(GND),
4645         .outclkena(VCC),
4646         .inclk(GND),
4647         .inclkena(VCC),
4648         .areset(GND),
4649         .sreset(GND)
4650 );
4651 defparam d_toggle_counter_out_20_.operation_mode = "output";
4652 // @6:66
4653   stratix_io d_toggle_counter_out_19_ (
4654         .padio(d_toggle_counter[19]),
4655         .datain(vga_control_unit_toggle_counter_sig[19]),
4656         .oe(VCC),
4657         .outclk(GND),
4658         .outclkena(VCC),
4659         .inclk(GND),
4660         .inclkena(VCC),
4661         .areset(GND),
4662         .sreset(GND)
4663 );
4664 defparam d_toggle_counter_out_19_.operation_mode = "output";
4665 // @6:66
4666   stratix_io d_toggle_counter_out_18_ (
4667         .padio(d_toggle_counter[18]),
4668         .datain(vga_control_unit_toggle_counter_sig[18]),
4669         .oe(VCC),
4670         .outclk(GND),
4671         .outclkena(VCC),
4672         .inclk(GND),
4673         .inclkena(VCC),
4674         .areset(GND),
4675         .sreset(GND)
4676 );
4677 defparam d_toggle_counter_out_18_.operation_mode = "output";
4678 // @6:66
4679   stratix_io d_toggle_counter_out_17_ (
4680         .padio(d_toggle_counter[17]),
4681         .datain(vga_control_unit_toggle_counter_sig[17]),
4682         .oe(VCC),
4683         .outclk(GND),
4684         .outclkena(VCC),
4685         .inclk(GND),
4686         .inclkena(VCC),
4687         .areset(GND),
4688         .sreset(GND)
4689 );
4690 defparam d_toggle_counter_out_17_.operation_mode = "output";
4691 // @6:66
4692   stratix_io d_toggle_counter_out_16_ (
4693         .padio(d_toggle_counter[16]),
4694         .datain(vga_control_unit_toggle_counter_sig[16]),
4695         .oe(VCC),
4696         .outclk(GND),
4697         .outclkena(VCC),
4698         .inclk(GND),
4699         .inclkena(VCC),
4700         .areset(GND),
4701         .sreset(GND)
4702 );
4703 defparam d_toggle_counter_out_16_.operation_mode = "output";
4704 // @6:66
4705   stratix_io d_toggle_counter_out_15_ (
4706         .padio(d_toggle_counter[15]),
4707         .datain(vga_control_unit_toggle_counter_sig[15]),
4708         .oe(VCC),
4709         .outclk(GND),
4710         .outclkena(VCC),
4711         .inclk(GND),
4712         .inclkena(VCC),
4713         .areset(GND),
4714         .sreset(GND)
4715 );
4716 defparam d_toggle_counter_out_15_.operation_mode = "output";
4717 // @6:66
4718   stratix_io d_toggle_counter_out_14_ (
4719         .padio(d_toggle_counter[14]),
4720         .datain(vga_control_unit_toggle_counter_sig[14]),
4721         .oe(VCC),
4722         .outclk(GND),
4723         .outclkena(VCC),
4724         .inclk(GND),
4725         .inclkena(VCC),
4726         .areset(GND),
4727         .sreset(GND)
4728 );
4729 defparam d_toggle_counter_out_14_.operation_mode = "output";
4730 // @6:66
4731   stratix_io d_toggle_counter_out_13_ (
4732         .padio(d_toggle_counter[13]),
4733         .datain(vga_control_unit_toggle_counter_sig[13]),
4734         .oe(VCC),
4735         .outclk(GND),
4736         .outclkena(VCC),
4737         .inclk(GND),
4738         .inclkena(VCC),
4739         .areset(GND),
4740         .sreset(GND)
4741 );
4742 defparam d_toggle_counter_out_13_.operation_mode = "output";
4743 // @6:66
4744   stratix_io d_toggle_counter_out_12_ (
4745         .padio(d_toggle_counter[12]),
4746         .datain(vga_control_unit_toggle_counter_sig[12]),
4747         .oe(VCC),
4748         .outclk(GND),
4749         .outclkena(VCC),
4750         .inclk(GND),
4751         .inclkena(VCC),
4752         .areset(GND),
4753         .sreset(GND)
4754 );
4755 defparam d_toggle_counter_out_12_.operation_mode = "output";
4756 // @6:66
4757   stratix_io d_toggle_counter_out_11_ (
4758         .padio(d_toggle_counter[11]),
4759         .datain(vga_control_unit_toggle_counter_sig[11]),
4760         .oe(VCC),
4761         .outclk(GND),
4762         .outclkena(VCC),
4763         .inclk(GND),
4764         .inclkena(VCC),
4765         .areset(GND),
4766         .sreset(GND)
4767 );
4768 defparam d_toggle_counter_out_11_.operation_mode = "output";
4769 // @6:66
4770   stratix_io d_toggle_counter_out_10_ (
4771         .padio(d_toggle_counter[10]),
4772         .datain(vga_control_unit_toggle_counter_sig[10]),
4773         .oe(VCC),
4774         .outclk(GND),
4775         .outclkena(VCC),
4776         .inclk(GND),
4777         .inclkena(VCC),
4778         .areset(GND),
4779         .sreset(GND)
4780 );
4781 defparam d_toggle_counter_out_10_.operation_mode = "output";
4782 // @6:66
4783   stratix_io d_toggle_counter_out_9_ (
4784         .padio(d_toggle_counter[9]),
4785         .datain(vga_control_unit_toggle_counter_sig[9]),
4786         .oe(VCC),
4787         .outclk(GND),
4788         .outclkena(VCC),
4789         .inclk(GND),
4790         .inclkena(VCC),
4791         .areset(GND),
4792         .sreset(GND)
4793 );
4794 defparam d_toggle_counter_out_9_.operation_mode = "output";
4795 // @6:66
4796   stratix_io d_toggle_counter_out_8_ (
4797         .padio(d_toggle_counter[8]),
4798         .datain(vga_control_unit_toggle_counter_sig[8]),
4799         .oe(VCC),
4800         .outclk(GND),
4801         .outclkena(VCC),
4802         .inclk(GND),
4803         .inclkena(VCC),
4804         .areset(GND),
4805         .sreset(GND)
4806 );
4807 defparam d_toggle_counter_out_8_.operation_mode = "output";
4808 // @6:66
4809   stratix_io d_toggle_counter_out_7_ (
4810         .padio(d_toggle_counter[7]),
4811         .datain(vga_control_unit_toggle_counter_sig[7]),
4812         .oe(VCC),
4813         .outclk(GND),
4814         .outclkena(VCC),
4815         .inclk(GND),
4816         .inclkena(VCC),
4817         .areset(GND),
4818         .sreset(GND)
4819 );
4820 defparam d_toggle_counter_out_7_.operation_mode = "output";
4821 // @6:66
4822   stratix_io d_toggle_counter_out_6_ (
4823         .padio(d_toggle_counter[6]),
4824         .datain(vga_control_unit_toggle_counter_sig[6]),
4825         .oe(VCC),
4826         .outclk(GND),
4827         .outclkena(VCC),
4828         .inclk(GND),
4829         .inclkena(VCC),
4830         .areset(GND),
4831         .sreset(GND)
4832 );
4833 defparam d_toggle_counter_out_6_.operation_mode = "output";
4834 // @6:66
4835   stratix_io d_toggle_counter_out_5_ (
4836         .padio(d_toggle_counter[5]),
4837         .datain(vga_control_unit_toggle_counter_sig[5]),
4838         .oe(VCC),
4839         .outclk(GND),
4840         .outclkena(VCC),
4841         .inclk(GND),
4842         .inclkena(VCC),
4843         .areset(GND),
4844         .sreset(GND)
4845 );
4846 defparam d_toggle_counter_out_5_.operation_mode = "output";
4847 // @6:66
4848   stratix_io d_toggle_counter_out_4_ (
4849         .padio(d_toggle_counter[4]),
4850         .datain(vga_control_unit_toggle_counter_sig[4]),
4851         .oe(VCC),
4852         .outclk(GND),
4853         .outclkena(VCC),
4854         .inclk(GND),
4855         .inclkena(VCC),
4856         .areset(GND),
4857         .sreset(GND)
4858 );
4859 defparam d_toggle_counter_out_4_.operation_mode = "output";
4860 // @6:66
4861   stratix_io d_toggle_counter_out_3_ (
4862         .padio(d_toggle_counter[3]),
4863         .datain(vga_control_unit_toggle_counter_sig[3]),
4864         .oe(VCC),
4865         .outclk(GND),
4866         .outclkena(VCC),
4867         .inclk(GND),
4868         .inclkena(VCC),
4869         .areset(GND),
4870         .sreset(GND)
4871 );
4872 defparam d_toggle_counter_out_3_.operation_mode = "output";
4873 // @6:66
4874   stratix_io d_toggle_counter_out_2_ (
4875         .padio(d_toggle_counter[2]),
4876         .datain(vga_control_unit_toggle_counter_sig[2]),
4877         .oe(VCC),
4878         .outclk(GND),
4879         .outclkena(VCC),
4880         .inclk(GND),
4881         .inclkena(VCC),
4882         .areset(GND),
4883         .sreset(GND)
4884 );
4885 defparam d_toggle_counter_out_2_.operation_mode = "output";
4886 // @6:66
4887   stratix_io d_toggle_counter_out_1_ (
4888         .padio(d_toggle_counter[1]),
4889         .datain(vga_control_unit_toggle_counter_sig[1]),
4890         .oe(VCC),
4891         .outclk(GND),
4892         .outclkena(VCC),
4893         .inclk(GND),
4894         .inclkena(VCC),
4895         .areset(GND),
4896         .sreset(GND)
4897 );
4898 defparam d_toggle_counter_out_1_.operation_mode = "output";
4899 // @6:66
4900   stratix_io d_toggle_counter_out_0_ (
4901         .padio(d_toggle_counter[0]),
4902         .datain(vga_control_unit_toggle_counter_sig[0]),
4903         .oe(VCC),
4904         .outclk(GND),
4905         .outclkena(VCC),
4906         .inclk(GND),
4907         .inclkena(VCC),
4908         .areset(GND),
4909         .sreset(GND)
4910 );
4911 defparam d_toggle_counter_out_0_.operation_mode = "output";
4912 // @6:65
4913   stratix_io d_toggle_out (
4914         .padio(d_toggle),
4915         .datain(vga_control_unit_toggle_sig),
4916         .oe(VCC),
4917         .outclk(GND),
4918         .outclkena(VCC),
4919         .inclk(GND),
4920         .inclkena(VCC),
4921         .areset(GND),
4922         .sreset(GND)
4923 );
4924 defparam d_toggle_out.operation_mode = "output";
4925 // @6:64
4926   stratix_io d_state_clk_out (
4927         .padio(d_state_clk),
4928         .datain(G_33),
4929         .oe(VCC),
4930         .outclk(GND),
4931         .outclkena(VCC),
4932         .inclk(GND),
4933         .inclkena(VCC),
4934         .areset(GND),
4935         .sreset(GND)
4936 );
4937 defparam d_state_clk_out.operation_mode = "output";
4938 // @6:63
4939   stratix_io d_vsync_state_out_0_ (
4940         .padio(d_vsync_state[0]),
4941         .datain(vga_driver_unit_vsync_state[0]),
4942         .oe(VCC),
4943         .outclk(GND),
4944         .outclkena(VCC),
4945         .inclk(GND),
4946         .inclkena(VCC),
4947         .areset(GND),
4948         .sreset(GND)
4949 );
4950 defparam d_vsync_state_out_0_.operation_mode = "output";
4951 // @6:63
4952   stratix_io d_vsync_state_out_1_ (
4953         .padio(d_vsync_state[1]),
4954         .datain(vga_driver_unit_vsync_state[1]),
4955         .oe(VCC),
4956         .outclk(GND),
4957         .outclkena(VCC),
4958         .inclk(GND),
4959         .inclkena(VCC),
4960         .areset(GND),
4961         .sreset(GND)
4962 );
4963 defparam d_vsync_state_out_1_.operation_mode = "output";
4964 // @6:63
4965   stratix_io d_vsync_state_out_2_ (
4966         .padio(d_vsync_state[2]),
4967         .datain(vga_driver_unit_vsync_state[2]),
4968         .oe(VCC),
4969         .outclk(GND),
4970         .outclkena(VCC),
4971         .inclk(GND),
4972         .inclkena(VCC),
4973         .areset(GND),
4974         .sreset(GND)
4975 );
4976 defparam d_vsync_state_out_2_.operation_mode = "output";
4977 // @6:63
4978   stratix_io d_vsync_state_out_3_ (
4979         .padio(d_vsync_state[3]),
4980         .datain(vga_driver_unit_vsync_state[3]),
4981         .oe(VCC),
4982         .outclk(GND),
4983         .outclkena(VCC),
4984         .inclk(GND),
4985         .inclkena(VCC),
4986         .areset(GND),
4987         .sreset(GND)
4988 );
4989 defparam d_vsync_state_out_3_.operation_mode = "output";
4990 // @6:63
4991   stratix_io d_vsync_state_out_4_ (
4992         .padio(d_vsync_state[4]),
4993         .datain(vga_driver_unit_vsync_state[4]),
4994         .oe(VCC),
4995         .outclk(GND),
4996         .outclkena(VCC),
4997         .inclk(GND),
4998         .inclkena(VCC),
4999         .areset(GND),
5000         .sreset(GND)
5001 );
5002 defparam d_vsync_state_out_4_.operation_mode = "output";
5003 // @6:63
5004   stratix_io d_vsync_state_out_5_ (
5005         .padio(d_vsync_state[5]),
5006         .datain(vga_driver_unit_vsync_state[5]),
5007         .oe(VCC),
5008         .outclk(GND),
5009         .outclkena(VCC),
5010         .inclk(GND),
5011         .inclkena(VCC),
5012         .areset(GND),
5013         .sreset(GND)
5014 );
5015 defparam d_vsync_state_out_5_.operation_mode = "output";
5016 // @6:63
5017   stratix_io d_vsync_state_out_6_ (
5018         .padio(d_vsync_state[6]),
5019         .datain(vga_driver_unit_vsync_state[6]),
5020         .oe(VCC),
5021         .outclk(GND),
5022         .outclkena(VCC),
5023         .inclk(GND),
5024         .inclkena(VCC),
5025         .areset(GND),
5026         .sreset(GND)
5027 );
5028 defparam d_vsync_state_out_6_.operation_mode = "output";
5029 // @6:62
5030   stratix_io d_hsync_state_out_0_ (
5031         .padio(d_hsync_state[0]),
5032         .datain(vga_driver_unit_hsync_state[0]),
5033         .oe(VCC),
5034         .outclk(GND),
5035         .outclkena(VCC),
5036         .inclk(GND),
5037         .inclkena(VCC),
5038         .areset(GND),
5039         .sreset(GND)
5040 );
5041 defparam d_hsync_state_out_0_.operation_mode = "output";
5042 // @6:62
5043   stratix_io d_hsync_state_out_1_ (
5044         .padio(d_hsync_state[1]),
5045         .datain(vga_driver_unit_hsync_state[1]),
5046         .oe(VCC),
5047         .outclk(GND),
5048         .outclkena(VCC),
5049         .inclk(GND),
5050         .inclkena(VCC),
5051         .areset(GND),
5052         .sreset(GND)
5053 );
5054 defparam d_hsync_state_out_1_.operation_mode = "output";
5055 // @6:62
5056   stratix_io d_hsync_state_out_2_ (
5057         .padio(d_hsync_state[2]),
5058         .datain(vga_driver_unit_hsync_state[2]),
5059         .oe(VCC),
5060         .outclk(GND),
5061         .outclkena(VCC),
5062         .inclk(GND),
5063         .inclkena(VCC),
5064         .areset(GND),
5065         .sreset(GND)
5066 );
5067 defparam d_hsync_state_out_2_.operation_mode = "output";
5068 // @6:62
5069   stratix_io d_hsync_state_out_3_ (
5070         .padio(d_hsync_state[3]),
5071         .datain(vga_driver_unit_hsync_state[3]),
5072         .oe(VCC),
5073         .outclk(GND),
5074         .outclkena(VCC),
5075         .inclk(GND),
5076         .inclkena(VCC),
5077         .areset(GND),
5078         .sreset(GND)
5079 );
5080 defparam d_hsync_state_out_3_.operation_mode = "output";
5081 // @6:62
5082   stratix_io d_hsync_state_out_4_ (
5083         .padio(d_hsync_state[4]),
5084         .datain(vga_driver_unit_hsync_state[4]),
5085         .oe(VCC),
5086         .outclk(GND),
5087         .outclkena(VCC),
5088         .inclk(GND),
5089         .inclkena(VCC),
5090         .areset(GND),
5091         .sreset(GND)
5092 );
5093 defparam d_hsync_state_out_4_.operation_mode = "output";
5094 // @6:62
5095   stratix_io d_hsync_state_out_5_ (
5096         .padio(d_hsync_state[5]),
5097         .datain(vga_driver_unit_hsync_state[5]),
5098         .oe(VCC),
5099         .outclk(GND),
5100         .outclkena(VCC),
5101         .inclk(GND),
5102         .inclkena(VCC),
5103         .areset(GND),
5104         .sreset(GND)
5105 );
5106 defparam d_hsync_state_out_5_.operation_mode = "output";
5107 // @6:62
5108   stratix_io d_hsync_state_out_6_ (
5109         .padio(d_hsync_state[6]),
5110         .datain(vga_driver_unit_hsync_state[6]),
5111         .oe(VCC),
5112         .outclk(GND),
5113         .outclkena(VCC),
5114         .inclk(GND),
5115         .inclkena(VCC),
5116         .areset(GND),
5117         .sreset(GND)
5118 );
5119 defparam d_hsync_state_out_6_.operation_mode = "output";
5120 // @6:61
5121   stratix_io d_b_out (
5122         .padio(d_b),
5123         .datain(vga_control_unit_b),
5124         .oe(VCC),
5125         .outclk(GND),
5126         .outclkena(VCC),
5127         .inclk(GND),
5128         .inclkena(VCC),
5129         .areset(GND),
5130         .sreset(GND)
5131 );
5132 defparam d_b_out.operation_mode = "output";
5133 // @6:61
5134   stratix_io d_g_out (
5135         .padio(d_g),
5136         .datain(vga_control_unit_g),
5137         .oe(VCC),
5138         .outclk(GND),
5139         .outclkena(VCC),
5140         .inclk(GND),
5141         .inclkena(VCC),
5142         .areset(GND),
5143         .sreset(GND)
5144 );
5145 defparam d_g_out.operation_mode = "output";
5146 // @6:61
5147   stratix_io d_r_out (
5148         .padio(d_r),
5149         .datain(vga_control_unit_r),
5150         .oe(VCC),
5151         .outclk(GND),
5152         .outclkena(VCC),
5153         .inclk(GND),
5154         .inclkena(VCC),
5155         .areset(GND),
5156         .sreset(GND)
5157 );
5158 defparam d_r_out.operation_mode = "output";
5159 // @6:60
5160   stratix_io d_v_enable_out (
5161         .padio(d_v_enable),
5162         .datain(vga_driver_unit_v_enable_sig),
5163         .oe(VCC),
5164         .outclk(GND),
5165         .outclkena(VCC),
5166         .inclk(GND),
5167         .inclkena(VCC),
5168         .areset(GND),
5169         .sreset(GND)
5170 );
5171 defparam d_v_enable_out.operation_mode = "output";
5172 // @6:59
5173   stratix_io d_h_enable_out (
5174         .padio(d_h_enable),
5175         .datain(vga_driver_unit_h_enable_sig),
5176         .oe(VCC),
5177         .outclk(GND),
5178         .outclkena(VCC),
5179         .inclk(GND),
5180         .inclkena(VCC),
5181         .areset(GND),
5182         .sreset(GND)
5183 );
5184 defparam d_h_enable_out.operation_mode = "output";
5185 // @6:58
5186   stratix_io d_set_vsync_counter_out (
5187         .padio(d_set_vsync_counter),
5188         .datain(vga_driver_unit_d_set_vsync_counter),
5189         .oe(VCC),
5190         .outclk(GND),
5191         .outclkena(VCC),
5192         .inclk(GND),
5193         .inclkena(VCC),
5194         .areset(GND),
5195         .sreset(GND)
5196 );
5197 defparam d_set_vsync_counter_out.operation_mode = "output";
5198 // @6:58
5199   stratix_io d_set_hsync_counter_out (
5200         .padio(d_set_hsync_counter),
5201         .datain(vga_driver_unit_d_set_hsync_counter),
5202         .oe(VCC),
5203         .outclk(GND),
5204         .outclkena(VCC),
5205         .inclk(GND),
5206         .inclkena(VCC),
5207         .areset(GND),
5208         .sreset(GND)
5209 );
5210 defparam d_set_hsync_counter_out.operation_mode = "output";
5211 // @6:57
5212   stratix_io d_vsync_counter_out_9_ (
5213         .padio(d_vsync_counter[9]),
5214         .datain(vga_driver_unit_vsync_counter[9]),
5215         .oe(VCC),
5216         .outclk(GND),
5217         .outclkena(VCC),
5218         .inclk(GND),
5219         .inclkena(VCC),
5220         .areset(GND),
5221         .sreset(GND)
5222 );
5223 defparam d_vsync_counter_out_9_.operation_mode = "output";
5224 // @6:57
5225   stratix_io d_vsync_counter_out_8_ (
5226         .padio(d_vsync_counter[8]),
5227         .datain(vga_driver_unit_vsync_counter[8]),
5228         .oe(VCC),
5229         .outclk(GND),
5230         .outclkena(VCC),
5231         .inclk(GND),
5232         .inclkena(VCC),
5233         .areset(GND),
5234         .sreset(GND)
5235 );
5236 defparam d_vsync_counter_out_8_.operation_mode = "output";
5237 // @6:57
5238   stratix_io d_vsync_counter_out_7_ (
5239         .padio(d_vsync_counter[7]),
5240         .datain(vga_driver_unit_vsync_counter[7]),
5241         .oe(VCC),
5242         .outclk(GND),
5243         .outclkena(VCC),
5244         .inclk(GND),
5245         .inclkena(VCC),
5246         .areset(GND),
5247         .sreset(GND)
5248 );
5249 defparam d_vsync_counter_out_7_.operation_mode = "output";
5250 // @6:57
5251   stratix_io d_vsync_counter_out_6_ (
5252         .padio(d_vsync_counter[6]),
5253         .datain(vga_driver_unit_vsync_counter[6]),
5254         .oe(VCC),
5255         .outclk(GND),
5256         .outclkena(VCC),
5257         .inclk(GND),
5258         .inclkena(VCC),
5259         .areset(GND),
5260         .sreset(GND)
5261 );
5262 defparam d_vsync_counter_out_6_.operation_mode = "output";
5263 // @6:57
5264   stratix_io d_vsync_counter_out_5_ (
5265         .padio(d_vsync_counter[5]),
5266         .datain(vga_driver_unit_vsync_counter[5]),
5267         .oe(VCC),
5268         .outclk(GND),
5269         .outclkena(VCC),
5270         .inclk(GND),
5271         .inclkena(VCC),
5272         .areset(GND),
5273         .sreset(GND)
5274 );
5275 defparam d_vsync_counter_out_5_.operation_mode = "output";
5276 // @6:57
5277   stratix_io d_vsync_counter_out_4_ (
5278         .padio(d_vsync_counter[4]),
5279         .datain(vga_driver_unit_vsync_counter[4]),
5280         .oe(VCC),
5281         .outclk(GND),
5282         .outclkena(VCC),
5283         .inclk(GND),
5284         .inclkena(VCC),
5285         .areset(GND),
5286         .sreset(GND)
5287 );
5288 defparam d_vsync_counter_out_4_.operation_mode = "output";
5289 // @6:57
5290   stratix_io d_vsync_counter_out_3_ (
5291         .padio(d_vsync_counter[3]),
5292         .datain(vga_driver_unit_vsync_counter[3]),
5293         .oe(VCC),
5294         .outclk(GND),
5295         .outclkena(VCC),
5296         .inclk(GND),
5297         .inclkena(VCC),
5298         .areset(GND),
5299         .sreset(GND)
5300 );
5301 defparam d_vsync_counter_out_3_.operation_mode = "output";
5302 // @6:57
5303   stratix_io d_vsync_counter_out_2_ (
5304         .padio(d_vsync_counter[2]),
5305         .datain(vga_driver_unit_vsync_counter[2]),
5306         .oe(VCC),
5307         .outclk(GND),
5308         .outclkena(VCC),
5309         .inclk(GND),
5310         .inclkena(VCC),
5311         .areset(GND),
5312         .sreset(GND)
5313 );
5314 defparam d_vsync_counter_out_2_.operation_mode = "output";
5315 // @6:57
5316   stratix_io d_vsync_counter_out_1_ (
5317         .padio(d_vsync_counter[1]),
5318         .datain(vga_driver_unit_vsync_counter[1]),
5319         .oe(VCC),
5320         .outclk(GND),
5321         .outclkena(VCC),
5322         .inclk(GND),
5323         .inclkena(VCC),
5324         .areset(GND),
5325         .sreset(GND)
5326 );
5327 defparam d_vsync_counter_out_1_.operation_mode = "output";
5328 // @6:57
5329   stratix_io d_vsync_counter_out_0_ (
5330         .padio(d_vsync_counter[0]),
5331         .datain(vga_driver_unit_vsync_counter[0]),
5332         .oe(VCC),
5333         .outclk(GND),
5334         .outclkena(VCC),
5335         .inclk(GND),
5336         .inclkena(VCC),
5337         .areset(GND),
5338         .sreset(GND)
5339 );
5340 defparam d_vsync_counter_out_0_.operation_mode = "output";
5341 // @6:56
5342   stratix_io d_hsync_counter_out_9_ (
5343         .padio(d_hsync_counter[9]),
5344         .datain(vga_driver_unit_hsync_counter[9]),
5345         .oe(VCC),
5346         .outclk(GND),
5347         .outclkena(VCC),
5348         .inclk(GND),
5349         .inclkena(VCC),
5350         .areset(GND),
5351         .sreset(GND)
5352 );
5353 defparam d_hsync_counter_out_9_.operation_mode = "output";
5354 // @6:56
5355   stratix_io d_hsync_counter_out_8_ (
5356         .padio(d_hsync_counter[8]),
5357         .datain(vga_driver_unit_hsync_counter[8]),
5358         .oe(VCC),
5359         .outclk(GND),
5360         .outclkena(VCC),
5361         .inclk(GND),
5362         .inclkena(VCC),
5363         .areset(GND),
5364         .sreset(GND)
5365 );
5366 defparam d_hsync_counter_out_8_.operation_mode = "output";
5367 // @6:56
5368   stratix_io d_hsync_counter_out_7_ (
5369         .padio(d_hsync_counter[7]),
5370         .datain(vga_driver_unit_hsync_counter[7]),
5371         .oe(VCC),
5372         .outclk(GND),
5373         .outclkena(VCC),
5374         .inclk(GND),
5375         .inclkena(VCC),
5376         .areset(GND),
5377         .sreset(GND)
5378 );
5379 defparam d_hsync_counter_out_7_.operation_mode = "output";
5380 // @6:56
5381   stratix_io d_hsync_counter_out_6_ (
5382         .padio(d_hsync_counter[6]),
5383         .datain(vga_driver_unit_hsync_counter[6]),
5384         .oe(VCC),
5385         .outclk(GND),
5386         .outclkena(VCC),
5387         .inclk(GND),
5388         .inclkena(VCC),
5389         .areset(GND),
5390         .sreset(GND)
5391 );
5392 defparam d_hsync_counter_out_6_.operation_mode = "output";
5393 // @6:56
5394   stratix_io d_hsync_counter_out_5_ (
5395         .padio(d_hsync_counter[5]),
5396         .datain(vga_driver_unit_hsync_counter[5]),
5397         .oe(VCC),
5398         .outclk(GND),
5399         .outclkena(VCC),
5400         .inclk(GND),
5401         .inclkena(VCC),
5402         .areset(GND),
5403         .sreset(GND)
5404 );
5405 defparam d_hsync_counter_out_5_.operation_mode = "output";
5406 // @6:56
5407   stratix_io d_hsync_counter_out_4_ (
5408         .padio(d_hsync_counter[4]),
5409         .datain(vga_driver_unit_hsync_counter[4]),
5410         .oe(VCC),
5411         .outclk(GND),
5412         .outclkena(VCC),
5413         .inclk(GND),
5414         .inclkena(VCC),
5415         .areset(GND),
5416         .sreset(GND)
5417 );
5418 defparam d_hsync_counter_out_4_.operation_mode = "output";
5419 // @6:56
5420   stratix_io d_hsync_counter_out_3_ (
5421         .padio(d_hsync_counter[3]),
5422         .datain(vga_driver_unit_hsync_counter[3]),
5423         .oe(VCC),
5424         .outclk(GND),
5425         .outclkena(VCC),
5426         .inclk(GND),
5427         .inclkena(VCC),
5428         .areset(GND),
5429         .sreset(GND)
5430 );
5431 defparam d_hsync_counter_out_3_.operation_mode = "output";
5432 // @6:56
5433   stratix_io d_hsync_counter_out_2_ (
5434         .padio(d_hsync_counter[2]),
5435         .datain(vga_driver_unit_hsync_counter[2]),
5436         .oe(VCC),
5437         .outclk(GND),
5438         .outclkena(VCC),
5439         .inclk(GND),
5440         .inclkena(VCC),
5441         .areset(GND),
5442         .sreset(GND)
5443 );
5444 defparam d_hsync_counter_out_2_.operation_mode = "output";
5445 // @6:56
5446   stratix_io d_hsync_counter_out_1_ (
5447         .padio(d_hsync_counter[1]),
5448         .datain(vga_driver_unit_hsync_counter[1]),
5449         .oe(VCC),
5450         .outclk(GND),
5451         .outclkena(VCC),
5452         .inclk(GND),
5453         .inclkena(VCC),
5454         .areset(GND),
5455         .sreset(GND)
5456 );
5457 defparam d_hsync_counter_out_1_.operation_mode = "output";
5458 // @6:56
5459   stratix_io d_hsync_counter_out_0_ (
5460         .padio(d_hsync_counter[0]),
5461         .datain(vga_driver_unit_hsync_counter[0]),
5462         .oe(VCC),
5463         .outclk(GND),
5464         .outclkena(VCC),
5465         .inclk(GND),
5466         .inclkena(VCC),
5467         .areset(GND),
5468         .sreset(GND)
5469 );
5470 defparam d_hsync_counter_out_0_.operation_mode = "output";
5471 // @6:55
5472   stratix_io d_set_line_counter_out (
5473         .padio(d_set_line_counter),
5474         .datain(vga_driver_unit_vsync_state[1]),
5475         .oe(VCC),
5476         .outclk(GND),
5477         .outclkena(VCC),
5478         .inclk(GND),
5479         .inclkena(VCC),
5480         .areset(GND),
5481         .sreset(GND)
5482 );
5483 defparam d_set_line_counter_out.operation_mode = "output";
5484 // @6:55
5485   stratix_io d_set_column_counter_out (
5486         .padio(d_set_column_counter),
5487         .datain(vga_driver_unit_hsync_state[1]),
5488         .oe(VCC),
5489         .outclk(GND),
5490         .outclkena(VCC),
5491         .inclk(GND),
5492         .inclkena(VCC),
5493         .areset(GND),
5494         .sreset(GND)
5495 );
5496 defparam d_set_column_counter_out.operation_mode = "output";
5497 // @6:54
5498   stratix_io d_line_counter_out_8_ (
5499         .padio(d_line_counter[8]),
5500         .datain(vga_driver_unit_line_counter_sig[8]),
5501         .oe(VCC),
5502         .outclk(GND),
5503         .outclkena(VCC),
5504         .inclk(GND),
5505         .inclkena(VCC),
5506         .areset(GND),
5507         .sreset(GND)
5508 );
5509 defparam d_line_counter_out_8_.operation_mode = "output";
5510 // @6:54
5511   stratix_io d_line_counter_out_7_ (
5512         .padio(d_line_counter[7]),
5513         .datain(vga_driver_unit_line_counter_sig[7]),
5514         .oe(VCC),
5515         .outclk(GND),
5516         .outclkena(VCC),
5517         .inclk(GND),
5518         .inclkena(VCC),
5519         .areset(GND),
5520         .sreset(GND)
5521 );
5522 defparam d_line_counter_out_7_.operation_mode = "output";
5523 // @6:54
5524   stratix_io d_line_counter_out_6_ (
5525         .padio(d_line_counter[6]),
5526         .datain(vga_driver_unit_line_counter_sig[6]),
5527         .oe(VCC),
5528         .outclk(GND),
5529         .outclkena(VCC),
5530         .inclk(GND),
5531         .inclkena(VCC),
5532         .areset(GND),
5533         .sreset(GND)
5534 );
5535 defparam d_line_counter_out_6_.operation_mode = "output";
5536 // @6:54
5537   stratix_io d_line_counter_out_5_ (
5538         .padio(d_line_counter[5]),
5539         .datain(vga_driver_unit_line_counter_sig[5]),
5540         .oe(VCC),
5541         .outclk(GND),
5542         .outclkena(VCC),
5543         .inclk(GND),
5544         .inclkena(VCC),
5545         .areset(GND),
5546         .sreset(GND)
5547 );
5548 defparam d_line_counter_out_5_.operation_mode = "output";
5549 // @6:54
5550   stratix_io d_line_counter_out_4_ (
5551         .padio(d_line_counter[4]),
5552         .datain(vga_driver_unit_line_counter_sig[4]),
5553         .oe(VCC),
5554         .outclk(GND),
5555         .outclkena(VCC),
5556         .inclk(GND),
5557         .inclkena(VCC),
5558         .areset(GND),
5559         .sreset(GND)
5560 );
5561 defparam d_line_counter_out_4_.operation_mode = "output";
5562 // @6:54
5563   stratix_io d_line_counter_out_3_ (
5564         .padio(d_line_counter[3]),
5565         .datain(vga_driver_unit_line_counter_sig[3]),
5566         .oe(VCC),
5567         .outclk(GND),
5568         .outclkena(VCC),
5569         .inclk(GND),
5570         .inclkena(VCC),
5571         .areset(GND),
5572         .sreset(GND)
5573 );
5574 defparam d_line_counter_out_3_.operation_mode = "output";
5575 // @6:54
5576   stratix_io d_line_counter_out_2_ (
5577         .padio(d_line_counter[2]),
5578         .datain(vga_driver_unit_line_counter_sig[2]),
5579         .oe(VCC),
5580         .outclk(GND),
5581         .outclkena(VCC),
5582         .inclk(GND),
5583         .inclkena(VCC),
5584         .areset(GND),
5585         .sreset(GND)
5586 );
5587 defparam d_line_counter_out_2_.operation_mode = "output";
5588 // @6:54
5589   stratix_io d_line_counter_out_1_ (
5590         .padio(d_line_counter[1]),
5591         .datain(vga_driver_unit_line_counter_sig[1]),
5592         .oe(VCC),
5593         .outclk(GND),
5594         .outclkena(VCC),
5595         .inclk(GND),
5596         .inclkena(VCC),
5597         .areset(GND),
5598         .sreset(GND)
5599 );
5600 defparam d_line_counter_out_1_.operation_mode = "output";
5601 // @6:54
5602   stratix_io d_line_counter_out_0_ (
5603         .padio(d_line_counter[0]),
5604         .datain(vga_driver_unit_line_counter_sig[0]),
5605         .oe(VCC),
5606         .outclk(GND),
5607         .outclkena(VCC),
5608         .inclk(GND),
5609         .inclkena(VCC),
5610         .areset(GND),
5611         .sreset(GND)
5612 );
5613 defparam d_line_counter_out_0_.operation_mode = "output";
5614 // @6:53
5615   stratix_io d_column_counter_out_9_ (
5616         .padio(d_column_counter[9]),
5617         .datain(vga_driver_unit_column_counter_sig[9]),
5618         .oe(VCC),
5619         .outclk(GND),
5620         .outclkena(VCC),
5621         .inclk(GND),
5622         .inclkena(VCC),
5623         .areset(GND),
5624         .sreset(GND)
5625 );
5626 defparam d_column_counter_out_9_.operation_mode = "output";
5627 // @6:53
5628   stratix_io d_column_counter_out_8_ (
5629         .padio(d_column_counter[8]),
5630         .datain(vga_driver_unit_column_counter_sig[8]),
5631         .oe(VCC),
5632         .outclk(GND),
5633         .outclkena(VCC),
5634         .inclk(GND),
5635         .inclkena(VCC),
5636         .areset(GND),
5637         .sreset(GND)
5638 );
5639 defparam d_column_counter_out_8_.operation_mode = "output";
5640 // @6:53
5641   stratix_io d_column_counter_out_7_ (
5642         .padio(d_column_counter[7]),
5643         .datain(vga_driver_unit_column_counter_sig[7]),
5644         .oe(VCC),
5645         .outclk(GND),
5646         .outclkena(VCC),
5647         .inclk(GND),
5648         .inclkena(VCC),
5649         .areset(GND),
5650         .sreset(GND)
5651 );
5652 defparam d_column_counter_out_7_.operation_mode = "output";
5653 // @6:53
5654   stratix_io d_column_counter_out_6_ (
5655         .padio(d_column_counter[6]),
5656         .datain(vga_driver_unit_column_counter_sig[6]),
5657         .oe(VCC),
5658         .outclk(GND),
5659         .outclkena(VCC),
5660         .inclk(GND),
5661         .inclkena(VCC),
5662         .areset(GND),
5663         .sreset(GND)
5664 );
5665 defparam d_column_counter_out_6_.operation_mode = "output";
5666 // @6:53
5667   stratix_io d_column_counter_out_5_ (
5668         .padio(d_column_counter[5]),
5669         .datain(vga_driver_unit_column_counter_sig[5]),
5670         .oe(VCC),
5671         .outclk(GND),
5672         .outclkena(VCC),
5673         .inclk(GND),
5674         .inclkena(VCC),
5675         .areset(GND),
5676         .sreset(GND)
5677 );
5678 defparam d_column_counter_out_5_.operation_mode = "output";
5679 // @6:53
5680   stratix_io d_column_counter_out_4_ (
5681         .padio(d_column_counter[4]),
5682         .datain(vga_driver_unit_column_counter_sig[4]),
5683         .oe(VCC),
5684         .outclk(GND),
5685         .outclkena(VCC),
5686         .inclk(GND),
5687         .inclkena(VCC),
5688         .areset(GND),
5689         .sreset(GND)
5690 );
5691 defparam d_column_counter_out_4_.operation_mode = "output";
5692 // @6:53
5693   stratix_io d_column_counter_out_3_ (
5694         .padio(d_column_counter[3]),
5695         .datain(vga_driver_unit_column_counter_sig[3]),
5696         .oe(VCC),
5697         .outclk(GND),
5698         .outclkena(VCC),
5699         .inclk(GND),
5700         .inclkena(VCC),
5701         .areset(GND),
5702         .sreset(GND)
5703 );
5704 defparam d_column_counter_out_3_.operation_mode = "output";
5705 // @6:53
5706   stratix_io d_column_counter_out_2_ (
5707         .padio(d_column_counter[2]),
5708         .datain(vga_driver_unit_column_counter_sig[2]),
5709         .oe(VCC),
5710         .outclk(GND),
5711         .outclkena(VCC),
5712         .inclk(GND),
5713         .inclkena(VCC),
5714         .areset(GND),
5715         .sreset(GND)
5716 );
5717 defparam d_column_counter_out_2_.operation_mode = "output";
5718 // @6:53
5719   stratix_io d_column_counter_out_1_ (
5720         .padio(d_column_counter[1]),
5721         .datain(vga_driver_unit_column_counter_sig[1]),
5722         .oe(VCC),
5723         .outclk(GND),
5724         .outclkena(VCC),
5725         .inclk(GND),
5726         .inclkena(VCC),
5727         .areset(GND),
5728         .sreset(GND)
5729 );
5730 defparam d_column_counter_out_1_.operation_mode = "output";
5731 // @6:53
5732   stratix_io d_column_counter_out_0_ (
5733         .padio(d_column_counter[0]),
5734         .datain(vga_driver_unit_column_counter_sig[0]),
5735         .oe(VCC),
5736         .outclk(GND),
5737         .outclkena(VCC),
5738         .inclk(GND),
5739         .inclkena(VCC),
5740         .areset(GND),
5741         .sreset(GND)
5742 );
5743 defparam d_column_counter_out_0_.operation_mode = "output";
5744 // @6:52
5745   stratix_io d_vsync_out (
5746         .padio(d_vsync),
5747         .datain(vga_driver_unit_v_sync),
5748         .oe(VCC),
5749         .outclk(GND),
5750         .outclkena(VCC),
5751         .inclk(GND),
5752         .inclkena(VCC),
5753         .areset(GND),
5754         .sreset(GND)
5755 );
5756 defparam d_vsync_out.operation_mode = "output";
5757 // @6:52
5758   stratix_io d_hsync_out (
5759         .padio(d_hsync),
5760         .datain(vga_driver_unit_h_sync),
5761         .oe(VCC),
5762         .outclk(GND),
5763         .outclkena(VCC),
5764         .inclk(GND),
5765         .inclkena(VCC),
5766         .areset(GND),
5767         .sreset(GND)
5768 );
5769 defparam d_hsync_out.operation_mode = "output";
5770 // @6:50
5771   stratix_io seven_seg_pin_tri_13_ (
5772         .padio(seven_seg_pin[13]),
5773         .datain(VCC),
5774         .oe(VCC),
5775         .outclk(GND),
5776         .outclkena(VCC),
5777         .inclk(GND),
5778         .inclkena(VCC),
5779         .areset(GND),
5780         .sreset(GND)
5781 );
5782 defparam seven_seg_pin_tri_13_.operation_mode = "output";
5783 // @6:50
5784   stratix_io seven_seg_pin_out_12_ (
5785         .padio(seven_seg_pin[12]),
5786         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5787         .oe(VCC),
5788         .outclk(GND),
5789         .outclkena(VCC),
5790         .inclk(GND),
5791         .inclkena(VCC),
5792         .areset(GND),
5793         .sreset(GND)
5794 );
5795 defparam seven_seg_pin_out_12_.operation_mode = "output";
5796 // @6:50
5797   stratix_io seven_seg_pin_out_11_ (
5798         .padio(seven_seg_pin[11]),
5799         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5800         .oe(VCC),
5801         .outclk(GND),
5802         .outclkena(VCC),
5803         .inclk(GND),
5804         .inclkena(VCC),
5805         .areset(GND),
5806         .sreset(GND)
5807 );
5808 defparam seven_seg_pin_out_11_.operation_mode = "output";
5809 // @6:50
5810   stratix_io seven_seg_pin_out_10_ (
5811         .padio(seven_seg_pin[10]),
5812         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5813         .oe(VCC),
5814         .outclk(GND),
5815         .outclkena(VCC),
5816         .inclk(GND),
5817         .inclkena(VCC),
5818         .areset(GND),
5819         .sreset(GND)
5820 );
5821 defparam seven_seg_pin_out_10_.operation_mode = "output";
5822 // @6:50
5823   stratix_io seven_seg_pin_out_9_ (
5824         .padio(seven_seg_pin[9]),
5825         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5826         .oe(VCC),
5827         .outclk(GND),
5828         .outclkena(VCC),
5829         .inclk(GND),
5830         .inclkena(VCC),
5831         .areset(GND),
5832         .sreset(GND)
5833 );
5834 defparam seven_seg_pin_out_9_.operation_mode = "output";
5835 // @6:50
5836   stratix_io seven_seg_pin_out_8_ (
5837         .padio(seven_seg_pin[8]),
5838         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5839         .oe(VCC),
5840         .outclk(GND),
5841         .outclkena(VCC),
5842         .inclk(GND),
5843         .inclkena(VCC),
5844         .areset(GND),
5845         .sreset(GND)
5846 );
5847 defparam seven_seg_pin_out_8_.operation_mode = "output";
5848 // @6:50
5849   stratix_io seven_seg_pin_out_7_ (
5850         .padio(seven_seg_pin[7]),
5851         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5852         .oe(VCC),
5853         .outclk(GND),
5854         .outclkena(VCC),
5855         .inclk(GND),
5856         .inclkena(VCC),
5857         .areset(GND),
5858         .sreset(GND)
5859 );
5860 defparam seven_seg_pin_out_7_.operation_mode = "output";
5861 // @6:50
5862   stratix_io seven_seg_pin_tri_6_ (
5863         .padio(seven_seg_pin[6]),
5864         .datain(VCC),
5865         .oe(VCC),
5866         .outclk(GND),
5867         .outclkena(VCC),
5868         .inclk(GND),
5869         .inclkena(VCC),
5870         .areset(GND),
5871         .sreset(GND)
5872 );
5873 defparam seven_seg_pin_tri_6_.operation_mode = "output";
5874 // @6:50
5875   stratix_io seven_seg_pin_tri_5_ (
5876         .padio(seven_seg_pin[5]),
5877         .datain(VCC),
5878         .oe(VCC),
5879         .outclk(GND),
5880         .outclkena(VCC),
5881         .inclk(GND),
5882         .inclkena(VCC),
5883         .areset(GND),
5884         .sreset(GND)
5885 );
5886 defparam seven_seg_pin_tri_5_.operation_mode = "output";
5887 // @6:50
5888   stratix_io seven_seg_pin_tri_4_ (
5889         .padio(seven_seg_pin[4]),
5890         .datain(VCC),
5891         .oe(VCC),
5892         .outclk(GND),
5893         .outclkena(VCC),
5894         .inclk(GND),
5895         .inclkena(VCC),
5896         .areset(GND),
5897         .sreset(GND)
5898 );
5899 defparam seven_seg_pin_tri_4_.operation_mode = "output";
5900 // @6:50
5901   stratix_io seven_seg_pin_tri_3_ (
5902         .padio(seven_seg_pin[3]),
5903         .datain(VCC),
5904         .oe(VCC),
5905         .outclk(GND),
5906         .outclkena(VCC),
5907         .inclk(GND),
5908         .inclkena(VCC),
5909         .areset(GND),
5910         .sreset(GND)
5911 );
5912 defparam seven_seg_pin_tri_3_.operation_mode = "output";
5913 // @6:50
5914   stratix_io seven_seg_pin_out_2_ (
5915         .padio(seven_seg_pin[2]),
5916         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5917         .oe(VCC),
5918         .outclk(GND),
5919         .outclkena(VCC),
5920         .inclk(GND),
5921         .inclkena(VCC),
5922         .areset(GND),
5923         .sreset(GND)
5924 );
5925 defparam seven_seg_pin_out_2_.operation_mode = "output";
5926 // @6:50
5927   stratix_io seven_seg_pin_out_1_ (
5928         .padio(seven_seg_pin[1]),
5929         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5930         .oe(VCC),
5931         .outclk(GND),
5932         .outclkena(VCC),
5933         .inclk(GND),
5934         .inclkena(VCC),
5935         .areset(GND),
5936         .sreset(GND)
5937 );
5938 defparam seven_seg_pin_out_1_.operation_mode = "output";
5939 // @6:50
5940   stratix_io seven_seg_pin_tri_0_ (
5941         .padio(seven_seg_pin[0]),
5942         .datain(VCC),
5943         .oe(VCC),
5944         .outclk(GND),
5945         .outclkena(VCC),
5946         .inclk(GND),
5947         .inclkena(VCC),
5948         .areset(GND),
5949         .sreset(GND)
5950 );
5951 defparam seven_seg_pin_tri_0_.operation_mode = "output";
5952 // @6:48
5953   stratix_io vsync_pin_out (
5954         .padio(vsync_pin),
5955         .datain(vga_driver_unit_v_sync),
5956         .oe(VCC),
5957         .outclk(GND),
5958         .outclkena(VCC),
5959         .inclk(GND),
5960         .inclkena(VCC),
5961         .areset(GND),
5962         .sreset(GND)
5963 );
5964 defparam vsync_pin_out.operation_mode = "output";
5965 // @6:47
5966   stratix_io hsync_pin_out (
5967         .padio(hsync_pin),
5968         .datain(vga_driver_unit_h_sync),
5969         .oe(VCC),
5970         .outclk(GND),
5971         .outclkena(VCC),
5972         .inclk(GND),
5973         .inclkena(VCC),
5974         .areset(GND),
5975         .sreset(GND)
5976 );
5977 defparam hsync_pin_out.operation_mode = "output";
5978 // @6:46
5979   stratix_io b1_pin_out (
5980         .padio(b1_pin),
5981         .datain(vga_control_unit_b),
5982         .oe(VCC),
5983         .outclk(GND),
5984         .outclkena(VCC),
5985         .inclk(GND),
5986         .inclkena(VCC),
5987         .areset(GND),
5988         .sreset(GND)
5989 );
5990 defparam b1_pin_out.operation_mode = "output";
5991 // @6:46
5992   stratix_io b0_pin_out (
5993         .padio(b0_pin),
5994         .datain(vga_control_unit_b),
5995         .oe(VCC),
5996         .outclk(GND),
5997         .outclkena(VCC),
5998         .inclk(GND),
5999         .inclkena(VCC),
6000         .areset(GND),
6001         .sreset(GND)
6002 );
6003 defparam b0_pin_out.operation_mode = "output";
6004 // @6:45
6005   stratix_io g2_pin_out (
6006         .padio(g2_pin),
6007         .datain(vga_control_unit_g),
6008         .oe(VCC),
6009         .outclk(GND),
6010         .outclkena(VCC),
6011         .inclk(GND),
6012         .inclkena(VCC),
6013         .areset(GND),
6014         .sreset(GND)
6015 );
6016 defparam g2_pin_out.operation_mode = "output";
6017 // @6:45
6018   stratix_io g1_pin_out (
6019         .padio(g1_pin),
6020         .datain(vga_control_unit_g),
6021         .oe(VCC),
6022         .outclk(GND),
6023         .outclkena(VCC),
6024         .inclk(GND),
6025         .inclkena(VCC),
6026         .areset(GND),
6027         .sreset(GND)
6028 );
6029 defparam g1_pin_out.operation_mode = "output";
6030 // @6:45
6031   stratix_io g0_pin_out (
6032         .padio(g0_pin),
6033         .datain(vga_control_unit_g),
6034         .oe(VCC),
6035         .outclk(GND),
6036         .outclkena(VCC),
6037         .inclk(GND),
6038         .inclkena(VCC),
6039         .areset(GND),
6040         .sreset(GND)
6041 );
6042 defparam g0_pin_out.operation_mode = "output";
6043 // @6:44
6044   stratix_io r2_pin_out (
6045         .padio(r2_pin),
6046         .datain(vga_control_unit_r),
6047         .oe(VCC),
6048         .outclk(GND),
6049         .outclkena(VCC),
6050         .inclk(GND),
6051         .inclkena(VCC),
6052         .areset(GND),
6053         .sreset(GND)
6054 );
6055 defparam r2_pin_out.operation_mode = "output";
6056 // @6:44
6057   stratix_io r1_pin_out (
6058         .padio(r1_pin),
6059         .datain(vga_control_unit_r),
6060         .oe(VCC),
6061         .outclk(GND),
6062         .outclkena(VCC),
6063         .inclk(GND),
6064         .inclkena(VCC),
6065         .areset(GND),
6066         .sreset(GND)
6067 );
6068 defparam r1_pin_out.operation_mode = "output";
6069 // @6:44
6070   stratix_io r0_pin_out (
6071         .padio(r0_pin),
6072         .datain(vga_control_unit_r),
6073         .oe(VCC),
6074         .outclk(GND),
6075         .outclkena(VCC),
6076         .inclk(GND),
6077         .inclkena(VCC),
6078         .areset(GND),
6079         .sreset(GND)
6080 );
6081 defparam r0_pin_out.operation_mode = "output";
6082 //@6:41
6083 // @10:161
6084   vga_driver vga_driver_unit (
6085         .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
6086         .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
6087         .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
6088         .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
6089         .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
6090         .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
6091         .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
6092         .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
6093         .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
6094         .dly_counter_1(dly_counter[1]),
6095         .dly_counter_0(dly_counter[0]),
6096         .vsync_state_2(vga_driver_unit_vsync_state[2]),
6097         .vsync_state_5(vga_driver_unit_vsync_state[5]),
6098         .vsync_state_3(vga_driver_unit_vsync_state[3]),
6099         .vsync_state_6(vga_driver_unit_vsync_state[6]),
6100         .vsync_state_4(vga_driver_unit_vsync_state[4]),
6101         .vsync_state_1(vga_driver_unit_vsync_state[1]),
6102         .vsync_state_0(vga_driver_unit_vsync_state[0]),
6103         .hsync_state_2(vga_driver_unit_hsync_state[2]),
6104         .hsync_state_4(vga_driver_unit_hsync_state[4]),
6105         .hsync_state_0(vga_driver_unit_hsync_state[0]),
6106         .hsync_state_5(vga_driver_unit_hsync_state[5]),
6107         .hsync_state_1(vga_driver_unit_hsync_state[1]),
6108         .hsync_state_3(vga_driver_unit_hsync_state[3]),
6109         .hsync_state_6(vga_driver_unit_hsync_state[6]),
6110         .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
6111         .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
6112         .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
6113         .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
6114         .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
6115         .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
6116         .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
6117         .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
6118         .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
6119         .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
6120         .vsync_counter_9(vga_driver_unit_vsync_counter[9]),
6121         .vsync_counter_8(vga_driver_unit_vsync_counter[8]),
6122         .vsync_counter_7(vga_driver_unit_vsync_counter[7]),
6123         .vsync_counter_6(vga_driver_unit_vsync_counter[6]),
6124         .vsync_counter_5(vga_driver_unit_vsync_counter[5]),
6125         .vsync_counter_4(vga_driver_unit_vsync_counter[4]),
6126         .vsync_counter_3(vga_driver_unit_vsync_counter[3]),
6127         .vsync_counter_2(vga_driver_unit_vsync_counter[2]),
6128         .vsync_counter_1(vga_driver_unit_vsync_counter[1]),
6129         .vsync_counter_0(vga_driver_unit_vsync_counter[0]),
6130         .hsync_counter_9(vga_driver_unit_hsync_counter[9]),
6131         .hsync_counter_8(vga_driver_unit_hsync_counter[8]),
6132         .hsync_counter_7(vga_driver_unit_hsync_counter[7]),
6133         .hsync_counter_6(vga_driver_unit_hsync_counter[6]),
6134         .hsync_counter_5(vga_driver_unit_hsync_counter[5]),
6135         .hsync_counter_4(vga_driver_unit_hsync_counter[4]),
6136         .hsync_counter_3(vga_driver_unit_hsync_counter[3]),
6137         .hsync_counter_2(vga_driver_unit_hsync_counter[2]),
6138         .hsync_counter_1(vga_driver_unit_hsync_counter[1]),
6139         .hsync_counter_0(vga_driver_unit_hsync_counter[0]),
6140         .d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter),
6141         .v_sync(vga_driver_unit_v_sync),
6142         .h_sync(vga_driver_unit_h_sync),
6143         .h_enable_sig(vga_driver_unit_h_enable_sig),
6144         .v_enable_sig(vga_driver_unit_v_enable_sig),
6145         .reset_pin_c(reset_pin_c),
6146         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
6147         .d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter),
6148         .clk_pin_c(G_33)
6149 );
6150 // @10:186
6151   vga_control vga_control_unit (
6152         .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
6153         .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
6154         .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
6155         .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
6156         .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
6157         .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
6158         .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
6159         .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
6160         .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
6161         .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
6162         .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
6163         .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
6164         .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
6165         .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
6166         .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
6167         .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
6168         .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
6169         .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
6170         .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
6171         .toggle_counter_sig_0(vga_control_unit_toggle_counter_sig[0]),
6172         .toggle_counter_sig_1(vga_control_unit_toggle_counter_sig[1]),
6173         .toggle_counter_sig_2(vga_control_unit_toggle_counter_sig[2]),
6174         .toggle_counter_sig_3(vga_control_unit_toggle_counter_sig[3]),
6175         .toggle_counter_sig_4(vga_control_unit_toggle_counter_sig[4]),
6176         .toggle_counter_sig_5(vga_control_unit_toggle_counter_sig[5]),
6177         .toggle_counter_sig_6(vga_control_unit_toggle_counter_sig[6]),
6178         .toggle_counter_sig_7(vga_control_unit_toggle_counter_sig[7]),
6179         .toggle_counter_sig_8(vga_control_unit_toggle_counter_sig[8]),
6180         .toggle_counter_sig_9(vga_control_unit_toggle_counter_sig[9]),
6181         .toggle_counter_sig_10(vga_control_unit_toggle_counter_sig[10]),
6182         .toggle_counter_sig_11(vga_control_unit_toggle_counter_sig[11]),
6183         .toggle_counter_sig_12(vga_control_unit_toggle_counter_sig[12]),
6184         .toggle_counter_sig_13(vga_control_unit_toggle_counter_sig[13]),
6185         .toggle_counter_sig_14(vga_control_unit_toggle_counter_sig[14]),
6186         .toggle_counter_sig_15(vga_control_unit_toggle_counter_sig[15]),
6187         .toggle_counter_sig_16(vga_control_unit_toggle_counter_sig[16]),
6188         .toggle_counter_sig_17(vga_control_unit_toggle_counter_sig[17]),
6189         .toggle_counter_sig_18(vga_control_unit_toggle_counter_sig[18]),
6190         .toggle_counter_sig_19(vga_control_unit_toggle_counter_sig[19]),
6191         .toggle_counter_sig_20(vga_control_unit_toggle_counter_sig[20]),
6192         .toggle_counter_sig_21(vga_control_unit_toggle_counter_sig[21]),
6193         .toggle_counter_sig_22(vga_control_unit_toggle_counter_sig[22]),
6194         .toggle_counter_sig_23(vga_control_unit_toggle_counter_sig[23]),
6195         .toggle_counter_sig_24(vga_control_unit_toggle_counter_sig[24]),
6196         .h_enable_sig(vga_driver_unit_h_enable_sig),
6197         .g(vga_control_unit_g),
6198         .b(vga_control_unit_b),
6199         .v_enable_sig(vga_driver_unit_v_enable_sig),
6200         .r(vga_control_unit_r),
6201         .toggle_sig(vga_control_unit_toggle_sig),
6202         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
6203         .clk_pin_c(G_33)
6204 );
6205 endmodule /* vga */
6206