bsp2/Designflow/syn/rev_1/vga.tcl

   1 # Run with quartus_sh -t <x_cons.tcl>
   2
   3 # Global assignments
   4 set_global_assignment -name TOP_LEVEL_ENTITY "|vga"
   5 set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL
   6 set_global_assignment -name FAMILY "STRATIX"
   7 set_global_assignment -name DEVICE "EP1S25F672C6"
   8 set_global_assignment -section_id vga -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "SYNPLIFY"
   9 set_global_assignment -section_id eda_design_synthesis -name EDA_USE_LMF synplcty.lmf
  10 set_global_assignment -name TAO_FILE "myresults.tao"
  11 set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000"
  12 set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
  13 set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF"
  14 set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF"
  15 set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF"
  16 # set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
  17 #set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY"
  18 set_global_assignment -name ENABLE_CLOCK_LATENCY "ON"
  19
  20 # Clock assignments
  21
  22 create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin
  23
  24
  25 # False path constraints
  26
  27 # Multicycle constraints
  28
  29 # Path delay constraints
  30 if {[file exists ___quartus_options.tcl]} {
  31         source ___quartus_options.tcl
  32 }
  33
  34
  35 # Incremental Compilation
  36     # this will synchronize any existing partitions declared in Synpilfy
  37     # with partitions existing in Quartus. If partitions exist,
  38     # incremental compilation will be enabled
  39     variable compile_point_list
  40     set compile_point_list [list]
  41     source "/opt/synplify/fpga_c200906/lib/altera/qic.tcl"