bsp2/Designflow/syn/rev_1/vga.srr

   1 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   2 #install: /opt/synplify/fpga_c200906
   3 #OS: Linux
   4 #Hostname: ti12
   5
   6 #Implementation: rev_1
   7
   8 #Wed Oct 21 17:26:30 2009
   9
  10 $ Start of Compile
  11 #Wed Oct 21 17:26:30 2009
  12
  13 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  14 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  15
  16 @N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
  17 @N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
  18 VHDL syntax check successful!
  19
  20 Compiler output is up to date.  No re-compile necessary
  21
  22 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
  23 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  24 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  25 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
  26 Post processing for work.vga_control.behav
  27 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
  28 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  29 @N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  30 Post processing for work.vga_driver.behav
  31 @N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
  32 Post processing for work.board_driver.behav
  33 Post processing for work.vga.behav
  34 @END
  35 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  36 # Wed Oct 21 17:26:30 2009
  37
  38 ###########################################################]
  39 Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
  40 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  41 Product Version C-2009.06
  42 @N: MF249 |Running in 32-bit mode.
  43 @N: MF257 |Gated clock conversion enabled
  44 @N|Running in logic synthesis mode without enhanced optimization
  45
  46 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
  47 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
  48
  49 Available hyper_sources - for debug and ip models
  50         None Found
  51
  52 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  53
  54 @N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
  55 @N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
  56 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  57
  58 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  59
  60 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  61
  62
  63
  64 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
  65
  66 ======================================================================================
  67                                 Instance:Pin        Generated Clock Optimization Status
  68 ======================================================================================
  69
  70
  71 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
  72
  73 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  74
  75 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  76
  77 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  78
  79 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  80
  81 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  82
  83 Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  84
  85 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  86
  87 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  88
  89 Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
  90
  91 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
  92
  93 Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
  94
  95
  96 Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
  97 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
  98
  99 Writing Verilog Netlist and constraint files
 100 Writing .vqm output for Quartus
 101 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
 102 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 103
 104 Writing VHDL Simulation files
 105 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 106
 107 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 108
 109 @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
 110 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 111
 112 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 113
 114 @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
 115 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 116
 117 Found clock vga|clk_pin with period 39.72ns
 118
 119
 120 ##### START OF TIMING REPORT #####[
 121 # Timing Report written on Wed Oct 21 17:26:36 2009
 122 #
 123
 124
 125 Top view:               vga
 126 Requested Frequency:    25.2 MHz
 127 Wire load mode:         top
 128 Paths requested:        5
 129 Constraint File(s):
 130 @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 131
 132 @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
 133
 134
 135
 136 Performance Summary
 137 *******************
 138
 139
 140 Worst slack in design: 34.458
 141
 142                    Requested     Estimated     Requested     Estimated                Clock        Clock
 143 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
 144 ----------------------------------------------------------------------------------------------------------------------
 145 vga|clk_pin        25.2 MHz      190.0 MHz     39.722        5.264         34.458     inferred     Inferred_clkgroup_0
 146 ======================================================================================================================
 147
 148
 149
 150
 151
 152 Clock Relationships
 153 *******************
 154
 155 Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
 156 -----------------------------------------------------------------------------------------------------------------
 157 Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
 158 -----------------------------------------------------------------------------------------------------------------
 159 vga|clk_pin  vga|clk_pin  |  39.722      34.458  |  No paths    -      |  No paths    -      |  No paths    -
 160 =================================================================================================================
 161  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 162        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 163
 164
 165
 166 Interface Information
 167 *********************
 168
 169                 No IO constraint found
 170
 171
 172
 173 ====================================
 174 Detailed Report for Clock: vga|clk_pin
 175 ====================================
 176
 177
 178
 179 Starting Points with Worst Slack
 180 ********************************
 181
 182                                            Starting                                                                 Arrival
 183 Instance                                   Reference       Type                 Pin        Net                      Time        Slack
 184                                            Clock
 185 --------------------------------------------------------------------------------------------------------------------------------------
 186 vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_6     0.176       34.458
 187 dly_counter[0]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]           0.176       34.465
 188 dly_counter[1]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[1]           0.176       34.584
 189 vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_5     0.176       34.585
 190 vga_driver_unit.vsync_counter[6]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6          0.176       34.836
 191 vga_driver_unit.vsync_counter[7]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7          0.176       34.865
 192 vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_8     0.176       34.921
 193 vga_driver_unit.vsync_counter[3]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3          0.176       34.992
 194 vga_driver_unit.vsync_counter[8]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8          0.176       34.992
 195 vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_9     0.176       35.048
 196 ======================================================================================================================================
 197
 198
 199 Ending Points with Worst Slack
 200 ******************************
 201
 202                                            Starting                                                              Required
 203 Instance                                   Reference       Type                 Pin      Net                     Time         Slack
 204                                            Clock
 205 ------------------------------------------------------------------------------------------------------------------------------------
 206 vga_control_unit.toggle_counter_sig[0]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 207 vga_control_unit.toggle_counter_sig[1]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 208 vga_control_unit.toggle_counter_sig[2]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 209 vga_control_unit.toggle_counter_sig[3]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 210 vga_control_unit.toggle_counter_sig[4]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 211 vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 212 vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 213 vga_control_unit.toggle_counter_sig[7]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 214 vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 215 vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 216 ====================================================================================================================================
 217
 218
 219
 220 Worst Path Information
 221 ***********************
 222
 223
 224 Path information for path number 1:
 225     Requested Period:                        39.722
 226     - Setup time:                            0.792
 227     + Clock delay at ending point:           0.000 (ideal)
 228     = Required time:                         38.930
 229
 230     - Propagation time:                      4.472
 231     - Clock delay at starting point:         0.000 (ideal)
 232     = Slack (critical) :                     34.458
 233
 234     Number of logic level(s):                6
 235     Starting point:                          vga_control_unit.toggle_counter_sig[6] / regout
 236     Ending point:                            vga_control_unit.toggle_counter_sig[0] / sclr
 237     The start point is clocked by            vga|clk_pin [rising] on pin clk
 238     The end   point is clocked by            vga|clk_pin [rising] on pin clk
 239
 240 Instance / Net                                                                     Pin         Pin               Arrival     No. of
 241 Name                                                          Type                 Name        Dir     Delay     Time        Fan Out(s)
 242 ---------------------------------------------------------------------------------------------------------------------------------------
 243 vga_control_unit.toggle_counter_sig[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -
 244 toggle_counter_sig_6                                          Net                  -           -       1.000     -           4
 245 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        dataa       In      -         1.176       -
 246 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        combout     Out     0.459     1.635       -
 247 un1_toggle_counter_siglt6                                     Net                  -           -       0.376     -           1
 248 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        datad       In      -         2.011       -
 249 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        combout     Out     0.087     2.098       -
 250 un1_toggle_counter_siglto9                                    Net                  -           -       0.376     -           1
 251 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        datad       In      -         2.474       -
 252 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        combout     Out     0.087     2.561       -
 253 un1_toggle_counter_siglto12                                   Net                  -           -       0.376     -           1
 254 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        datad       In      -         2.938       -
 255 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        combout     Out     0.087     3.025       -
 256 un1_toggle_counter_siglto15                                   Net                  -           -       0.376     -           1
 257 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        datad       In      -         3.401       -
 258 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        combout     Out     0.087     3.488       -
 259 un1_toggle_counter_siglto18                                   Net                  -           -       0.376     -           1
 260 vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        datad       In      -         3.864       -
 261 vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        combout     Out     0.087     3.951       -
 262 toggle_sig_0_0_0_g1                                           Net                  -           -       0.521     -           22(6)
 263 vga_control_unit.toggle_counter_sig[0]                        stratix_lcell_ff     sclr        In      -         4.472       -
 264 =======================================================================================================================================
 265 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
 266 Fanout format: logic fanout (physical fanout)
 267 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 268 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
 269
 270
 271
 272 ##### END OF TIMING REPORT #####]
 273
 274 ##### START OF AREA REPORT #####[
 275 Design view:work.vga(behav)
 276 Selecting part EP1S25F672C6
 277 @N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 278
 279 I/O ATOMs:       117
 280
 281 Total LUTs:  179 of 25660 ( 0%)
 282 Logic resources:  181 ATOMs of 25660 ( 0%)
 283
 284 Number of I/O registers
 285                         Output DDRs   :0
 286
 287 ATOM count by mode:
 288   normal:       128
 289   arithmetic:   53
 290
 291 DSP Blocks:     0  (0 nine-bit DSP elements).
 292 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
 293 ShiftTap:       0  (0 registers)
 294 MRAM:           0  (0% of 2)
 295 M4Ks:           0  (0% of 138)
 296 M512s:          0  (0% of 224)
 297 Total ESB:      0 bits
 298
 299 ATOMs using regout pin: 88
 300   also using enable pin: 12
 301   also using combout pin: 1
 302 ATOMs using combout pin: 91
 303 Number of Inputs on ATOMs: 760
 304 Number of Nets:   54954
 305
 306 ##### END OF AREA REPORT #####]
 307
 308 Mapper successful!
 309 Process took 0h:00m:05s realtime, 0h:00m:04s cputime
 310 # Wed Oct 21 17:26:36 2009
 311
 312 ###########################################################]