bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm

   1 <html><body><samp><pre>
   2 <!@TC:1256138796>
   3 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   4 #install: /opt/synplify/fpga_c200906
   5 #OS: Linux
   6 #Hostname: ti12
   7
   8 #Implementation: rev_1
   9
  10 #Wed Oct 21 17:26:30 2009
  11
  12 <a name=compilerReport1>$ Start of Compile</a>
  13 #Wed Oct 21 17:26:30 2009
  14
  15 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  16 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  17
  18 @N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synplify/fpga_c200906/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1256138796> | Setting time resolution to ns
  19 @N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd:38:7:38:10:@N::@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256138796> | Top entity is set to vga.
  20 VHDL syntax check successful!
  21
  22 Compiler output is up to date.  No re-compile necessary
  23
  24 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd:38:7:38:10:@N:CD630:@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256138796> | Synthesizing work.vga.behav
  25 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1256138796> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
  26 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1256138796> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
  27 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd:37:7:37:18:@N:CD630:@XP_MSG">vga_control_ent.vhd(37)</a><!@TM:1256138796> | Synthesizing work.vga_control.behav
  28 Post processing for work.vga_control.behav
  29 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd:37:7:37:17:@N:CD630:@XP_MSG">vga_driver_ent.vhd(37)</a><!@TM:1256138796> | Synthesizing work.vga_driver.behav
  30 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1256138796> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
  31 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1256138796> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
  32 Post processing for work.vga_driver.behav
  33 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd:36:7:36:19:@N:CD630:@XP_MSG">board_driver_ent.vhd(36)</a><!@TM:1256138796> | Synthesizing work.board_driver.behav
  34 Post processing for work.board_driver.behav
  35 Post processing for work.vga.behav
  36 @END
  37 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  38 # Wed Oct 21 17:26:30 2009
  39
  40 ###########################################################]
  41 <a name=mapperReport2>Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53</a>
  42 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  43 Product Version C-2009.06
  44 @N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1256138796> | Running in 32-bit mode.
  45 @N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1256138796> | Gated clock conversion enabled
  46 @N: : <!@TM:1256138796> | Running in logic synthesis mode without enhanced optimization
  47
  48 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
  49 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
  50
  51 Available hyper_sources - for debug and ip models
  52         None Found
  53
  54 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  55
  56 @N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd:267:4:267:6:@N::@XP_MSG">vga_driver_arc.vhd(267)</a><!@TM:1256138796> | Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
  57 @N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd:158:4:158:6:@N::@XP_MSG">vga_driver_arc.vhd(158)</a><!@TM:1256138796> | Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
  58 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  59
  60 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  61
  62 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  63
  64
  65
  66 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
  67
  68 ======================================================================================
  69                                 Instance:Pin        Generated Clock Optimization Status
  70 ======================================================================================
  71
  72
  73 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
  74
  75 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  76
  77 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  78
  79 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  80
  81 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  82
  83 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  84
  85 Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  86
  87 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  88
  89 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  90
  91 Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
  92
  93 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
  94
  95 Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
  96
  97
  98 Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
  99 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 100
 101 Writing Verilog Netlist and constraint files
 102 Writing .vqm output for Quartus
 103 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
 104 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 105
 106 Writing VHDL Simulation files
 107 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 108
 109 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 110
 111 @N:<a href="@N:MF276:@XP_HELP">MF276</a> : <!@TM:1256138796> | Gated clock conversion enabled, but no gated clocks found in design
 112 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 113
 114 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 115
 116 @N:<a href="@N:MF333:@XP_HELP">MF333</a> : <!@TM:1256138796> | Generated clock conversion enabled, but no generated clocks found in design
 117 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
 118
 119 Found clock vga|clk_pin with period 39.72ns
 120
 121
 122 <a name=timingReport3>##### START OF TIMING REPORT #####[</a>
 123 # Timing Report written on Wed Oct 21 17:26:36 2009
 124 #
 125
 126
 127 Top view:               vga
 128 Requested Frequency:    25.2 MHz
 129 Wire load mode:         top
 130 Paths requested:        5
 131 Constraint File(s):
 132 @N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1256138796> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 133
 134 @N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1256138796> | Clock constraints cover only FF-to-FF paths associated with the clock..
 135
 136
 137
 138 <a name=performanceSummary4>Performance Summary </a>
 139 *******************
 140
 141
 142 Worst slack in design: 34.458
 143
 144                    Requested     Estimated     Requested     Estimated                Clock        Clock
 145 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
 146 ----------------------------------------------------------------------------------------------------------------------
 147 vga|clk_pin        25.2 MHz      190.0 MHz     39.722        5.264         34.458     inferred     Inferred_clkgroup_0
 148 ======================================================================================================================
 149
 150
 151
 152
 153
 154 <a name=clockRelationships5>Clock Relationships</a>
 155 *******************
 156
 157 Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
 158 -----------------------------------------------------------------------------------------------------------------
 159 Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
 160 -----------------------------------------------------------------------------------------------------------------
 161 vga|clk_pin  vga|clk_pin  |  39.722      34.458  |  No paths    -      |  No paths    -      |  No paths    -
 162 =================================================================================================================
 163  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 164        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 165
 166
 167
 168 <a name=interfaceInfo6>Interface Information </a>
 169 *********************
 170
 171                 No IO constraint found
 172
 173
 174
 175 ====================================
 176 <a name=clockReport7>Detailed Report for Clock: vga|clk_pin</a>
 177 ====================================
 178
 179
 180
 181 <a name=startingSlack8>Starting Points with Worst Slack</a>
 182 ********************************
 183
 184                                            Starting                                                                 Arrival
 185 Instance                                   Reference       Type                 Pin        Net                      Time        Slack
 186                                            Clock
 187 --------------------------------------------------------------------------------------------------------------------------------------
 188 vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_6     0.176       34.458
 189 dly_counter[0]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]           0.176       34.465
 190 dly_counter[1]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[1]           0.176       34.584
 191 vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_5     0.176       34.585
 192 vga_driver_unit.vsync_counter[6]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6          0.176       34.836
 193 vga_driver_unit.vsync_counter[7]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7          0.176       34.865
 194 vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_8     0.176       34.921
 195 vga_driver_unit.vsync_counter[3]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3          0.176       34.992
 196 vga_driver_unit.vsync_counter[8]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8          0.176       34.992
 197 vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_9     0.176       35.048
 198 ======================================================================================================================================
 199
 200
 201 <a name=endingSlack9>Ending Points with Worst Slack</a>
 202 ******************************
 203
 204                                            Starting                                                              Required
 205 Instance                                   Reference       Type                 Pin      Net                     Time         Slack
 206                                            Clock
 207 ------------------------------------------------------------------------------------------------------------------------------------
 208 vga_control_unit.toggle_counter_sig[0]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 209 vga_control_unit.toggle_counter_sig[1]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 210 vga_control_unit.toggle_counter_sig[2]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 211 vga_control_unit.toggle_counter_sig[3]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 212 vga_control_unit.toggle_counter_sig[4]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 213 vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 214 vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 215 vga_control_unit.toggle_counter_sig[7]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 216 vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 217 vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
 218 ====================================================================================================================================
 219
 220
 221
 222 <a name=worstPaths10>Worst Path Information</a>
 223 <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srr:fp:13902:16758:@XP_NAMES_GATE">View Worst Path in Analyst</a>
 224 ***********************
 225
 226
 227 Path information for path number 1:
 228     Requested Period:                        39.722
 229     - Setup time:                            0.792
 230     + Clock delay at ending point:           0.000 (ideal)
 231     = Required time:                         38.930
 232
 233     - Propagation time:                      4.472
 234     - Clock delay at starting point:         0.000 (ideal)
 235     = Slack (critical) :                     34.458
 236
 237     Number of logic level(s):                6
 238     Starting point:                          vga_control_unit.toggle_counter_sig[6] / regout
 239     Ending point:                            vga_control_unit.toggle_counter_sig[0] / sclr
 240     The start point is clocked by            vga|clk_pin [rising] on pin clk
 241     The end   point is clocked by            vga|clk_pin [rising] on pin clk
 242
 243 Instance / Net                                                                     Pin         Pin               Arrival     No. of
 244 Name                                                          Type                 Name        Dir     Delay     Time        Fan Out(s)
 245 ---------------------------------------------------------------------------------------------------------------------------------------
 246 vga_control_unit.toggle_counter_sig[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -
 247 toggle_counter_sig_6                                          Net                  -           -       1.000     -           4
 248 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        dataa       In      -         1.176       -
 249 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        combout     Out     0.459     1.635       -
 250 un1_toggle_counter_siglt6                                     Net                  -           -       0.376     -           1
 251 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        datad       In      -         2.011       -
 252 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        combout     Out     0.087     2.098       -
 253 un1_toggle_counter_siglto9                                    Net                  -           -       0.376     -           1
 254 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        datad       In      -         2.474       -
 255 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        combout     Out     0.087     2.561       -
 256 un1_toggle_counter_siglto12                                   Net                  -           -       0.376     -           1
 257 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        datad       In      -         2.938       -
 258 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        combout     Out     0.087     3.025       -
 259 un1_toggle_counter_siglto15                                   Net                  -           -       0.376     -           1
 260 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        datad       In      -         3.401       -
 261 vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        combout     Out     0.087     3.488       -
 262 un1_toggle_counter_siglto18                                   Net                  -           -       0.376     -           1
 263 vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        datad       In      -         3.864       -
 264 vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        combout     Out     0.087     3.951       -
 265 toggle_sig_0_0_0_g1                                           Net                  -           -       0.521     -           22(6)
 266 vga_control_unit.toggle_counter_sig[0]                        stratix_lcell_ff     sclr        In      -         4.472       -
 267 =======================================================================================================================================
 268 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
 269 Fanout format: logic fanout (physical fanout)
 270 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 271 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
 272
 273
 274
 275 ##### END OF TIMING REPORT #####]
 276
 277 <a name=areaReport11>##### START OF AREA REPORT #####[</a>
 278 Design view:work.vga(behav)
 279 Selecting part EP1S25F672C6
 280 @N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1256138796> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 281
 282 I/O ATOMs:       117
 283
 284 Total LUTs:  179 of 25660 ( 0%)
 285 Logic resources:  181 ATOMs of 25660 ( 0%)
 286
 287 Number of I/O registers
 288                         Output DDRs   :0
 289
 290 ATOM count by mode:
 291   normal:       128
 292   arithmetic:   53
 293
 294 DSP Blocks:     0  (0 nine-bit DSP elements).
 295 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
 296 ShiftTap:       0  (0 registers)
 297 MRAM:           0  (0% of 2)
 298 M4Ks:           0  (0% of 138)
 299 M512s:          0  (0% of 224)
 300 Total ESB:      0 bits
 301
 302 ATOMs using regout pin: 88
 303   also using enable pin: 12
 304   also using combout pin: 1
 305 ATOMs using combout pin: 91
 306 Number of Inputs on ATOMs: 760
 307 Number of Nets:   54954
 308
 309 ##### END OF AREA REPORT #####]
 310
 311 Mapper successful!
 312 Process took 0h:00m:05s realtime, 0h:00m:04s cputime
 313 # Wed Oct 21 17:26:36 2009
 314
 315 ###########################################################]