bsp2/Designflow/src/vga_pre_tb.vhd

   1 -------------------------------------------------------------------------------
   2 -- Title      : vga testbench
   3 -- Project    :
   4 -------------------------------------------------------------------------------
   5 -- File       : vga_tb.vhd
   6 -- Author     : Thomas Handl
   7 -- Company    : TU Wien
   8 -- Created    : 2004-04-07
   9 -- Last update: 2006-09-29
  10 -- Platform   :
  11 -------------------------------------------------------------------------------
  12 -- Description:
  13 -------------------------------------------------------------------------------
  14 -- Copyright (c) 2004 TU Wien
  15 -------------------------------------------------------------------------------
  16 -- Revisions  :
  17 -- Date        Version  Author  Description
  18 -- 2004-04-07  1.0      handl   Created
  19 -------------------------------------------------------------------------------
  20
  21
  22 -------------------------------------------------------------------------------
  23 -- LIBRARIES
  24 -------------------------------------------------------------------------------
  25
  26 library IEEE;
  27 use IEEE.std_logic_1164.all;
  28 use IEEE.std_logic_unsigned.all;
  29 use IEEE.std_logic_arith.all;
  30
  31 use work.vga_pak.all;
  32
  33
  34 -------------------------------------------------------------------------------
  35 -- ENTITY
  36 -------------------------------------------------------------------------------
  37 entity vga_pre_tb is
  38
  39 end vga_pre_tb;
  40
  41
  42 -------------------------------------------------------------------------------
  43 -- ARCHITECTURE
  44 -------------------------------------------------------------------------------
  45 architecture structure of vga_pre_tb is
  46
  47   constant cc : time := 39.7 ns;        -- test clock period
  48
  49   component vga
  50     port (
  51       clk_pin                                  : in  std_logic;
  52       reset_pin                                : in  std_logic;
  53       r0_pin, r1_pin, r2_pin                   : out std_logic;
  54       g0_pin, g1_pin, g2_pin                   : out std_logic;
  55       b0_pin, b1_pin                           : out std_logic;
  56       hsync_pin                                : out std_logic;
  57       vsync_pin                                : out std_logic;
  58       seven_seg_pin                            : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
  59       d_hsync, d_vsync                         : out std_logic;
  60       d_column_counter                         : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  61       d_line_counter                           : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  62       d_set_column_counter, d_set_line_counter : out std_logic;
  63       d_hsync_counter                          : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  64       d_vsync_counter                          : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  65       d_set_hsync_counter, d_set_vsync_counter : out std_logic;
  66       d_h_enable                               : out std_logic;
  67       d_v_enable                               : out std_logic;
  68       d_r, d_g, d_b                            : out std_logic;
  69       d_hsync_state                            : out std_logic_vector(0 to 6);
  70       d_vsync_state                            : out std_logic_vector(0 to 6);
  71       d_state_clk                              : out std_logic;
  72       d_toggle                                 : out std_logic;
  73       d_toggle_counter                         : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0));
  74   end component;
  75
  76   signal clk_pin                                  : std_logic;
  77   signal reset_pin                                : std_logic;
  78   signal r0_pin, r1_pin, r2_pin                   : std_logic;
  79   signal g0_pin, g1_pin, g2_pin                   : std_logic;
  80   signal b0_pin, b1_pin                           : std_logic;
  81   signal hsync_pin                                : std_logic;
  82   signal vsync_pin                                : std_logic;
  83   signal seven_seg_pin                            : std_logic_vector(2*SEG_WIDTH-1 downto 0);
  84   signal d_hsync, d_vsync                         : std_logic;
  85   signal d_column_counter                         : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  86   signal d_line_counter                           : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  87   signal d_set_column_counter, d_set_line_counter : std_logic;
  88   signal d_hsync_counter                          : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  89   signal d_vsync_counter                          : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  90   signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
  91   signal d_h_enable                               : std_logic;
  92   signal d_v_enable                               : std_logic;
  93   signal d_r, d_g, d_b                            : std_logic;
  94   signal d_hsync_state                            : std_logic_vector(0 to 6);
  95   signal d_vsync_state                            : std_logic_vector(0 to 6);
  96   signal d_state_clk                              : std_logic;
  97   signal d_toggle                                 : std_logic;
  98   signal d_toggle_counter                         : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);
  99   signal clk                                      : std_logic;
 100
 101 begin
 102
 103   vga_unit: vga
 104     port map (
 105       clk_pin              => clk_pin,
 106       reset_pin            => reset_pin,
 107       r0_pin               => r0_pin,
 108       r1_pin               => r1_pin,
 109       r2_pin               => r2_pin,
 110       g0_pin               => g0_pin,
 111       g1_pin               => g1_pin,
 112       g2_pin               => g2_pin,
 113       b0_pin               => b0_pin,
 114       b1_pin               => b1_pin,
 115       hsync_pin            => hsync_pin,
 116       vsync_pin            => vsync_pin,
 117       seven_seg_pin        => seven_seg_pin,
 118       d_hsync              => d_hsync,
 119       d_vsync              => d_vsync,
 120       d_column_counter     => d_column_counter,
 121       d_line_counter       => d_line_counter,
 122       d_set_column_counter => d_set_column_counter,
 123       d_set_line_counter   => d_set_line_counter,
 124       d_hsync_counter      => d_hsync_counter,
 125       d_vsync_counter      => d_vsync_counter,
 126       d_set_hsync_counter  => d_set_hsync_counter,
 127       d_set_vsync_counter  => d_set_vsync_counter,
 128       d_h_enable           => d_h_enable,
 129       d_v_enable           => d_v_enable,
 130       d_r                  => d_r,
 131       d_g                  => d_g,
 132       d_b                  => d_b,
 133       d_hsync_state        => d_hsync_state,
 134       d_vsync_state        => d_vsync_state,
 135       d_state_clk          => d_state_clk,
 136       d_toggle             => d_toggle,
 137       d_toggle_counter     => d_toggle_counter);
 138
 139
 140 -------------------------------------------------------------------------------
 141 -- generate simulation clock
 142 -------------------------------------------------------------------------------
 143   CLKGEN : process
 144   begin
 145     clk <= '1';
 146     wait for cc/2;
 147     clk <= '0';
 148     wait for cc/2;
 149   end process CLKGEN;
 150
 151 -------------------------------------------------------------------------------
 152 -- test the design
 153 -------------------------------------------------------------------------------
 154   TEST_IT : process
 155
 156     -- wait for n clock cycles
 157     procedure icwait(cycles : natural) is
 158     begin
 159       for i in 1 to cycles loop
 160         wait until clk = '1' and clk'event;
 161       end loop;
 162     end;
 163
 164   begin
 165     -----------------------------------------------------------------------------
 166     -- initial reset
 167     -----------------------------------------------------------------------------
 168     reset_pin <= '0';
 169     icwait(10);
 170     reset_pin <= '1';
 171     icwait(10000000);
 172
 173     ---------------------------------------------------------------------------
 174     -- exit testbench
 175     ---------------------------------------------------------------------------
 176     assert false
 177       report "Test finished"
 178       severity error;
 179
 180   end process test_it;
 181
 182   clk_pin <= clk;
 183
 184 end structure;
 185
 186 -------------------------------------------------------------------------------
 187 -- configuration
 188 -------------------------------------------------------------------------------
 189 configuration vga_conf_pre of vga_pre_tb is
 190   for structure
 191     for vga_unit : vga use entity work.vga(beh);
 192     end for;
 193   end for;
 194 end vga_conf_pre;
 195
 196
 197