bsp2/Designflow/src/vga_ent.vhd

   1 -------------------------------------------------------------------------------
   2 -- Title      : vga entitiy
   3 -- Project    : LU Digital Design
   4 -------------------------------------------------------------------------------
   5 -- File       : vga_ent.vhd
   6 -- Author     : Thomas Handl
   7 -- Company    : TU Wien
   8 -- Created    : 2004-04-07
   9 -- Last update: 2006-02-24
  10 -------------------------------------------------------------------------------
  11 -- Description: entity of top level module, external pins defined here
  12 -------------------------------------------------------------------------------
  13 -- Copyright (c) 2004 TU Wien
  14 -------------------------------------------------------------------------------
  15 -- Revisions  :
  16 -- Date        Version  Author  Description
  17 -- 2004-04-07  1.0      handl   Created
  18 -- 2006-02-24  2.0      ST      revised
  19 -------------------------------------------------------------------------------
  20
  21
  22 -------------------------------------------------------------------------------
  23 -- LIBRARIES
  24 -------------------------------------------------------------------------------
  25
  26 library IEEE;
  27 use IEEE.std_logic_1164.all;
  28 use IEEE.std_logic_unsigned.all;
  29 use IEEE.std_logic_arith.all;
  30
  31 use work.vga_pak.all;
  32
  33
  34 -------------------------------------------------------------------------------
  35 -- ENTITY
  36 -------------------------------------------------------------------------------
  37
  38 entity vga is
  39   port(
  40 -- input pins from PCB board
  41        clk_pin                                  : in  std_logic;         -- clock pin
  42        reset_pin                                : in  std_logic;         -- reset pins (from switch)
  43 -- output pins to RGB connector / VGA screen
  44        r0_pin, r1_pin, r2_pin                   : out std_logic;         -- to RGB connector "red"
  45        g0_pin, g1_pin, g2_pin                   : out std_logic;         -- to RGB connector "green"
  46        b0_pin, b1_pin                           : out std_logic;         -- to RGB connector "blue"
  47        hsync_pin                                : out std_logic;         -- to RGB connector "Hsync"
  48        vsync_pin                                : out std_logic;         -- to RGB connector "Vsync"
  49 -- output pins to 7-segment display
  50        seven_seg_pin                                 : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
  51 -- output pins provided for debugging only / logic analyzer
  52        d_hsync, d_vsync                         : out std_logic;         -- copy of hsync_pin, vsync_pin
  53        d_column_counter                         : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  54        d_line_counter                           : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  55        d_set_column_counter, d_set_line_counter : out std_logic;
  56        d_hsync_counter                          : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  57        d_vsync_counter                          : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  58        d_set_hsync_counter, d_set_vsync_counter : out std_logic;
  59        d_h_enable                               : out std_logic;
  60        d_v_enable                               : out std_logic;
  61        d_r, d_g, d_b                            : out std_logic;
  62        d_hsync_state                            : out hsync_state_type;
  63        d_vsync_state                            : out vsync_state_type;
  64        d_state_clk                              : out std_logic;
  65        d_toggle                                 : out std_logic;
  66        d_toggle_counter                         : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)
  67        );
  68
  69 end vga;
  70
  71 -------------------------------------------------------------------------------
  72 -- END ENTITY
  73 -------------------------------------------------------------------------------