bsp2/Designflow/src/vga_beh_tb.vhd

   1 -------------------------------------------------------------------------------
   2 -- Title      : vga testbench
   3 -- Project    :
   4 -------------------------------------------------------------------------------
   5 -- File       : vga_tb.vhd
   6 -- Author     : Thomas Handl
   7 -- Company    : TU Wien
   8 -- Created    : 2004-04-07
   9 -- Last update: 2006-09-29
  10 -- Platform   :
  11 -------------------------------------------------------------------------------
  12 -- Description:
  13 -------------------------------------------------------------------------------
  14 -- Copyright (c) 2004 TU Wien
  15 -------------------------------------------------------------------------------
  16 -- Revisions  :
  17 -- Date        Version  Author  Description
  18 -- 2004-04-07  1.0      handl   Created
  19 -------------------------------------------------------------------------------
  20
  21
  22 -------------------------------------------------------------------------------
  23 -- LIBRARIES
  24 -------------------------------------------------------------------------------
  25
  26 library IEEE;
  27 use IEEE.std_logic_1164.all;
  28 use IEEE.std_logic_unsigned.all;
  29 use IEEE.std_logic_arith.all;
  30
  31 use work.vga_pak.all;
  32
  33
  34 -------------------------------------------------------------------------------
  35 -- ENTITY
  36 -------------------------------------------------------------------------------
  37 entity vga_tb is
  38
  39 end vga_tb;
  40
  41
  42 -------------------------------------------------------------------------------
  43 -- ARCHITECTURE
  44 -------------------------------------------------------------------------------
  45 architecture behaviour of vga_tb is
  46
  47   constant cc : time := 39.7 ns;        -- test clock period
  48   component vga
  49     port (
  50       clk_pin                                  : in  std_logic;
  51       reset_pin                                : in  std_logic;
  52       r0_pin, r1_pin, r2_pin                   : out std_logic;
  53       g0_pin, g1_pin, g2_pin                   : out std_logic;
  54       b0_pin, b1_pin                           : out std_logic;
  55       hsync_pin                                : out std_logic;
  56       vsync_pin                                : out std_logic;
  57       seven_seg_pin                            : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
  58       d_hsync, d_vsync                         : out std_logic;
  59       d_column_counter                         : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  60       d_line_counter                           : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  61       d_set_column_counter, d_set_line_counter : out std_logic;
  62       d_hsync_counter                          : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  63       d_vsync_counter                          : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  64       d_set_hsync_counter, d_set_vsync_counter : out std_logic;
  65       d_h_enable                               : out std_logic;
  66       d_v_enable                               : out std_logic;
  67       d_r, d_g, d_b                            : out std_logic;
  68       d_hsync_state                            : out hsync_state_type;
  69       d_vsync_state                            : out vsync_state_type;
  70       d_state_clk                              : out std_logic;
  71       d_toggle                                 : out std_logic;
  72       d_toggle_counter                         : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0));
  73   end component;
  74
  75   signal clk_pin                                  : std_logic;
  76   signal reset_pin                                : std_logic;
  77   signal r0_pin, r1_pin, r2_pin                   : std_logic;
  78   signal g0_pin, g1_pin, g2_pin                   : std_logic;
  79   signal b0_pin, b1_pin                           : std_logic;
  80   signal hsync_pin                                : std_logic;
  81   signal vsync_pin                                : std_logic;
  82   signal seven_seg_pin                            : std_logic_vector(2*SEG_WIDTH-1 downto 0);
  83   signal d_hsync, d_vsync                         : std_logic;
  84   signal d_column_counter                         : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  85   signal d_line_counter                           : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  86   signal d_set_column_counter, d_set_line_counter : std_logic;
  87   signal d_hsync_counter                          : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  88   signal d_vsync_counter                          : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  89   signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
  90   signal d_h_enable                               : std_logic;
  91   signal d_v_enable                               : std_logic;
  92   signal d_r, d_g, d_b                            : std_logic;
  93   signal d_hsync_state                            : hsync_state_type;
  94   signal d_vsync_state                            : vsync_state_type;
  95   signal d_state_clk                              : std_logic;
  96   signal d_toggle                                 : std_logic;
  97   signal d_toggle_counter                         : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);
  98
  99
 100 begin
 101
 102   vga_unit: vga
 103     port map (
 104       clk_pin              => clk_pin,
 105       reset_pin            => reset_pin,
 106       r0_pin               => r0_pin,
 107       r1_pin               => r1_pin,
 108       r2_pin               => r2_pin,
 109       g0_pin               => g0_pin,
 110       g1_pin               => g1_pin,
 111       g2_pin               => g2_pin,
 112       b0_pin               => b0_pin,
 113       b1_pin               => b1_pin,
 114       hsync_pin            => hsync_pin,
 115       vsync_pin            => vsync_pin,
 116       seven_seg_pin        => seven_seg_pin,
 117       d_hsync              => d_hsync,
 118       d_vsync              => d_vsync,
 119       d_column_counter     => d_column_counter,
 120       d_line_counter       => d_line_counter,
 121       d_set_column_counter => d_set_column_counter,
 122       d_set_line_counter   => d_set_line_counter,
 123       d_hsync_counter      => d_hsync_counter,
 124       d_vsync_counter      => d_vsync_counter,
 125       d_set_hsync_counter  => d_set_hsync_counter,
 126       d_set_vsync_counter  => d_set_vsync_counter,
 127       d_h_enable           => d_h_enable,
 128       d_v_enable           => d_v_enable,
 129       d_r                  => d_r,
 130       d_g                  => d_g,
 131       d_b                  => d_b,
 132       d_hsync_state        => d_hsync_state,
 133       d_vsync_state        => d_vsync_state,
 134       d_state_clk          => d_state_clk,
 135       d_toggle             => d_toggle,
 136       d_toggle_counter     => d_toggle_counter);
 137
 138
 139 -------------------------------------------------------------------------------
 140 -- generate simulation clock
 141 -------------------------------------------------------------------------------
 142   CLKGEN : process
 143   begin
 144     clk_pin <= '1';
 145     wait for cc/2;
 146     clk_pin <= '0';
 147     wait for cc/2;
 148   end process CLKGEN;
 149
 150 -------------------------------------------------------------------------------
 151 -- test the design
 152 -------------------------------------------------------------------------------
 153   TEST_IT : process
 154
 155     -- wait for n clock cycles
 156     procedure icwait(cycles : natural) is
 157     begin
 158       for i in 1 to cycles loop
 159         wait until clk_pin = '1' and clk_pin'event;
 160       end loop;
 161     end;
 162
 163   begin
 164     -----------------------------------------------------------------------------
 165     -- initial reset
 166     -----------------------------------------------------------------------------
 167     reset_pin <= '0';
 168     icwait(10);
 169     reset_pin <= '1';
 170     icwait(10000000);
 171
 172     ---------------------------------------------------------------------------
 173     -- exit testbench
 174     ---------------------------------------------------------------------------
 175     assert false
 176       report "Test finished"
 177       severity error;
 178
 179   end process test_it;
 180
 181 end behaviour;
 182
 183
 184 -------------------------------------------------------------------------------
 185 -- configuration
 186 -------------------------------------------------------------------------------
 187 configuration vga_conf_beh of vga_tb is
 188   for behaviour
 189     for vga_unit : vga use entity work.vga(behav);
 190     end for;
 191   end for;
 192 end vga_conf_beh;
 193
 194