bsp2/Designflow/ppr/sim/vga.eda.rpt

   1 EDA Netlist Writer report for vga
   2 Wed Oct 28 14:19:55 2009
   3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
   4
   5
   6 ---------------------
   7 ; Table of Contents ;
   8 ---------------------
   9   1. Legal Notice
  10   2. EDA Netlist Writer Summary
  11   3. Simulation Settings
  12   4. Simulation Generated Files
  13   5. EDA Netlist Writer Messages
  14
  15
  16
  17 ----------------
  18 ; Legal Notice ;
  19 ----------------
  20 Copyright (C) 1991-2009 Altera Corporation
  21 Your use of Altera Corporation's design tools, logic functions
  22 and other software and tools, and its AMPP partner logic
  23 functions, and any output files from any of the foregoing
  24 (including device programming or simulation files), and any
  25 associated documentation or information are expressly subject
  26 to the terms and conditions of the Altera Program License
  27 Subscription Agreement, Altera MegaCore Function License
  28 Agreement, or other applicable license agreement, including,
  29 without limitation, that your use is for the sole purpose of
  30 programming logic devices manufactured by Altera and sold by
  31 Altera or its authorized distributors.  Please refer to the
  32 applicable agreement for further details.
  33
  34
  35
  36 +-------------------------------------------------------------------+
  37 ; EDA Netlist Writer Summary                                        ;
  38 +---------------------------+---------------------------------------+
  39 ; EDA Netlist Writer Status ; Successful - Wed Oct 28 14:19:55 2009 ;
  40 ; Revision Name             ; vga                                   ;
  41 ; Top-level Entity Name     ; vga                                   ;
  42 ; Family                    ; Stratix                               ;
  43 ; Simulation Files Creation ; Successful                            ;
  44 +---------------------------+---------------------------------------+
  45
  46
  47 +---------------------------------------------------------------------------------------------------------------------+
  48 ; Simulation Settings                                                                                                 ;
  49 +---------------------------------------------------------------------------------------------------+-----------------+
  50 ; Option                                                                                            ; Setting         ;
  51 +---------------------------------------------------------------------------------------------------+-----------------+
  52 ; Tool Name                                                                                         ; ModelSim (VHDL) ;
  53 ; Generate netlist for functional simulation only                                                   ; Off             ;
  54 ; Time scale                                                                                        ; 1 ps            ;
  55 ; Truncate long hierarchy paths                                                                     ; Off             ;
  56 ; Map illegal HDL characters                                                                        ; Off             ;
  57 ; Flatten buses into individual nodes                                                               ; Off             ;
  58 ; Maintain hierarchy                                                                                ; Off             ;
  59 ; Bring out device-wide set/reset signals as ports                                                  ; Off             ;
  60 ; Enable glitch filtering                                                                           ; Off             ;
  61 ; Do not write top level VHDL entity                                                                ; Off             ;
  62 ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off             ;
  63 ; Architecture name in VHDL output netlist                                                          ; structure       ;
  64 ; Generate third-party EDA tool command script for RTL functional simulation                        ; Off             ;
  65 ; Generate third-party EDA tool command script for gate-level simulation                            ; Off             ;
  66 +---------------------------------------------------------------------------------------------------+-----------------+
  67
  68
  69 +--------------------------------------------------------------------------------------+
  70 ; Simulation Generated Files                                                           ;
  71 +--------------------------------------------------------------------------------------+
  72 ; Generated Files                                                                      ;
  73 +--------------------------------------------------------------------------------------+
  74 ; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho     ;
  75 ; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo ;
  76 +--------------------------------------------------------------------------------------+
  77
  78
  79 +-----------------------------+
  80 ; EDA Netlist Writer Messages ;
  81 +-----------------------------+
  82 Info: *******************************************************************
  83 Info: Running Quartus II EDA Netlist Writer
  84     Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
  85     Info: Processing started: Wed Oct 28 14:19:54 2009
  86 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga
  87 Info: Generated files "vga.vho" and "vga_vhd.sdo" in directory "/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/" for EDA simulation tool
  88 Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
  89     Info: Peak virtual memory: 163 megabytes
  90     Info: Processing ended: Wed Oct 28 14:19:55 2009
  91     Info: Elapsed time: 00:00:01
  92     Info: Total CPU time (on all processors): 00:00:01
  93
  94