bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho

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   2 -- Your use of Altera Corporation's design tools, logic functions
   3 -- and other software and tools, and its AMPP partner logic
   4 -- functions, and any output files from any of the foregoing
   5 -- (including device programming or simulation files), and any
   6 -- associated documentation or information are expressly subject
   7 -- to the terms and conditions of the Altera Program License
   8 -- Subscription Agreement, Altera MegaCore Function License
   9 -- Agreement, or other applicable license agreement, including,
  10 -- without limitation, that your use is for the sole purpose of
  11 -- programming logic devices manufactured by Altera and sold by
  12 -- Altera or its authorized distributors.  Please refer to the
  13 -- applicable agreement for further details.
  14
  15 -- VENDOR "Altera"
  16 -- PROGRAM "Quartus II"
  17 -- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
  18
  19 -- DATE "10/28/2009 14:19:55"
  20
  21 --
  22 -- Device: Altera EP1S25F672C6 Package FBGA672
  23 --
  24
  25 --
  26 -- This VHDL file should be used for ModelSim (VHDL) only
  27 --
  28
  29 LIBRARY IEEE, stratix;
  30 USE IEEE.std_logic_1164.all;
  31 USE stratix.stratix_components.all;
  32
  33 ENTITY  vga IS
  34     PORT (
  35         clk_pin : IN std_logic;
  36         reset_pin : IN std_logic;
  37         r0_pin : OUT std_logic;
  38         r1_pin : OUT std_logic;
  39         r2_pin : OUT std_logic;
  40         g0_pin : OUT std_logic;
  41         g1_pin : OUT std_logic;
  42         g2_pin : OUT std_logic;
  43         b0_pin : OUT std_logic;
  44         b1_pin : OUT std_logic;
  45         hsync_pin : OUT std_logic;
  46         vsync_pin : OUT std_logic;
  47         seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0);
  48         d_hsync : OUT std_logic;
  49         d_vsync : OUT std_logic;
  50         d_column_counter : OUT std_logic_vector(9 DOWNTO 0);
  51         d_line_counter : OUT std_logic_vector(8 DOWNTO 0);
  52         d_set_column_counter : OUT std_logic;
  53         d_set_line_counter : OUT std_logic;
  54         d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  55         d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  56         d_set_hsync_counter : OUT std_logic;
  57         d_set_vsync_counter : OUT std_logic;
  58         d_h_enable : OUT std_logic;
  59         d_v_enable : OUT std_logic;
  60         d_r : OUT std_logic;
  61         d_g : OUT std_logic;
  62         d_b : OUT std_logic;
  63         d_hsync_state : OUT std_logic_vector(0 TO 6);
  64         d_vsync_state : OUT std_logic_vector(0 TO 6);
  65         d_state_clk : OUT std_logic;
  66         d_toggle : OUT std_logic;
  67         d_toggle_counter : OUT std_logic_vector(24 DOWNTO 0)
  68         );
  69 END vga;
  70
  71 ARCHITECTURE structure OF vga IS
  72 SIGNAL gnd : std_logic := '0';
  73 SIGNAL vcc : std_logic := '1';
  74 SIGNAL devoe : std_logic := '1';
  75 SIGNAL devclrn : std_logic := '1';
  76 SIGNAL devpor : std_logic := '1';
  77 SIGNAL ww_devoe : std_logic;
  78 SIGNAL ww_devclrn : std_logic;
  79 SIGNAL ww_devpor : std_logic;
  80 SIGNAL ww_clk_pin : std_logic;
  81 SIGNAL ww_reset_pin : std_logic;
  82 SIGNAL ww_r0_pin : std_logic;
  83 SIGNAL ww_r1_pin : std_logic;
  84 SIGNAL ww_r2_pin : std_logic;
  85 SIGNAL ww_g0_pin : std_logic;
  86 SIGNAL ww_g1_pin : std_logic;
  87 SIGNAL ww_g2_pin : std_logic;
  88 SIGNAL ww_b0_pin : std_logic;
  89 SIGNAL ww_b1_pin : std_logic;
  90 SIGNAL ww_hsync_pin : std_logic;
  91 SIGNAL ww_vsync_pin : std_logic;
  92 SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0);
  93 SIGNAL ww_d_hsync : std_logic;
  94 SIGNAL ww_d_vsync : std_logic;
  95 SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0);
  96 SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0);
  97 SIGNAL ww_d_set_column_counter : std_logic;
  98 SIGNAL ww_d_set_line_counter : std_logic;
  99 SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0);
 100 SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0);
 101 SIGNAL ww_d_set_hsync_counter : std_logic;
 102 SIGNAL ww_d_set_vsync_counter : std_logic;
 103 SIGNAL ww_d_h_enable : std_logic;
 104 SIGNAL ww_d_v_enable : std_logic;
 105 SIGNAL ww_d_r : std_logic;
 106 SIGNAL ww_d_g : std_logic;
 107 SIGNAL ww_d_b : std_logic;
 108 SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6);
 109 SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6);
 110 SIGNAL ww_d_state_clk : std_logic;
 111 SIGNAL ww_d_toggle : std_logic;
 112 SIGNAL ww_d_toggle_counter : std_logic_vector(24 DOWNTO 0);
 113 SIGNAL \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\ : std_logic;
 114 SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic;
 115 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic;
 116 SIGNAL \clk_pin~combout\ : std_logic;
 117 SIGNAL \reset_pin~combout\ : std_logic;
 118 SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic;
 119 SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic;
 120 SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic;
 121 SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic;
 122 SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic;
 123 SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic;
 124 SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic;
 125 SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic;
 126 SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic;
 127 SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic;
 128 SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic;
 129 SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic;
 130 SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic;
 131 SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic;
 132 SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic;
 133 SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic;
 134 SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic;
 135 SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic;
 136 SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic;
 137 SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic;
 138 SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic;
 139 SIGNAL \vga_driver_unit|G_2_i\ : std_logic;
 140 SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic;
 141 SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic;
 142 SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic;
 143 SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic;
 144 SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic;
 145 SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic;
 146 SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic;
 147 SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic;
 148 SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic;
 149 SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic;
 150 SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic;
 151 SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic;
 152 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic;
 153 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic;
 154 SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic;
 155 SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic;
 156 SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic;
 157 SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic;
 158 SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic;
 159 SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic;
 160 SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic;
 161 SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic;
 162 SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic;
 163 SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic;
 164 SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 165 SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic;
 166 SIGNAL \vga_control_unit|toggle_counter_sig_0\ : std_logic;
 167 SIGNAL \vga_control_unit|toggle_counter_sig_1\ : std_logic;
 168 SIGNAL \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ : std_logic;
 169 SIGNAL \vga_control_unit|toggle_counter_sig_3\ : std_logic;
 170 SIGNAL \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ : std_logic;
 171 SIGNAL \vga_control_unit|toggle_counter_sig_2\ : std_logic;
 172 SIGNAL \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ : std_logic;
 173 SIGNAL \vga_control_unit|toggle_counter_sig_4\ : std_logic;
 174 SIGNAL \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ : std_logic;
 175 SIGNAL \vga_control_unit|toggle_counter_sig_5\ : std_logic;
 176 SIGNAL \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ : std_logic;
 177 SIGNAL \vga_control_unit|toggle_counter_sig_7\ : std_logic;
 178 SIGNAL \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ : std_logic;
 179 SIGNAL \vga_control_unit|toggle_counter_sig_6\ : std_logic;
 180 SIGNAL \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ : std_logic;
 181 SIGNAL \vga_control_unit|toggle_counter_sig_8\ : std_logic;
 182 SIGNAL \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ : std_logic;
 183 SIGNAL \vga_control_unit|toggle_counter_sig_9\ : std_logic;
 184 SIGNAL \vga_control_unit|toggle_counter_sig_11\ : std_logic;
 185 SIGNAL \vga_control_unit|toggle_counter_sig_10\ : std_logic;
 186 SIGNAL \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ : std_logic;
 187 SIGNAL \vga_control_unit|toggle_counter_sig_13\ : std_logic;
 188 SIGNAL \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ : std_logic;
 189 SIGNAL \vga_control_unit|toggle_counter_sig_12\ : std_logic;
 190 SIGNAL \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ : std_logic;
 191 SIGNAL \vga_control_unit|toggle_counter_sig_15\ : std_logic;
 192 SIGNAL \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ : std_logic;
 193 SIGNAL \vga_control_unit|toggle_counter_sig_14\ : std_logic;
 194 SIGNAL \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ : std_logic;
 195 SIGNAL \vga_control_unit|toggle_counter_sig_16\ : std_logic;
 196 SIGNAL \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ : std_logic;
 197 SIGNAL \vga_control_unit|toggle_counter_sig_17\ : std_logic;
 198 SIGNAL \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ : std_logic;
 199 SIGNAL \vga_control_unit|toggle_counter_sig_19\ : std_logic;
 200 SIGNAL \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ : std_logic;
 201 SIGNAL \vga_control_unit|toggle_counter_sig_18\ : std_logic;
 202 SIGNAL \vga_control_unit|toggle_counter_sig_20\ : std_logic;
 203 SIGNAL \vga_control_unit|un1_toggle_counter_siglt6\ : std_logic;
 204 SIGNAL \vga_control_unit|un1_toggle_counter_siglto9\ : std_logic;
 205 SIGNAL \vga_control_unit|un1_toggle_counter_siglto12\ : std_logic;
 206 SIGNAL \vga_control_unit|un1_toggle_counter_siglto15\ : std_logic;
 207 SIGNAL \vga_control_unit|un1_toggle_counter_siglto18\ : std_logic;
 208 SIGNAL \vga_control_unit|toggle_sig_0_0_0_g1\ : std_logic;
 209 SIGNAL \vga_control_unit|toggle_sig\ : std_logic;
 210 SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic;
 211 SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic;
 212 SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic;
 213 SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic;
 214 SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic;
 215 SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic;
 216 SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic;
 217 SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic;
 218 SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic;
 219 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic;
 220 SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic;
 221 SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic;
 222 SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic;
 223 SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic;
 224 SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic;
 225 SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic;
 226 SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic;
 227 SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic;
 228 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic;
 229 SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic;
 230 SIGNAL \vga_driver_unit|G_16_i\ : std_logic;
 231 SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic;
 232 SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic;
 233 SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic;
 234 SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic;
 235 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic;
 236 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic;
 237 SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic;
 238 SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic;
 239 SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic;
 240 SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic;
 241 SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic;
 242 SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic;
 243 SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic;
 244 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic;
 245 SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic;
 246 SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic;
 247 SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic;
 248 SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic;
 249 SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic;
 250 SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic;
 251 SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic;
 252 SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic;
 253 SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic;
 254 SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic;
 255 SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic;
 256 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic;
 257 SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic;
 258 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic;
 259 SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic;
 260 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic;
 261 SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic;
 262 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic;
 263 SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic;
 264 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic;
 265 SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic;
 266 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic;
 267 SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic;
 268 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic;
 269 SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic;
 270 SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic;
 271 SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic;
 272 SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic;
 273 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic;
 274 SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic;
 275 SIGNAL \vga_control_unit|un17_v_enablelto3\ : std_logic;
 276 SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_4_a\ : std_logic;
 277 SIGNAL \vga_control_unit|un13_v_enablelto4_0\ : std_logic;
 278 SIGNAL \vga_control_unit|un13_v_enablelto6\ : std_logic;
 279 SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_4\ : std_logic;
 280 SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic;
 281 SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic;
 282 SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic;
 283 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic;
 284 SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic;
 285 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic;
 286 SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic;
 287 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic;
 288 SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic;
 289 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic;
 290 SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic;
 291 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic;
 292 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic;
 293 SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic;
 294 SIGNAL \vga_driver_unit|un10_column_counter_siglt6_4\ : std_logic;
 295 SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic;
 296 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic;
 297 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic;
 298 SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic;
 299 SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic;
 300 SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic;
 301 SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic;
 302 SIGNAL \vga_control_unit|un5_v_enablelt2\ : std_logic;
 303 SIGNAL \vga_control_unit|un5_v_enablelto5\ : std_logic;
 304 SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 305 SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic;
 306 SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_2\ : std_logic;
 307 SIGNAL \vga_control_unit|un9_v_enablelto4\ : std_logic;
 308 SIGNAL \vga_control_unit|un9_v_enablelto6\ : std_logic;
 309 SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_3\ : std_logic;
 310 SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_5\ : std_logic;
 311 SIGNAL \vga_control_unit|r\ : std_logic;
 312 SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 313 SIGNAL \vga_control_unit|b\ : std_logic;
 314 SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic;
 315 SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic;
 316 SIGNAL \vga_driver_unit|h_sync\ : std_logic;
 317 SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic;
 318 SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic;
 319 SIGNAL \vga_driver_unit|v_sync\ : std_logic;
 320 SIGNAL \vga_control_unit|toggle_counter_sig_cout\ : std_logic_vector(18 DOWNTO 1);
 321 SIGNAL \vga_control_unit|un2_toggle_counter_next_cout\ : std_logic_vector(0 DOWNTO 0);
 322 SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 323 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1);
 324 SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1);
 325 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1);
 326 SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1);
 327 SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0);
 328 SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 329 SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0);
 330 SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic;
 331 SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic;
 332 SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic;
 333 SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic;
 334 SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic;
 335 SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic;
 336 SIGNAL \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ : std_logic;
 337 SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 338
 339 BEGIN
 340
 341 ww_clk_pin <= clk_pin;
 342 ww_reset_pin <= reset_pin;
 343 r0_pin <= ww_r0_pin;
 344 r1_pin <= ww_r1_pin;
 345 r2_pin <= ww_r2_pin;
 346 g0_pin <= ww_g0_pin;
 347 g1_pin <= ww_g1_pin;
 348 g2_pin <= ww_g2_pin;
 349 b0_pin <= ww_b0_pin;
 350 b1_pin <= ww_b1_pin;
 351 hsync_pin <= ww_hsync_pin;
 352 vsync_pin <= ww_vsync_pin;
 353 seven_seg_pin <= ww_seven_seg_pin;
 354 d_hsync <= ww_d_hsync;
 355 d_vsync <= ww_d_vsync;
 356 d_column_counter <= ww_d_column_counter;
 357 d_line_counter <= ww_d_line_counter;
 358 d_set_column_counter <= ww_d_set_column_counter;
 359 d_set_line_counter <= ww_d_set_line_counter;
 360 d_hsync_counter <= ww_d_hsync_counter;
 361 d_vsync_counter <= ww_d_vsync_counter;
 362 d_set_hsync_counter <= ww_d_set_hsync_counter;
 363 d_set_vsync_counter <= ww_d_set_vsync_counter;
 364 d_h_enable <= ww_d_h_enable;
 365 d_v_enable <= ww_d_v_enable;
 366 d_r <= ww_d_r;
 367 d_g <= ww_d_g;
 368 d_b <= ww_d_b;
 369 d_hsync_state <= ww_d_hsync_state;
 370 d_vsync_state <= ww_d_vsync_state;
 371 d_state_clk <= ww_d_state_clk;
 372 d_toggle <= ww_d_toggle;
 373 d_toggle_counter <= ww_d_toggle_counter;
 374 ww_devoe <= devoe;
 375 ww_devclrn <= devclrn;
 376 ww_devpor <= devpor;
 377 \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\;
 378 \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\;
 379 \vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\;
 380 \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\;
 381 \vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\;
 382 \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\;
 383 \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ <= NOT \vga_control_unit|toggle_sig_0_0_0_g1\;
 384 \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\;
 385
 386 clk_pin_in : stratix_io
 387 -- pragma translate_off
 388 GENERIC MAP (
 389         ddio_mode => "none",
 390         input_async_reset => "none",
 391         input_power_up => "low",
 392         input_register_mode => "none",
 393         input_sync_reset => "none",
 394         oe_async_reset => "none",
 395         oe_power_up => "low",
 396         oe_register_mode => "none",
 397         oe_sync_reset => "none",
 398         operation_mode => "input",
 399         output_async_reset => "none",
 400         output_power_up => "low",
 401         output_register_mode => "none",
 402         output_sync_reset => "none")
 403 -- pragma translate_on
 404 PORT MAP (
 405         devclrn => ww_devclrn,
 406         devpor => ww_devpor,
 407         devoe => ww_devoe,
 408         oe => GND,
 409         padio => ww_clk_pin,
 410         combout => \clk_pin~combout\);
 411
 412 reset_pin_in : stratix_io
 413 -- pragma translate_off
 414 GENERIC MAP (
 415         ddio_mode => "none",
 416         input_async_reset => "none",
 417         input_power_up => "low",
 418         input_register_mode => "none",
 419         input_sync_reset => "none",
 420         oe_async_reset => "none",
 421         oe_power_up => "low",
 422         oe_register_mode => "none",
 423         oe_sync_reset => "none",
 424         operation_mode => "input",
 425         output_async_reset => "none",
 426         output_power_up => "low",
 427         output_register_mode => "none",
 428         output_sync_reset => "none")
 429 -- pragma translate_on
 430 PORT MAP (
 431         devclrn => ww_devclrn,
 432         devpor => ww_devpor,
 433         devoe => ww_devoe,
 434         oe => GND,
 435         padio => ww_reset_pin,
 436         combout => \reset_pin~combout\);
 437
 438 \dly_counter_0_\ : stratix_lcell
 439 -- Equation(s):
 440 -- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 441
 442 -- pragma translate_off
 443 GENERIC MAP (
 444         lut_mask => "a0f0",
 445         operation_mode => "normal",
 446         output_mode => "reg_only",
 447         register_cascade_mode => "off",
 448         sum_lutc_input => "datac",
 449         synch_mode => "off")
 450 -- pragma translate_on
 451 PORT MAP (
 452         clk => \clk_pin~combout\,
 453         dataa => dly_counter(1),
 454         datac => \reset_pin~combout\,
 455         datad => dly_counter(0),
 456         aclr => GND,
 457         devclrn => ww_devclrn,
 458         devpor => ww_devpor,
 459         regout => dly_counter(0));
 460
 461 \dly_counter_1_\ : stratix_lcell
 462 -- Equation(s):
 463 -- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 464
 465 -- pragma translate_off
 466 GENERIC MAP (
 467         lut_mask => "e0e0",
 468         operation_mode => "normal",
 469         output_mode => "reg_only",
 470         register_cascade_mode => "off",
 471         sum_lutc_input => "datac",
 472         synch_mode => "off")
 473 -- pragma translate_on
 474 PORT MAP (
 475         clk => \clk_pin~combout\,
 476         dataa => dly_counter(0),
 477         datab => dly_counter(1),
 478         datac => \reset_pin~combout\,
 479         aclr => GND,
 480         devclrn => ww_devclrn,
 481         devpor => ww_devpor,
 482         regout => dly_counter(1));
 483
 484 \vga_driver_unit|vsync_state_6_\ : stratix_lcell
 485 -- Equation(s):
 486 -- \vga_driver_unit|un6_dly_counter_0_x\ = !dly_counter(0) # !\reset_pin~combout\ # !dly_counter(1)
 487 -- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 488
 489 -- pragma translate_off
 490 GENERIC MAP (
 491         lut_mask => "3fff",
 492         operation_mode => "normal",
 493         output_mode => "reg_and_comb",
 494         register_cascade_mode => "off",
 495         sum_lutc_input => "datac",
 496         synch_mode => "off")
 497 -- pragma translate_on
 498 PORT MAP (
 499         clk => \clk_pin~combout\,
 500         datab => dly_counter(1),
 501         datac => \reset_pin~combout\,
 502         datad => dly_counter(0),
 503         aclr => GND,
 504         devclrn => ww_devclrn,
 505         devpor => ww_devpor,
 506         combout => \vga_driver_unit|un6_dly_counter_0_x\,
 507         regout => \vga_driver_unit|vsync_state_6\);
 508
 509 \vga_driver_unit|hsync_state_6_\ : stratix_lcell
 510 -- Equation(s):
 511 -- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\
 512 -- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC)
 513
 514 -- pragma translate_off
 515 GENERIC MAP (
 516         lut_mask => "fff0",
 517         operation_mode => "normal",
 518         output_mode => "reg_and_comb",
 519         register_cascade_mode => "off",
 520         sum_lutc_input => "qfbk",
 521         synch_mode => "on")
 522 -- pragma translate_on
 523 PORT MAP (
 524         clk => \clk_pin~combout\,
 525         datac => \vga_driver_unit|un6_dly_counter_0_x\,
 526         datad => \vga_driver_unit|hsync_state_0\,
 527         aclr => GND,
 528         sload => VCC,
 529         devclrn => ww_devclrn,
 530         devpor => ww_devpor,
 531         combout => \vga_driver_unit|d_set_hsync_counter\,
 532         regout => \vga_driver_unit|hsync_state_6\);
 533
 534 \vga_driver_unit|hsync_counter_0_\ : stratix_lcell
 535 -- Equation(s):
 536 -- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 537 -- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\)
 538 -- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\)
 539
 540 -- pragma translate_off
 541 GENERIC MAP (
 542         lut_mask => "33cc",
 543         operation_mode => "arithmetic",
 544         output_mode => "reg_only",
 545         register_cascade_mode => "off",
 546         sum_lutc_input => "datac",
 547         synch_mode => "on")
 548 -- pragma translate_on
 549 PORT MAP (
 550         clk => \clk_pin~combout\,
 551         datab => \vga_driver_unit|hsync_counter_0\,
 552         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 553         aclr => GND,
 554         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 555         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 556         devclrn => ww_devclrn,
 557         devpor => ww_devpor,
 558         regout => \vga_driver_unit|hsync_counter_0\,
 559         cout0 => \vga_driver_unit|hsync_counter_cout\(0),
 560         cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\);
 561
 562 \vga_driver_unit|hsync_counter_1_\ : stratix_lcell
 563 -- Equation(s):
 564 -- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 565 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 566 -- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\)
 567 -- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\)
 568
 569 -- pragma translate_off
 570 GENERIC MAP (
 571         cin0_used => "true",
 572         cin1_used => "true",
 573         lut_mask => "3c3f",
 574         operation_mode => "arithmetic",
 575         output_mode => "reg_only",
 576         register_cascade_mode => "off",
 577         sum_lutc_input => "cin",
 578         synch_mode => "on")
 579 -- pragma translate_on
 580 PORT MAP (
 581         clk => \clk_pin~combout\,
 582         datab => \vga_driver_unit|hsync_counter_1\,
 583         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 584         aclr => GND,
 585         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 586         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 587         cin0 => \vga_driver_unit|hsync_counter_cout\(0),
 588         cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\,
 589         devclrn => ww_devclrn,
 590         devpor => ww_devpor,
 591         regout => \vga_driver_unit|hsync_counter_1\,
 592         cout0 => \vga_driver_unit|hsync_counter_cout\(1),
 593         cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\);
 594
 595 \vga_driver_unit|hsync_counter_2_\ : stratix_lcell
 596 -- Equation(s):
 597 -- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 598 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 599 -- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1)))
 600 -- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\))
 601
 602 -- pragma translate_off
 603 GENERIC MAP (
 604         cin0_used => "true",
 605         cin1_used => "true",
 606         lut_mask => "a50a",
 607         operation_mode => "arithmetic",
 608         output_mode => "reg_only",
 609         register_cascade_mode => "off",
 610         sum_lutc_input => "cin",
 611         synch_mode => "on")
 612 -- pragma translate_on
 613 PORT MAP (
 614         clk => \clk_pin~combout\,
 615         dataa => \vga_driver_unit|hsync_counter_2\,
 616         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 617         aclr => GND,
 618         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 619         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 620         cin0 => \vga_driver_unit|hsync_counter_cout\(1),
 621         cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\,
 622         devclrn => ww_devclrn,
 623         devpor => ww_devpor,
 624         regout => \vga_driver_unit|hsync_counter_2\,
 625         cout0 => \vga_driver_unit|hsync_counter_cout\(2),
 626         cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\);
 627
 628 \vga_driver_unit|hsync_counter_3_\ : stratix_lcell
 629 -- Equation(s):
 630 -- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 631 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 632 -- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\)
 633 -- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\)
 634
 635 -- pragma translate_off
 636 GENERIC MAP (
 637         cin0_used => "true",
 638         cin1_used => "true",
 639         lut_mask => "5a5f",
 640         operation_mode => "arithmetic",
 641         output_mode => "reg_only",
 642         register_cascade_mode => "off",
 643         sum_lutc_input => "cin",
 644         synch_mode => "on")
 645 -- pragma translate_on
 646 PORT MAP (
 647         clk => \clk_pin~combout\,
 648         dataa => \vga_driver_unit|hsync_counter_3\,
 649         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 650         aclr => GND,
 651         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 652         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 653         cin0 => \vga_driver_unit|hsync_counter_cout\(2),
 654         cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\,
 655         devclrn => ww_devclrn,
 656         devpor => ww_devpor,
 657         regout => \vga_driver_unit|hsync_counter_3\,
 658         cout0 => \vga_driver_unit|hsync_counter_cout\(3),
 659         cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\);
 660
 661 \vga_driver_unit|hsync_counter_4_\ : stratix_lcell
 662 -- Equation(s):
 663 -- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 664 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 665 -- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\))
 666
 667 -- pragma translate_off
 668 GENERIC MAP (
 669         cin0_used => "true",
 670         cin1_used => "true",
 671         lut_mask => "a50a",
 672         operation_mode => "arithmetic",
 673         output_mode => "reg_only",
 674         register_cascade_mode => "off",
 675         sum_lutc_input => "cin",
 676         synch_mode => "on")
 677 -- pragma translate_on
 678 PORT MAP (
 679         clk => \clk_pin~combout\,
 680         dataa => \vga_driver_unit|hsync_counter_4\,
 681         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 682         aclr => GND,
 683         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 684         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 685         cin0 => \vga_driver_unit|hsync_counter_cout\(3),
 686         cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\,
 687         devclrn => ww_devclrn,
 688         devpor => ww_devpor,
 689         regout => \vga_driver_unit|hsync_counter_4\,
 690         cout => \vga_driver_unit|hsync_counter_cout\(4));
 691
 692 \vga_driver_unit|hsync_counter_5_\ : stratix_lcell
 693 -- Equation(s):
 694 -- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 695 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 696 -- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 697 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 698
 699 -- pragma translate_off
 700 GENERIC MAP (
 701         cin_used => "true",
 702         lut_mask => "3c3f",
 703         operation_mode => "arithmetic",
 704         output_mode => "reg_only",
 705         register_cascade_mode => "off",
 706         sum_lutc_input => "cin",
 707         synch_mode => "on")
 708 -- pragma translate_on
 709 PORT MAP (
 710         clk => \clk_pin~combout\,
 711         datab => \vga_driver_unit|hsync_counter_5\,
 712         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 713         aclr => GND,
 714         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 715         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 716         cin => \vga_driver_unit|hsync_counter_cout\(4),
 717         devclrn => ww_devclrn,
 718         devpor => ww_devpor,
 719         regout => \vga_driver_unit|hsync_counter_5\,
 720         cout0 => \vga_driver_unit|hsync_counter_cout\(5),
 721         cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\);
 722
 723 \vga_driver_unit|hsync_counter_6_\ : stratix_lcell
 724 -- Equation(s):
 725 -- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 726 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 727 -- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5))
 728 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\)
 729
 730 -- pragma translate_off
 731 GENERIC MAP (
 732         cin0_used => "true",
 733         cin1_used => "true",
 734         cin_used => "true",
 735         lut_mask => "c30c",
 736         operation_mode => "arithmetic",
 737         output_mode => "reg_only",
 738         register_cascade_mode => "off",
 739         sum_lutc_input => "cin",
 740         synch_mode => "on")
 741 -- pragma translate_on
 742 PORT MAP (
 743         clk => \clk_pin~combout\,
 744         datab => \vga_driver_unit|hsync_counter_6\,
 745         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 746         aclr => GND,
 747         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 748         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 749         cin => \vga_driver_unit|hsync_counter_cout\(4),
 750         cin0 => \vga_driver_unit|hsync_counter_cout\(5),
 751         cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\,
 752         devclrn => ww_devclrn,
 753         devpor => ww_devpor,
 754         regout => \vga_driver_unit|hsync_counter_6\,
 755         cout0 => \vga_driver_unit|hsync_counter_cout\(6),
 756         cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\);
 757
 758 \vga_driver_unit|hsync_counter_7_\ : stratix_lcell
 759 -- Equation(s):
 760 -- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 761 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 762 -- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\)
 763 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\)
 764
 765 -- pragma translate_off
 766 GENERIC MAP (
 767         cin0_used => "true",
 768         cin1_used => "true",
 769         cin_used => "true",
 770         lut_mask => "5a5f",
 771         operation_mode => "arithmetic",
 772         output_mode => "reg_only",
 773         register_cascade_mode => "off",
 774         sum_lutc_input => "cin",
 775         synch_mode => "on")
 776 -- pragma translate_on
 777 PORT MAP (
 778         clk => \clk_pin~combout\,
 779         dataa => \vga_driver_unit|hsync_counter_7\,
 780         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 781         aclr => GND,
 782         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 783         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 784         cin => \vga_driver_unit|hsync_counter_cout\(4),
 785         cin0 => \vga_driver_unit|hsync_counter_cout\(6),
 786         cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\,
 787         devclrn => ww_devclrn,
 788         devpor => ww_devpor,
 789         regout => \vga_driver_unit|hsync_counter_7\,
 790         cout0 => \vga_driver_unit|hsync_counter_cout\(7),
 791         cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\);
 792
 793 \vga_driver_unit|hsync_counter_8_\ : stratix_lcell
 794 -- Equation(s):
 795 -- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 796 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 797 -- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7)))
 798 -- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\))
 799
 800 -- pragma translate_off
 801 GENERIC MAP (
 802         cin0_used => "true",
 803         cin1_used => "true",
 804         cin_used => "true",
 805         lut_mask => "a50a",
 806         operation_mode => "arithmetic",
 807         output_mode => "reg_only",
 808         register_cascade_mode => "off",
 809         sum_lutc_input => "cin",
 810         synch_mode => "on")
 811 -- pragma translate_on
 812 PORT MAP (
 813         clk => \clk_pin~combout\,
 814         dataa => \vga_driver_unit|hsync_counter_8\,
 815         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 816         aclr => GND,
 817         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 818         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 819         cin => \vga_driver_unit|hsync_counter_cout\(4),
 820         cin0 => \vga_driver_unit|hsync_counter_cout\(7),
 821         cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\,
 822         devclrn => ww_devclrn,
 823         devpor => ww_devpor,
 824         regout => \vga_driver_unit|hsync_counter_8\,
 825         cout0 => \vga_driver_unit|hsync_counter_cout\(8),
 826         cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\);
 827
 828 \vga_driver_unit|hsync_counter_9_\ : stratix_lcell
 829 -- Equation(s):
 830 -- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $
 831 -- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 832
 833 -- pragma translate_off
 834 GENERIC MAP (
 835         cin0_used => "true",
 836         cin1_used => "true",
 837         cin_used => "true",
 838         lut_mask => "0ff0",
 839         operation_mode => "normal",
 840         output_mode => "reg_only",
 841         register_cascade_mode => "off",
 842         sum_lutc_input => "cin",
 843         synch_mode => "on")
 844 -- pragma translate_on
 845 PORT MAP (
 846         clk => \clk_pin~combout\,
 847         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 848         datad => \vga_driver_unit|hsync_counter_9\,
 849         aclr => GND,
 850         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 851         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 852         cin => \vga_driver_unit|hsync_counter_cout\(4),
 853         cin0 => \vga_driver_unit|hsync_counter_cout\(8),
 854         cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\,
 855         devclrn => ww_devclrn,
 856         devpor => ww_devpor,
 857         regout => \vga_driver_unit|hsync_counter_9\);
 858
 859 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell
 860 -- Equation(s):
 861 -- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_5\ # !\vga_driver_unit|hsync_counter_7\ # !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_4\
 862
 863 -- pragma translate_off
 864 GENERIC MAP (
 865         lut_mask => "7fff",
 866         operation_mode => "normal",
 867         output_mode => "comb_only",
 868         register_cascade_mode => "off",
 869         sum_lutc_input => "datac",
 870         synch_mode => "off")
 871 -- pragma translate_on
 872 PORT MAP (
 873         dataa => \vga_driver_unit|hsync_counter_4\,
 874         datab => \vga_driver_unit|hsync_counter_6\,
 875         datac => \vga_driver_unit|hsync_counter_7\,
 876         datad => \vga_driver_unit|hsync_counter_5\,
 877         devclrn => ww_devclrn,
 878         devpor => ww_devpor,
 879         combout => \vga_driver_unit|un9_hsync_counterlt9_3\);
 880
 881 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell
 882 -- Equation(s):
 883 -- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_3\
 884
 885 -- pragma translate_off
 886 GENERIC MAP (
 887         lut_mask => "8000",
 888         operation_mode => "normal",
 889         output_mode => "comb_only",
 890         register_cascade_mode => "off",
 891         sum_lutc_input => "datac",
 892         synch_mode => "off")
 893 -- pragma translate_on
 894 PORT MAP (
 895         dataa => \vga_driver_unit|hsync_counter_1\,
 896         datab => \vga_driver_unit|hsync_counter_2\,
 897         datac => \vga_driver_unit|hsync_counter_0\,
 898         datad => \vga_driver_unit|hsync_counter_3\,
 899         devclrn => ww_devclrn,
 900         devpor => ww_devpor,
 901         combout => \vga_driver_unit|un13_hsync_counter_7\);
 902
 903 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell
 904 -- Equation(s):
 905 -- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|un13_hsync_counter_7\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|hsync_counter_8\
 906
 907 -- pragma translate_off
 908 GENERIC MAP (
 909         lut_mask => "f7ff",
 910         operation_mode => "normal",
 911         output_mode => "comb_only",
 912         register_cascade_mode => "off",
 913         sum_lutc_input => "datac",
 914         synch_mode => "off")
 915 -- pragma translate_on
 916 PORT MAP (
 917         dataa => \vga_driver_unit|hsync_counter_8\,
 918         datab => \vga_driver_unit|hsync_counter_9\,
 919         datac => \vga_driver_unit|un9_hsync_counterlt9_3\,
 920         datad => \vga_driver_unit|un13_hsync_counter_7\,
 921         devclrn => ww_devclrn,
 922         devpor => ww_devpor,
 923         combout => \vga_driver_unit|un9_hsync_counterlt9\);
 924
 925 \vga_driver_unit|G_2\ : stratix_lcell
 926 -- Equation(s):
 927 -- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\
 928
 929 -- pragma translate_off
 930 GENERIC MAP (
 931         lut_mask => "0f1f",
 932         operation_mode => "normal",
 933         output_mode => "comb_only",
 934         register_cascade_mode => "off",
 935         sum_lutc_input => "datac",
 936         synch_mode => "off")
 937 -- pragma translate_on
 938 PORT MAP (
 939         dataa => \vga_driver_unit|hsync_state_0\,
 940         datab => \vga_driver_unit|hsync_state_6\,
 941         datac => \vga_driver_unit|un9_hsync_counterlt9\,
 942         datad => \vga_driver_unit|un6_dly_counter_0_x\,
 943         devclrn => ww_devclrn,
 944         devpor => ww_devpor,
 945         combout => \vga_driver_unit|G_2_i\);
 946
 947 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell
 948 -- Equation(s):
 949 -- \vga_driver_unit|un13_hsync_counter_2\ = \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_5\
 950
 951 -- pragma translate_off
 952 GENERIC MAP (
 953         lut_mask => "0080",
 954         operation_mode => "normal",
 955         output_mode => "comb_only",
 956         register_cascade_mode => "off",
 957         sum_lutc_input => "datac",
 958         synch_mode => "off")
 959 -- pragma translate_on
 960 PORT MAP (
 961         dataa => \vga_driver_unit|hsync_counter_4\,
 962         datab => \vga_driver_unit|hsync_counter_9\,
 963         datac => \vga_driver_unit|hsync_counter_8\,
 964         datad => \vga_driver_unit|hsync_counter_5\,
 965         devclrn => ww_devclrn,
 966         devpor => ww_devpor,
 967         combout => \vga_driver_unit|un13_hsync_counter_2\);
 968
 969 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell
 970 -- Equation(s):
 971 -- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_2\ & \vga_driver_unit|un13_hsync_counter_7\
 972
 973 -- pragma translate_off
 974 GENERIC MAP (
 975         lut_mask => "1000",
 976         operation_mode => "normal",
 977         output_mode => "comb_only",
 978         register_cascade_mode => "off",
 979         sum_lutc_input => "datac",
 980         synch_mode => "off")
 981 -- pragma translate_on
 982 PORT MAP (
 983         dataa => \vga_driver_unit|hsync_counter_7\,
 984         datab => \vga_driver_unit|hsync_counter_6\,
 985         datac => \vga_driver_unit|un13_hsync_counter_2\,
 986         datad => \vga_driver_unit|un13_hsync_counter_7\,
 987         devclrn => ww_devclrn,
 988         devpor => ww_devpor,
 989         combout => \vga_driver_unit|un13_hsync_counter\);
 990
 991 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell
 992 -- Equation(s):
 993 -- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_0\ & !\vga_driver_unit|hsync_counter_3\
 994
 995 -- pragma translate_off
 996 GENERIC MAP (
 997         lut_mask => "0020",
 998         operation_mode => "normal",
 999         output_mode => "comb_only",
1000         register_cascade_mode => "off",
1001         sum_lutc_input => "datac",
1002         synch_mode => "off")
1003 -- pragma translate_on
1004 PORT MAP (
1005         dataa => \vga_driver_unit|hsync_counter_1\,
1006         datab => \vga_driver_unit|hsync_counter_4\,
1007         datac => \vga_driver_unit|hsync_counter_0\,
1008         datad => \vga_driver_unit|hsync_counter_3\,
1009         devclrn => ww_devclrn,
1010         devpor => ww_devpor,
1011         combout => \vga_driver_unit|un11_hsync_counter_3\);
1012
1013 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell
1014 -- Equation(s):
1015 -- \vga_driver_unit|un11_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\
1016
1017 -- pragma translate_off
1018 GENERIC MAP (
1019         lut_mask => "3000",
1020         operation_mode => "normal",
1021         output_mode => "comb_only",
1022         register_cascade_mode => "off",
1023         sum_lutc_input => "datac",
1024         synch_mode => "off")
1025 -- pragma translate_on
1026 PORT MAP (
1027         datab => \vga_driver_unit|hsync_counter_6\,
1028         datac => \vga_driver_unit|hsync_counter_7\,
1029         datad => \vga_driver_unit|hsync_counter_2\,
1030         devclrn => ww_devclrn,
1031         devpor => ww_devpor,
1032         combout => \vga_driver_unit|un11_hsync_counter_2\);
1033
1034 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell
1035 -- Equation(s):
1036 -- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\
1037
1038 -- pragma translate_off
1039 GENERIC MAP (
1040         lut_mask => "0003",
1041         operation_mode => "normal",
1042         output_mode => "comb_only",
1043         register_cascade_mode => "off",
1044         sum_lutc_input => "datac",
1045         synch_mode => "off")
1046 -- pragma translate_on
1047 PORT MAP (
1048         datab => \vga_driver_unit|hsync_counter_8\,
1049         datac => \vga_driver_unit|hsync_counter_9\,
1050         datad => \vga_driver_unit|hsync_counter_5\,
1051         devclrn => ww_devclrn,
1052         devpor => ww_devpor,
1053         combout => \vga_driver_unit|un10_hsync_counter_1\);
1054
1055 \vga_driver_unit|hsync_state_5_\ : stratix_lcell
1056 -- Equation(s):
1057 -- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_0\ # \vga_driver_unit|hsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1058
1059 -- pragma translate_off
1060 GENERIC MAP (
1061         lut_mask => "fafa",
1062         operation_mode => "normal",
1063         output_mode => "reg_only",
1064         register_cascade_mode => "off",
1065         sum_lutc_input => "datac",
1066         synch_mode => "on")
1067 -- pragma translate_on
1068 PORT MAP (
1069         clk => \clk_pin~combout\,
1070         dataa => \vga_driver_unit|hsync_state_0\,
1071         datac => \vga_driver_unit|hsync_state_6\,
1072         aclr => GND,
1073         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1074         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1075         devclrn => ww_devclrn,
1076         devpor => ww_devpor,
1077         regout => \vga_driver_unit|hsync_state_5\);
1078
1079 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell
1080 -- Equation(s):
1081 -- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_3\
1082
1083 -- pragma translate_off
1084 GENERIC MAP (
1085         lut_mask => "8000",
1086         operation_mode => "normal",
1087         output_mode => "comb_only",
1088         register_cascade_mode => "off",
1089         sum_lutc_input => "datac",
1090         synch_mode => "off")
1091 -- pragma translate_on
1092 PORT MAP (
1093         dataa => \vga_driver_unit|hsync_counter_4\,
1094         datab => \vga_driver_unit|hsync_counter_6\,
1095         datac => \vga_driver_unit|hsync_counter_1\,
1096         datad => \vga_driver_unit|hsync_counter_3\,
1097         devclrn => ww_devclrn,
1098         devpor => ww_devpor,
1099         combout => \vga_driver_unit|un10_hsync_counter_4\);
1100
1101 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell
1102 -- Equation(s):
1103 -- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_0\ & !\vga_driver_unit|hsync_counter_2\
1104
1105 -- pragma translate_off
1106 GENERIC MAP (
1107         lut_mask => "0003",
1108         operation_mode => "normal",
1109         output_mode => "comb_only",
1110         register_cascade_mode => "off",
1111         sum_lutc_input => "datac",
1112         synch_mode => "off")
1113 -- pragma translate_on
1114 PORT MAP (
1115         datab => \vga_driver_unit|hsync_counter_7\,
1116         datac => \vga_driver_unit|hsync_counter_0\,
1117         datad => \vga_driver_unit|hsync_counter_2\,
1118         devclrn => ww_devclrn,
1119         devpor => ww_devpor,
1120         combout => \vga_driver_unit|un10_hsync_counter_3\);
1121
1122 \vga_driver_unit|hsync_state_4_\ : stratix_lcell
1123 -- Equation(s):
1124 -- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|hsync_state_5\ & \vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un10_hsync_counter_3\, GLOBAL(\clk_pin~combout\), VCC, ,
1125 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1126
1127 -- pragma translate_off
1128 GENERIC MAP (
1129         lut_mask => "8000",
1130         operation_mode => "normal",
1131         output_mode => "reg_only",
1132         register_cascade_mode => "off",
1133         sum_lutc_input => "datac",
1134         synch_mode => "on")
1135 -- pragma translate_on
1136 PORT MAP (
1137         clk => \clk_pin~combout\,
1138         dataa => \vga_driver_unit|hsync_state_5\,
1139         datab => \vga_driver_unit|un10_hsync_counter_4\,
1140         datac => \vga_driver_unit|un10_hsync_counter_1\,
1141         datad => \vga_driver_unit|un10_hsync_counter_3\,
1142         aclr => GND,
1143         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1144         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1145         devclrn => ww_devclrn,
1146         devpor => ww_devpor,
1147         regout => \vga_driver_unit|hsync_state_4\);
1148
1149 \vga_driver_unit|hsync_state_1_\ : stratix_lcell
1150 -- Equation(s):
1151 -- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|un11_hsync_counter_3\ & \vga_driver_unit|un11_hsync_counter_2\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|hsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, ,
1152 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1153
1154 -- pragma translate_off
1155 GENERIC MAP (
1156         lut_mask => "8000",
1157         operation_mode => "normal",
1158         output_mode => "reg_only",
1159         register_cascade_mode => "off",
1160         sum_lutc_input => "datac",
1161         synch_mode => "on")
1162 -- pragma translate_on
1163 PORT MAP (
1164         clk => \clk_pin~combout\,
1165         dataa => \vga_driver_unit|un11_hsync_counter_3\,
1166         datab => \vga_driver_unit|un11_hsync_counter_2\,
1167         datac => \vga_driver_unit|un10_hsync_counter_1\,
1168         datad => \vga_driver_unit|hsync_state_4\,
1169         aclr => GND,
1170         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1171         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1172         devclrn => ww_devclrn,
1173         devpor => ww_devpor,
1174         regout => \vga_driver_unit|hsync_state_1\);
1175
1176 \vga_driver_unit|hsync_state_3_\ : stratix_lcell
1177 -- Equation(s):
1178 -- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|hsync_state_2\ & (!\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3 # !\vga_driver_unit|un13_hsync_counter\) # !\vga_driver_unit|hsync_state_2\ &
1179 -- !\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3
1180 -- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
1181
1182 -- pragma translate_off
1183 GENERIC MAP (
1184         lut_mask => "30ba",
1185         operation_mode => "normal",
1186         output_mode => "reg_and_comb",
1187         register_cascade_mode => "off",
1188         sum_lutc_input => "qfbk",
1189         synch_mode => "on")
1190 -- pragma translate_on
1191 PORT MAP (
1192         clk => \clk_pin~combout\,
1193         dataa => \vga_driver_unit|hsync_state_2\,
1194         datab => \vga_driver_unit|un12_hsync_counter\,
1195         datac => \vga_driver_unit|hsync_state_1\,
1196         datad => \vga_driver_unit|un13_hsync_counter\,
1197         aclr => GND,
1198         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1199         sload => VCC,
1200         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1201         devclrn => ww_devclrn,
1202         devpor => ww_devpor,
1203         combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1204         regout => \vga_driver_unit|hsync_state_3\);
1205
1206 \vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
1207 -- Equation(s):
1208 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_4\)
1209
1210 -- pragma translate_off
1211 GENERIC MAP (
1212         lut_mask => "2aaa",
1213         operation_mode => "normal",
1214         output_mode => "comb_only",
1215         register_cascade_mode => "off",
1216         sum_lutc_input => "datac",
1217         synch_mode => "off")
1218 -- pragma translate_on
1219 PORT MAP (
1220         dataa => \vga_driver_unit|hsync_state_5\,
1221         datab => \vga_driver_unit|un10_hsync_counter_4\,
1222         datac => \vga_driver_unit|un10_hsync_counter_3\,
1223         datad => \vga_driver_unit|un10_hsync_counter_1\,
1224         devclrn => ww_devclrn,
1225         devpor => ww_devpor,
1226         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\);
1227
1228 \vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
1229 -- Equation(s):
1230 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un11_hsync_counter_2\)
1231
1232 -- pragma translate_off
1233 GENERIC MAP (
1234         lut_mask => "2aaa",
1235         operation_mode => "normal",
1236         output_mode => "comb_only",
1237         register_cascade_mode => "off",
1238         sum_lutc_input => "datac",
1239         synch_mode => "off")
1240 -- pragma translate_on
1241 PORT MAP (
1242         dataa => \vga_driver_unit|hsync_state_4\,
1243         datab => \vga_driver_unit|un11_hsync_counter_2\,
1244         datac => \vga_driver_unit|un11_hsync_counter_3\,
1245         datad => \vga_driver_unit|un10_hsync_counter_1\,
1246         devclrn => ww_devclrn,
1247         devpor => ww_devpor,
1248         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\);
1249
1250 \vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell
1251 -- Equation(s):
1252 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\
1253
1254 -- pragma translate_off
1255 GENERIC MAP (
1256         lut_mask => "aaab",
1257         operation_mode => "normal",
1258         output_mode => "comb_only",
1259         register_cascade_mode => "off",
1260         sum_lutc_input => "datac",
1261         synch_mode => "off")
1262 -- pragma translate_on
1263 PORT MAP (
1264         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
1265         datab => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1266         datac => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\,
1267         datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\,
1268         devclrn => ww_devclrn,
1269         devpor => ww_devpor,
1270         combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\);
1271
1272 \vga_driver_unit|hsync_state_0_\ : stratix_lcell
1273 -- Equation(s):
1274 -- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|un13_hsync_counter\ & \vga_driver_unit|hsync_state_2\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1275
1276 -- pragma translate_off
1277 GENERIC MAP (
1278         lut_mask => "c0c0",
1279         operation_mode => "normal",
1280         output_mode => "reg_only",
1281         register_cascade_mode => "off",
1282         sum_lutc_input => "datac",
1283         synch_mode => "on")
1284 -- pragma translate_on
1285 PORT MAP (
1286         clk => \clk_pin~combout\,
1287         datab => \vga_driver_unit|un13_hsync_counter\,
1288         datac => \vga_driver_unit|hsync_state_2\,
1289         aclr => GND,
1290         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1291         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1292         devclrn => ww_devclrn,
1293         devpor => ww_devpor,
1294         regout => \vga_driver_unit|hsync_state_0\);
1295
1296 \vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
1297 -- Equation(s):
1298 -- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = \reset_pin~combout\ & dly_counter(1) & dly_counter(0) & !\vga_driver_unit|d_set_hsync_counter\
1299
1300 -- pragma translate_off
1301 GENERIC MAP (
1302         lut_mask => "0080",
1303         operation_mode => "normal",
1304         output_mode => "comb_only",
1305         register_cascade_mode => "off",
1306         sum_lutc_input => "datac",
1307         synch_mode => "off")
1308 -- pragma translate_on
1309 PORT MAP (
1310         dataa => \reset_pin~combout\,
1311         datab => dly_counter(1),
1312         datac => dly_counter(0),
1313         datad => \vga_driver_unit|d_set_hsync_counter\,
1314         devclrn => ww_devclrn,
1315         devpor => ww_devpor,
1316         combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\);
1317
1318 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell
1319 -- Equation(s):
1320 -- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_3\
1321
1322 -- pragma translate_off
1323 GENERIC MAP (
1324         lut_mask => "0004",
1325         operation_mode => "normal",
1326         output_mode => "comb_only",
1327         register_cascade_mode => "off",
1328         sum_lutc_input => "datac",
1329         synch_mode => "off")
1330 -- pragma translate_on
1331 PORT MAP (
1332         dataa => \vga_driver_unit|hsync_counter_7\,
1333         datab => \vga_driver_unit|hsync_counter_9\,
1334         datac => \vga_driver_unit|hsync_counter_6\,
1335         datad => \vga_driver_unit|hsync_counter_3\,
1336         devclrn => ww_devclrn,
1337         devpor => ww_devpor,
1338         combout => \vga_driver_unit|un12_hsync_counter_4\);
1339
1340 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell
1341 -- Equation(s):
1342 -- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_5\
1343
1344 -- pragma translate_off
1345 GENERIC MAP (
1346         lut_mask => "0040",
1347         operation_mode => "normal",
1348         output_mode => "comb_only",
1349         register_cascade_mode => "off",
1350         sum_lutc_input => "datac",
1351         synch_mode => "off")
1352 -- pragma translate_on
1353 PORT MAP (
1354         dataa => \vga_driver_unit|hsync_counter_4\,
1355         datab => \vga_driver_unit|hsync_counter_2\,
1356         datac => \vga_driver_unit|hsync_counter_8\,
1357         datad => \vga_driver_unit|hsync_counter_5\,
1358         devclrn => ww_devclrn,
1359         devpor => ww_devpor,
1360         combout => \vga_driver_unit|un12_hsync_counter_3\);
1361
1362 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell
1363 -- Equation(s):
1364 -- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|un12_hsync_counter_4\ & \vga_driver_unit|un12_hsync_counter_3\
1365
1366 -- pragma translate_off
1367 GENERIC MAP (
1368         lut_mask => "8000",
1369         operation_mode => "normal",
1370         output_mode => "comb_only",
1371         register_cascade_mode => "off",
1372         sum_lutc_input => "datac",
1373         synch_mode => "off")
1374 -- pragma translate_on
1375 PORT MAP (
1376         dataa => \vga_driver_unit|hsync_counter_1\,
1377         datab => \vga_driver_unit|hsync_counter_0\,
1378         datac => \vga_driver_unit|un12_hsync_counter_4\,
1379         datad => \vga_driver_unit|un12_hsync_counter_3\,
1380         devclrn => ww_devclrn,
1381         devpor => ww_devpor,
1382         combout => \vga_driver_unit|un12_hsync_counter\);
1383
1384 \vga_driver_unit|hsync_state_2_\ : stratix_lcell
1385 -- Equation(s):
1386 -- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|hsync_state_3\ & \vga_driver_unit|un12_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1387
1388 -- pragma translate_off
1389 GENERIC MAP (
1390         lut_mask => "c0c0",
1391         operation_mode => "normal",
1392         output_mode => "reg_only",
1393         register_cascade_mode => "off",
1394         sum_lutc_input => "datac",
1395         synch_mode => "on")
1396 -- pragma translate_on
1397 PORT MAP (
1398         clk => \clk_pin~combout\,
1399         datab => \vga_driver_unit|hsync_state_3\,
1400         datac => \vga_driver_unit|un12_hsync_counter\,
1401         aclr => GND,
1402         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1403         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1404         devclrn => ww_devclrn,
1405         devpor => ww_devpor,
1406         regout => \vga_driver_unit|hsync_state_2\);
1407
1408 \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
1409 -- Equation(s):
1410 -- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_4\ & !\vga_driver_unit|hsync_state_5\
1411
1412 -- pragma translate_off
1413 GENERIC MAP (
1414         lut_mask => "ff03",
1415         operation_mode => "normal",
1416         output_mode => "comb_only",
1417         register_cascade_mode => "off",
1418         sum_lutc_input => "datac",
1419         synch_mode => "off")
1420 -- pragma translate_on
1421 PORT MAP (
1422         datab => \vga_driver_unit|hsync_state_4\,
1423         datac => \vga_driver_unit|hsync_state_5\,
1424         datad => \vga_driver_unit|un6_dly_counter_0_x\,
1425         devclrn => ww_devclrn,
1426         devpor => ww_devpor,
1427         combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\);
1428
1429 \vga_driver_unit|v_enable_sig_Z\ : stratix_lcell
1430 -- Equation(s):
1431 -- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1432
1433 -- pragma translate_off
1434 GENERIC MAP (
1435         lut_mask => "fcfc",
1436         operation_mode => "normal",
1437         output_mode => "reg_only",
1438         register_cascade_mode => "off",
1439         sum_lutc_input => "datac",
1440         synch_mode => "on")
1441 -- pragma translate_on
1442 PORT MAP (
1443         clk => \clk_pin~combout\,
1444         datab => \vga_driver_unit|hsync_state_3\,
1445         datac => \vga_driver_unit|hsync_state_1\,
1446         aclr => GND,
1447         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1448         ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\,
1449         devclrn => ww_devclrn,
1450         devpor => ww_devpor,
1451         regout => \vga_driver_unit|v_enable_sig\);
1452
1453 \vga_control_unit|toggle_counter_sig_0_\ : stratix_lcell
1454 -- Equation(s):
1455 -- \vga_control_unit|toggle_counter_sig_0\ = DFFEAS(!\vga_control_unit|toggle_counter_sig_0\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1456
1457 -- pragma translate_off
1458 GENERIC MAP (
1459         lut_mask => "0f0f",
1460         operation_mode => "normal",
1461         output_mode => "reg_only",
1462         register_cascade_mode => "off",
1463         sum_lutc_input => "datac",
1464         synch_mode => "on")
1465 -- pragma translate_on
1466 PORT MAP (
1467         clk => \clk_pin~combout\,
1468         datac => \vga_control_unit|toggle_counter_sig_0\,
1469         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1470         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1471         devclrn => ww_devclrn,
1472         devpor => ww_devpor,
1473         regout => \vga_control_unit|toggle_counter_sig_0\);
1474
1475 \vga_control_unit|toggle_counter_sig_1_\ : stratix_lcell
1476 -- Equation(s):
1477 -- \vga_control_unit|toggle_counter_sig_1\ = DFFEAS(\vga_control_unit|toggle_counter_sig_0\ $ \vga_control_unit|toggle_counter_sig_1\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\,
1478 -- )
1479 -- \vga_control_unit|toggle_counter_sig_cout\(1) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
1480 -- \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
1481
1482 -- pragma translate_off
1483 GENERIC MAP (
1484         lut_mask => "6688",
1485         operation_mode => "arithmetic",
1486         output_mode => "reg_only",
1487         register_cascade_mode => "off",
1488         sum_lutc_input => "datac",
1489         synch_mode => "on")
1490 -- pragma translate_on
1491 PORT MAP (
1492         clk => \clk_pin~combout\,
1493         dataa => \vga_control_unit|toggle_counter_sig_0\,
1494         datab => \vga_control_unit|toggle_counter_sig_1\,
1495         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1496         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1497         devclrn => ww_devclrn,
1498         devpor => ww_devpor,
1499         regout => \vga_control_unit|toggle_counter_sig_1\,
1500         cout0 => \vga_control_unit|toggle_counter_sig_cout\(1),
1501         cout1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\);
1502
1503 \vga_control_unit|toggle_counter_sig_3_\ : stratix_lcell
1504 -- Equation(s):
1505 -- \vga_control_unit|toggle_counter_sig_3\ = DFFEAS(\vga_control_unit|toggle_counter_sig_3\ $ (\vga_control_unit|toggle_counter_sig_2\ & \vga_control_unit|toggle_counter_sig_cout\(1)), GLOBAL(\clk_pin~combout\),
1506 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1507 -- \vga_control_unit|toggle_counter_sig_cout\(3) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(1) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
1508 -- \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
1509
1510 -- pragma translate_off
1511 GENERIC MAP (
1512         cin0_used => "true",
1513         cin1_used => "true",
1514         lut_mask => "6c7f",
1515         operation_mode => "arithmetic",
1516         output_mode => "reg_only",
1517         register_cascade_mode => "off",
1518         sum_lutc_input => "cin",
1519         synch_mode => "on")
1520 -- pragma translate_on
1521 PORT MAP (
1522         clk => \clk_pin~combout\,
1523         dataa => \vga_control_unit|toggle_counter_sig_2\,
1524         datab => \vga_control_unit|toggle_counter_sig_3\,
1525         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1526         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1527         cin0 => \vga_control_unit|toggle_counter_sig_cout\(1),
1528         cin1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\,
1529         devclrn => ww_devclrn,
1530         devpor => ww_devpor,
1531         regout => \vga_control_unit|toggle_counter_sig_3\,
1532         cout0 => \vga_control_unit|toggle_counter_sig_cout\(3),
1533         cout1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\);
1534
1535 \vga_control_unit|un2_toggle_counter_next_0_\ : stratix_lcell
1536 -- Equation(s):
1537 -- \vga_control_unit|un2_toggle_counter_next_cout\(0) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
1538 -- \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
1539
1540 -- pragma translate_off
1541 GENERIC MAP (
1542         lut_mask => "ff88",
1543         operation_mode => "arithmetic",
1544         output_mode => "none",
1545         register_cascade_mode => "off",
1546         sum_lutc_input => "datac",
1547         synch_mode => "off")
1548 -- pragma translate_on
1549 PORT MAP (
1550         dataa => \vga_control_unit|toggle_counter_sig_0\,
1551         datab => \vga_control_unit|toggle_counter_sig_1\,
1552         devclrn => ww_devclrn,
1553         devpor => ww_devpor,
1554         combout => \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\,
1555         cout0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
1556         cout1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\);
1557
1558 \vga_control_unit|toggle_counter_sig_2_\ : stratix_lcell
1559 -- Equation(s):
1560 -- \vga_control_unit|toggle_counter_sig_2\ = DFFEAS(\vga_control_unit|toggle_counter_sig_2\ $ (\vga_control_unit|un2_toggle_counter_next_cout\(0)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
1561 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1562 -- \vga_control_unit|toggle_counter_sig_cout\(2) = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout\(0) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
1563 -- \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
1564
1565 -- pragma translate_off
1566 GENERIC MAP (
1567         cin0_used => "true",
1568         cin1_used => "true",
1569         lut_mask => "5a7f",
1570         operation_mode => "arithmetic",
1571         output_mode => "reg_only",
1572         register_cascade_mode => "off",
1573         sum_lutc_input => "cin",
1574         synch_mode => "on")
1575 -- pragma translate_on
1576 PORT MAP (
1577         clk => \clk_pin~combout\,
1578         dataa => \vga_control_unit|toggle_counter_sig_2\,
1579         datab => \vga_control_unit|toggle_counter_sig_3\,
1580         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1581         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1582         cin0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
1583         cin1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\,
1584         devclrn => ww_devclrn,
1585         devpor => ww_devpor,
1586         regout => \vga_control_unit|toggle_counter_sig_2\,
1587         cout0 => \vga_control_unit|toggle_counter_sig_cout\(2),
1588         cout1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\);
1589
1590 \vga_control_unit|toggle_counter_sig_4_\ : stratix_lcell
1591 -- Equation(s):
1592 -- \vga_control_unit|toggle_counter_sig_4\ = DFFEAS(\vga_control_unit|toggle_counter_sig_4\ $ (!\vga_control_unit|toggle_counter_sig_cout\(2)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
1593 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1594 -- \vga_control_unit|toggle_counter_sig_cout\(4) = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout\(2))
1595 -- \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\)
1596
1597 -- pragma translate_off
1598 GENERIC MAP (
1599         cin0_used => "true",
1600         cin1_used => "true",
1601         lut_mask => "a508",
1602         operation_mode => "arithmetic",
1603         output_mode => "reg_only",
1604         register_cascade_mode => "off",
1605         sum_lutc_input => "cin",
1606         synch_mode => "on")
1607 -- pragma translate_on
1608 PORT MAP (
1609         clk => \clk_pin~combout\,
1610         dataa => \vga_control_unit|toggle_counter_sig_4\,
1611         datab => \vga_control_unit|toggle_counter_sig_5\,
1612         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1613         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1614         cin0 => \vga_control_unit|toggle_counter_sig_cout\(2),
1615         cin1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\,
1616         devclrn => ww_devclrn,
1617         devpor => ww_devpor,
1618         regout => \vga_control_unit|toggle_counter_sig_4\,
1619         cout0 => \vga_control_unit|toggle_counter_sig_cout\(4),
1620         cout1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\);
1621
1622 \vga_control_unit|toggle_counter_sig_5_\ : stratix_lcell
1623 -- Equation(s):
1624 -- \vga_control_unit|toggle_counter_sig_5\ = DFFEAS(\vga_control_unit|toggle_counter_sig_5\ $ (\vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3)), GLOBAL(\clk_pin~combout\),
1625 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1626 -- \vga_control_unit|toggle_counter_sig_cout\(5) = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3))
1627 -- \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\)
1628
1629 -- pragma translate_off
1630 GENERIC MAP (
1631         cin0_used => "true",
1632         cin1_used => "true",
1633         lut_mask => "a608",
1634         operation_mode => "arithmetic",
1635         output_mode => "reg_only",
1636         register_cascade_mode => "off",
1637         sum_lutc_input => "cin",
1638         synch_mode => "on")
1639 -- pragma translate_on
1640 PORT MAP (
1641         clk => \clk_pin~combout\,
1642         dataa => \vga_control_unit|toggle_counter_sig_5\,
1643         datab => \vga_control_unit|toggle_counter_sig_4\,
1644         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1645         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1646         cin0 => \vga_control_unit|toggle_counter_sig_cout\(3),
1647         cin1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\,
1648         devclrn => ww_devclrn,
1649         devpor => ww_devpor,
1650         regout => \vga_control_unit|toggle_counter_sig_5\,
1651         cout0 => \vga_control_unit|toggle_counter_sig_cout\(5),
1652         cout1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\);
1653
1654 \vga_control_unit|toggle_counter_sig_7_\ : stratix_lcell
1655 -- Equation(s):
1656 -- \vga_control_unit|toggle_counter_sig_7\ = DFFEAS(\vga_control_unit|toggle_counter_sig_7\ $ (\vga_control_unit|toggle_counter_sig_6\ & \vga_control_unit|toggle_counter_sig_cout\(5)), GLOBAL(\clk_pin~combout\),
1657 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1658 -- \vga_control_unit|toggle_counter_sig_cout\(7) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(5) # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
1659 -- \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
1660
1661 -- pragma translate_off
1662 GENERIC MAP (
1663         cin0_used => "true",
1664         cin1_used => "true",
1665         lut_mask => "6a7f",
1666         operation_mode => "arithmetic",
1667         output_mode => "reg_only",
1668         register_cascade_mode => "off",
1669         sum_lutc_input => "cin",
1670         synch_mode => "on")
1671 -- pragma translate_on
1672 PORT MAP (
1673         clk => \clk_pin~combout\,
1674         dataa => \vga_control_unit|toggle_counter_sig_7\,
1675         datab => \vga_control_unit|toggle_counter_sig_6\,
1676         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1677         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1678         cin0 => \vga_control_unit|toggle_counter_sig_cout\(5),
1679         cin1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\,
1680         devclrn => ww_devclrn,
1681         devpor => ww_devpor,
1682         regout => \vga_control_unit|toggle_counter_sig_7\,
1683         cout0 => \vga_control_unit|toggle_counter_sig_cout\(7),
1684         cout1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\);
1685
1686 \vga_control_unit|toggle_counter_sig_6_\ : stratix_lcell
1687 -- Equation(s):
1688 -- \vga_control_unit|toggle_counter_sig_6\ = DFFEAS(\vga_control_unit|toggle_counter_sig_6\ $ (\vga_control_unit|toggle_counter_sig_cout\(4)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
1689 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1690 -- \vga_control_unit|toggle_counter_sig_cout\(6) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(4) # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
1691 -- \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
1692
1693 -- pragma translate_off
1694 GENERIC MAP (
1695         cin0_used => "true",
1696         cin1_used => "true",
1697         lut_mask => "5a7f",
1698         operation_mode => "arithmetic",
1699         output_mode => "reg_only",
1700         register_cascade_mode => "off",
1701         sum_lutc_input => "cin",
1702         synch_mode => "on")
1703 -- pragma translate_on
1704 PORT MAP (
1705         clk => \clk_pin~combout\,
1706         dataa => \vga_control_unit|toggle_counter_sig_6\,
1707         datab => \vga_control_unit|toggle_counter_sig_7\,
1708         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1709         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1710         cin0 => \vga_control_unit|toggle_counter_sig_cout\(4),
1711         cin1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\,
1712         devclrn => ww_devclrn,
1713         devpor => ww_devpor,
1714         regout => \vga_control_unit|toggle_counter_sig_6\,
1715         cout0 => \vga_control_unit|toggle_counter_sig_cout\(6),
1716         cout1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\);
1717
1718 \vga_control_unit|toggle_counter_sig_8_\ : stratix_lcell
1719 -- Equation(s):
1720 -- \vga_control_unit|toggle_counter_sig_8\ = DFFEAS(\vga_control_unit|toggle_counter_sig_8\ $ !\vga_control_unit|toggle_counter_sig_cout\(6), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
1721 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1722 -- \vga_control_unit|toggle_counter_sig_cout\(8) = CARRY(\vga_control_unit|toggle_counter_sig_9\ & \vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\)
1723
1724 -- pragma translate_off
1725 GENERIC MAP (
1726         cin0_used => "true",
1727         cin1_used => "true",
1728         lut_mask => "c308",
1729         operation_mode => "arithmetic",
1730         output_mode => "reg_only",
1731         register_cascade_mode => "off",
1732         sum_lutc_input => "cin",
1733         synch_mode => "on")
1734 -- pragma translate_on
1735 PORT MAP (
1736         clk => \clk_pin~combout\,
1737         dataa => \vga_control_unit|toggle_counter_sig_9\,
1738         datab => \vga_control_unit|toggle_counter_sig_8\,
1739         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1740         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1741         cin0 => \vga_control_unit|toggle_counter_sig_cout\(6),
1742         cin1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\,
1743         devclrn => ww_devclrn,
1744         devpor => ww_devpor,
1745         regout => \vga_control_unit|toggle_counter_sig_8\,
1746         cout => \vga_control_unit|toggle_counter_sig_cout\(8));
1747
1748 \vga_control_unit|toggle_counter_sig_9_\ : stratix_lcell
1749 -- Equation(s):
1750 -- \vga_control_unit|toggle_counter_sig_9\ = DFFEAS(\vga_control_unit|toggle_counter_sig_9\ $ (\vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout\(7)), GLOBAL(\clk_pin~combout\),
1751 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1752 -- \vga_control_unit|toggle_counter_sig_cout\(9) = CARRY(\vga_control_unit|toggle_counter_sig_9\ & \vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\)
1753
1754 -- pragma translate_off
1755 GENERIC MAP (
1756         cin0_used => "true",
1757         cin1_used => "true",
1758         lut_mask => "a608",
1759         operation_mode => "arithmetic",
1760         output_mode => "reg_only",
1761         register_cascade_mode => "off",
1762         sum_lutc_input => "cin",
1763         synch_mode => "on")
1764 -- pragma translate_on
1765 PORT MAP (
1766         clk => \clk_pin~combout\,
1767         dataa => \vga_control_unit|toggle_counter_sig_9\,
1768         datab => \vga_control_unit|toggle_counter_sig_8\,
1769         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1770         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1771         cin0 => \vga_control_unit|toggle_counter_sig_cout\(7),
1772         cin1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\,
1773         devclrn => ww_devclrn,
1774         devpor => ww_devpor,
1775         regout => \vga_control_unit|toggle_counter_sig_9\,
1776         cout => \vga_control_unit|toggle_counter_sig_cout\(9));
1777
1778 \vga_control_unit|toggle_counter_sig_11_\ : stratix_lcell
1779 -- Equation(s):
1780 -- \vga_control_unit|toggle_counter_sig_11\ = DFFEAS(\vga_control_unit|toggle_counter_sig_11\ $ (\vga_control_unit|toggle_counter_sig_10\ & \vga_control_unit|toggle_counter_sig_cout\(9)), GLOBAL(\clk_pin~combout\),
1781 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1782 -- \vga_control_unit|toggle_counter_sig_cout\(11) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
1783 -- \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
1784
1785 -- pragma translate_off
1786 GENERIC MAP (
1787         cin_used => "true",
1788         lut_mask => "6c7f",
1789         operation_mode => "arithmetic",
1790         output_mode => "reg_only",
1791         register_cascade_mode => "off",
1792         sum_lutc_input => "cin",
1793         synch_mode => "on")
1794 -- pragma translate_on
1795 PORT MAP (
1796         clk => \clk_pin~combout\,
1797         dataa => \vga_control_unit|toggle_counter_sig_10\,
1798         datab => \vga_control_unit|toggle_counter_sig_11\,
1799         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1800         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1801         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
1802         devclrn => ww_devclrn,
1803         devpor => ww_devpor,
1804         regout => \vga_control_unit|toggle_counter_sig_11\,
1805         cout0 => \vga_control_unit|toggle_counter_sig_cout\(11),
1806         cout1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\);
1807
1808 \vga_control_unit|toggle_counter_sig_10_\ : stratix_lcell
1809 -- Equation(s):
1810 -- \vga_control_unit|toggle_counter_sig_10\ = DFFEAS(\vga_control_unit|toggle_counter_sig_10\ $ (\vga_control_unit|toggle_counter_sig_cout\(8)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
1811 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1812 -- \vga_control_unit|toggle_counter_sig_cout\(10) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
1813 -- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
1814
1815 -- pragma translate_off
1816 GENERIC MAP (
1817         cin_used => "true",
1818         lut_mask => "5a7f",
1819         operation_mode => "arithmetic",
1820         output_mode => "reg_only",
1821         register_cascade_mode => "off",
1822         sum_lutc_input => "cin",
1823         synch_mode => "on")
1824 -- pragma translate_on
1825 PORT MAP (
1826         clk => \clk_pin~combout\,
1827         dataa => \vga_control_unit|toggle_counter_sig_10\,
1828         datab => \vga_control_unit|toggle_counter_sig_11\,
1829         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1830         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1831         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
1832         devclrn => ww_devclrn,
1833         devpor => ww_devpor,
1834         regout => \vga_control_unit|toggle_counter_sig_10\,
1835         cout0 => \vga_control_unit|toggle_counter_sig_cout\(10),
1836         cout1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\);
1837
1838 \vga_control_unit|toggle_counter_sig_13_\ : stratix_lcell
1839 -- Equation(s):
1840 -- \vga_control_unit|toggle_counter_sig_13\ = DFFEAS(\vga_control_unit|toggle_counter_sig_13\ $ (\vga_control_unit|toggle_counter_sig_12\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(11)) #
1841 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1842 -- \vga_control_unit|toggle_counter_sig_cout\(13) = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout\(11))
1843 -- \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)
1844
1845 -- pragma translate_off
1846 GENERIC MAP (
1847         cin0_used => "true",
1848         cin1_used => "true",
1849         cin_used => "true",
1850         lut_mask => "c608",
1851         operation_mode => "arithmetic",
1852         output_mode => "reg_only",
1853         register_cascade_mode => "off",
1854         sum_lutc_input => "cin",
1855         synch_mode => "on")
1856 -- pragma translate_on
1857 PORT MAP (
1858         clk => \clk_pin~combout\,
1859         dataa => \vga_control_unit|toggle_counter_sig_12\,
1860         datab => \vga_control_unit|toggle_counter_sig_13\,
1861         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1862         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1863         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
1864         cin0 => \vga_control_unit|toggle_counter_sig_cout\(11),
1865         cin1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\,
1866         devclrn => ww_devclrn,
1867         devpor => ww_devpor,
1868         regout => \vga_control_unit|toggle_counter_sig_13\,
1869         cout0 => \vga_control_unit|toggle_counter_sig_cout\(13),
1870         cout1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\);
1871
1872 \vga_control_unit|toggle_counter_sig_12_\ : stratix_lcell
1873 -- Equation(s):
1874 -- \vga_control_unit|toggle_counter_sig_12\ = DFFEAS(\vga_control_unit|toggle_counter_sig_12\ $ !(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(10)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
1875 -- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1876 -- \vga_control_unit|toggle_counter_sig_cout\(12) = CARRY(\vga_control_unit|toggle_counter_sig_13\ & \vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_cout\(10))
1877 -- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ = CARRY(\vga_control_unit|toggle_counter_sig_13\ & \vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\)
1878
1879 -- pragma translate_off
1880 GENERIC MAP (
1881         cin0_used => "true",
1882         cin1_used => "true",
1883         cin_used => "true",
1884         lut_mask => "c308",
1885         operation_mode => "arithmetic",
1886         output_mode => "reg_only",
1887         register_cascade_mode => "off",
1888         sum_lutc_input => "cin",
1889         synch_mode => "on")
1890 -- pragma translate_on
1891 PORT MAP (
1892         clk => \clk_pin~combout\,
1893         dataa => \vga_control_unit|toggle_counter_sig_13\,
1894         datab => \vga_control_unit|toggle_counter_sig_12\,
1895         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1896         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1897         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
1898         cin0 => \vga_control_unit|toggle_counter_sig_cout\(10),
1899         cin1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\,
1900         devclrn => ww_devclrn,
1901         devpor => ww_devpor,
1902         regout => \vga_control_unit|toggle_counter_sig_12\,
1903         cout0 => \vga_control_unit|toggle_counter_sig_cout\(12),
1904         cout1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\);
1905
1906 \vga_control_unit|toggle_counter_sig_15_\ : stratix_lcell
1907 -- Equation(s):
1908 -- \vga_control_unit|toggle_counter_sig_15\ = DFFEAS(\vga_control_unit|toggle_counter_sig_15\ $ (\vga_control_unit|toggle_counter_sig_14\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(13)) #
1909 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1910 -- \vga_control_unit|toggle_counter_sig_cout\(15) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(13) # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
1911 -- \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
1912
1913 -- pragma translate_off
1914 GENERIC MAP (
1915         cin0_used => "true",
1916         cin1_used => "true",
1917         cin_used => "true",
1918         lut_mask => "6a7f",
1919         operation_mode => "arithmetic",
1920         output_mode => "reg_only",
1921         register_cascade_mode => "off",
1922         sum_lutc_input => "cin",
1923         synch_mode => "on")
1924 -- pragma translate_on
1925 PORT MAP (
1926         clk => \clk_pin~combout\,
1927         dataa => \vga_control_unit|toggle_counter_sig_15\,
1928         datab => \vga_control_unit|toggle_counter_sig_14\,
1929         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1930         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1931         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
1932         cin0 => \vga_control_unit|toggle_counter_sig_cout\(13),
1933         cin1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\,
1934         devclrn => ww_devclrn,
1935         devpor => ww_devpor,
1936         regout => \vga_control_unit|toggle_counter_sig_15\,
1937         cout0 => \vga_control_unit|toggle_counter_sig_cout\(15),
1938         cout1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\);
1939
1940 \vga_control_unit|toggle_counter_sig_14_\ : stratix_lcell
1941 -- Equation(s):
1942 -- \vga_control_unit|toggle_counter_sig_14\ = DFFEAS(\vga_control_unit|toggle_counter_sig_14\ $ ((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(12)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
1943 -- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1944 -- \vga_control_unit|toggle_counter_sig_cout\(14) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(12) # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
1945 -- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
1946
1947 -- pragma translate_off
1948 GENERIC MAP (
1949         cin0_used => "true",
1950         cin1_used => "true",
1951         cin_used => "true",
1952         lut_mask => "5a7f",
1953         operation_mode => "arithmetic",
1954         output_mode => "reg_only",
1955         register_cascade_mode => "off",
1956         sum_lutc_input => "cin",
1957         synch_mode => "on")
1958 -- pragma translate_on
1959 PORT MAP (
1960         clk => \clk_pin~combout\,
1961         dataa => \vga_control_unit|toggle_counter_sig_14\,
1962         datab => \vga_control_unit|toggle_counter_sig_15\,
1963         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1964         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1965         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
1966         cin0 => \vga_control_unit|toggle_counter_sig_cout\(12),
1967         cin1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\,
1968         devclrn => ww_devclrn,
1969         devpor => ww_devpor,
1970         regout => \vga_control_unit|toggle_counter_sig_14\,
1971         cout0 => \vga_control_unit|toggle_counter_sig_cout\(14),
1972         cout1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\);
1973
1974 \vga_control_unit|toggle_counter_sig_16_\ : stratix_lcell
1975 -- Equation(s):
1976 -- \vga_control_unit|toggle_counter_sig_16\ = DFFEAS(\vga_control_unit|toggle_counter_sig_16\ $ !(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(14)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
1977 -- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
1978 -- \vga_control_unit|toggle_counter_sig_cout\(16) = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout\(14))
1979 -- \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\)
1980
1981 -- pragma translate_off
1982 GENERIC MAP (
1983         cin0_used => "true",
1984         cin1_used => "true",
1985         cin_used => "true",
1986         lut_mask => "c308",
1987         operation_mode => "arithmetic",
1988         output_mode => "reg_only",
1989         register_cascade_mode => "off",
1990         sum_lutc_input => "cin",
1991         synch_mode => "on")
1992 -- pragma translate_on
1993 PORT MAP (
1994         clk => \clk_pin~combout\,
1995         dataa => \vga_control_unit|toggle_counter_sig_17\,
1996         datab => \vga_control_unit|toggle_counter_sig_16\,
1997         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
1998         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
1999         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
2000         cin0 => \vga_control_unit|toggle_counter_sig_cout\(14),
2001         cin1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\,
2002         devclrn => ww_devclrn,
2003         devpor => ww_devpor,
2004         regout => \vga_control_unit|toggle_counter_sig_16\,
2005         cout0 => \vga_control_unit|toggle_counter_sig_cout\(16),
2006         cout1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\);
2007
2008 \vga_control_unit|toggle_counter_sig_17_\ : stratix_lcell
2009 -- Equation(s):
2010 -- \vga_control_unit|toggle_counter_sig_17\ = DFFEAS(\vga_control_unit|toggle_counter_sig_17\ $ (\vga_control_unit|toggle_counter_sig_16\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(15)) #
2011 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
2012 -- \vga_control_unit|toggle_counter_sig_cout\(17) = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout\(15))
2013 -- \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)
2014
2015 -- pragma translate_off
2016 GENERIC MAP (
2017         cin0_used => "true",
2018         cin1_used => "true",
2019         cin_used => "true",
2020         lut_mask => "a608",
2021         operation_mode => "arithmetic",
2022         output_mode => "reg_only",
2023         register_cascade_mode => "off",
2024         sum_lutc_input => "cin",
2025         synch_mode => "on")
2026 -- pragma translate_on
2027 PORT MAP (
2028         clk => \clk_pin~combout\,
2029         dataa => \vga_control_unit|toggle_counter_sig_17\,
2030         datab => \vga_control_unit|toggle_counter_sig_16\,
2031         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
2032         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
2033         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
2034         cin0 => \vga_control_unit|toggle_counter_sig_cout\(15),
2035         cin1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\,
2036         devclrn => ww_devclrn,
2037         devpor => ww_devpor,
2038         regout => \vga_control_unit|toggle_counter_sig_17\,
2039         cout0 => \vga_control_unit|toggle_counter_sig_cout\(17),
2040         cout1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\);
2041
2042 \vga_control_unit|toggle_counter_sig_19_\ : stratix_lcell
2043 -- Equation(s):
2044 -- \vga_control_unit|toggle_counter_sig_19\ = DFFEAS(\vga_control_unit|toggle_counter_sig_19\ $ (\vga_control_unit|toggle_counter_sig_18\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(17)) #
2045 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
2046
2047 -- pragma translate_off
2048 GENERIC MAP (
2049         cin0_used => "true",
2050         cin1_used => "true",
2051         cin_used => "true",
2052         lut_mask => "3fc0",
2053         operation_mode => "normal",
2054         output_mode => "reg_only",
2055         register_cascade_mode => "off",
2056         sum_lutc_input => "cin",
2057         synch_mode => "on")
2058 -- pragma translate_on
2059 PORT MAP (
2060         clk => \clk_pin~combout\,
2061         datab => \vga_control_unit|toggle_counter_sig_18\,
2062         datad => \vga_control_unit|toggle_counter_sig_19\,
2063         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
2064         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
2065         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
2066         cin0 => \vga_control_unit|toggle_counter_sig_cout\(17),
2067         cin1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\,
2068         devclrn => ww_devclrn,
2069         devpor => ww_devpor,
2070         regout => \vga_control_unit|toggle_counter_sig_19\);
2071
2072 \vga_control_unit|toggle_counter_sig_18_\ : stratix_lcell
2073 -- Equation(s):
2074 -- \vga_control_unit|toggle_counter_sig_18\ = DFFEAS(\vga_control_unit|toggle_counter_sig_18\ $ ((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(16)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
2075 -- \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
2076 -- \vga_control_unit|toggle_counter_sig_cout\(18) = CARRY(!\vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ # !\vga_control_unit|toggle_counter_sig_19\ # !\vga_control_unit|toggle_counter_sig_18\)
2077
2078 -- pragma translate_off
2079 GENERIC MAP (
2080         cin0_used => "true",
2081         cin1_used => "true",
2082         cin_used => "true",
2083         lut_mask => "5a7f",
2084         operation_mode => "arithmetic",
2085         output_mode => "reg_only",
2086         register_cascade_mode => "off",
2087         sum_lutc_input => "cin",
2088         synch_mode => "on")
2089 -- pragma translate_on
2090 PORT MAP (
2091         clk => \clk_pin~combout\,
2092         dataa => \vga_control_unit|toggle_counter_sig_18\,
2093         datab => \vga_control_unit|toggle_counter_sig_19\,
2094         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
2095         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
2096         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
2097         cin0 => \vga_control_unit|toggle_counter_sig_cout\(16),
2098         cin1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\,
2099         devclrn => ww_devclrn,
2100         devpor => ww_devpor,
2101         regout => \vga_control_unit|toggle_counter_sig_18\,
2102         cout => \vga_control_unit|toggle_counter_sig_cout\(18));
2103
2104 \vga_control_unit|toggle_counter_sig_20_\ : stratix_lcell
2105 -- Equation(s):
2106 -- \vga_control_unit|toggle_counter_sig_20\ = DFFEAS(\vga_control_unit|toggle_counter_sig_20\ $ !\vga_control_unit|toggle_counter_sig_cout\(18), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
2107 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
2108
2109 -- pragma translate_off
2110 GENERIC MAP (
2111         cin_used => "true",
2112         lut_mask => "c3c3",
2113         operation_mode => "normal",
2114         output_mode => "reg_only",
2115         register_cascade_mode => "off",
2116         sum_lutc_input => "cin",
2117         synch_mode => "on")
2118 -- pragma translate_on
2119 PORT MAP (
2120         clk => \clk_pin~combout\,
2121         datab => \vga_control_unit|toggle_counter_sig_20\,
2122         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
2123         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
2124         cin => \vga_control_unit|toggle_counter_sig_cout\(18),
2125         devclrn => ww_devclrn,
2126         devpor => ww_devpor,
2127         regout => \vga_control_unit|toggle_counter_sig_20\);
2128
2129 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6\ : stratix_lcell
2130 -- Equation(s):
2131 -- \vga_control_unit|un1_toggle_counter_siglt6\ = !\vga_control_unit|toggle_counter_sig_5\ # !\vga_control_unit|toggle_counter_sig_6\
2132
2133 -- pragma translate_off
2134 GENERIC MAP (
2135         lut_mask => "33ff",
2136         operation_mode => "normal",
2137         output_mode => "comb_only",
2138         register_cascade_mode => "off",
2139         sum_lutc_input => "datac",
2140         synch_mode => "off")
2141 -- pragma translate_on
2142 PORT MAP (
2143         datab => \vga_control_unit|toggle_counter_sig_6\,
2144         datad => \vga_control_unit|toggle_counter_sig_5\,
2145         devclrn => ww_devclrn,
2146         devpor => ww_devpor,
2147         combout => \vga_control_unit|un1_toggle_counter_siglt6\);
2148
2149 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9\ : stratix_lcell
2150 -- Equation(s):
2151 -- \vga_control_unit|un1_toggle_counter_siglto9\ = !\vga_control_unit|toggle_counter_sig_7\ & \vga_control_unit|un1_toggle_counter_siglt6\ # !\vga_control_unit|toggle_counter_sig_9\ # !\vga_control_unit|toggle_counter_sig_8\
2152
2153 -- pragma translate_off
2154 GENERIC MAP (
2155         lut_mask => "7f3f",
2156         operation_mode => "normal",
2157         output_mode => "comb_only",
2158         register_cascade_mode => "off",
2159         sum_lutc_input => "datac",
2160         synch_mode => "off")
2161 -- pragma translate_on
2162 PORT MAP (
2163         dataa => \vga_control_unit|toggle_counter_sig_7\,
2164         datab => \vga_control_unit|toggle_counter_sig_8\,
2165         datac => \vga_control_unit|toggle_counter_sig_9\,
2166         datad => \vga_control_unit|un1_toggle_counter_siglt6\,
2167         devclrn => ww_devclrn,
2168         devpor => ww_devpor,
2169         combout => \vga_control_unit|un1_toggle_counter_siglto9\);
2170
2171 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12\ : stratix_lcell
2172 -- Equation(s):
2173 -- \vga_control_unit|un1_toggle_counter_siglto12\ = !\vga_control_unit|toggle_counter_sig_11\ & !\vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_10\ & \vga_control_unit|un1_toggle_counter_siglto9\
2174
2175 -- pragma translate_off
2176 GENERIC MAP (
2177         lut_mask => "0100",
2178         operation_mode => "normal",
2179         output_mode => "comb_only",
2180         register_cascade_mode => "off",
2181         sum_lutc_input => "datac",
2182         synch_mode => "off")
2183 -- pragma translate_on
2184 PORT MAP (
2185         dataa => \vga_control_unit|toggle_counter_sig_11\,
2186         datab => \vga_control_unit|toggle_counter_sig_12\,
2187         datac => \vga_control_unit|toggle_counter_sig_10\,
2188         datad => \vga_control_unit|un1_toggle_counter_siglto9\,
2189         devclrn => ww_devclrn,
2190         devpor => ww_devpor,
2191         combout => \vga_control_unit|un1_toggle_counter_siglto12\);
2192
2193 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15\ : stratix_lcell
2194 -- Equation(s):
2195 -- \vga_control_unit|un1_toggle_counter_siglto15\ = \vga_control_unit|un1_toggle_counter_siglto12\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_13\ # !\vga_control_unit|toggle_counter_sig_14\
2196
2197 -- pragma translate_off
2198 GENERIC MAP (
2199         lut_mask => "ff7f",
2200         operation_mode => "normal",
2201         output_mode => "comb_only",
2202         register_cascade_mode => "off",
2203         sum_lutc_input => "datac",
2204         synch_mode => "off")
2205 -- pragma translate_on
2206 PORT MAP (
2207         dataa => \vga_control_unit|toggle_counter_sig_14\,
2208         datab => \vga_control_unit|toggle_counter_sig_13\,
2209         datac => \vga_control_unit|toggle_counter_sig_15\,
2210         datad => \vga_control_unit|un1_toggle_counter_siglto12\,
2211         devclrn => ww_devclrn,
2212         devpor => ww_devpor,
2213         combout => \vga_control_unit|un1_toggle_counter_siglto15\);
2214
2215 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18\ : stratix_lcell
2216 -- Equation(s):
2217 -- \vga_control_unit|un1_toggle_counter_siglto18\ = !\vga_control_unit|toggle_counter_sig_16\ & \vga_control_unit|un1_toggle_counter_siglto15\ # !\vga_control_unit|toggle_counter_sig_18\ # !\vga_control_unit|toggle_counter_sig_17\
2218
2219 -- pragma translate_off
2220 GENERIC MAP (
2221         lut_mask => "7f3f",
2222         operation_mode => "normal",
2223         output_mode => "comb_only",
2224         register_cascade_mode => "off",
2225         sum_lutc_input => "datac",
2226         synch_mode => "off")
2227 -- pragma translate_on
2228 PORT MAP (
2229         dataa => \vga_control_unit|toggle_counter_sig_16\,
2230         datab => \vga_control_unit|toggle_counter_sig_17\,
2231         datac => \vga_control_unit|toggle_counter_sig_18\,
2232         datad => \vga_control_unit|un1_toggle_counter_siglto15\,
2233         devclrn => ww_devclrn,
2234         devpor => ww_devpor,
2235         combout => \vga_control_unit|un1_toggle_counter_siglto18\);
2236
2237 \vga_control_unit|toggle_sig_0_0_0_g1_cZ\ : stratix_lcell
2238 -- Equation(s):
2239 -- \vga_control_unit|toggle_sig_0_0_0_g1\ = !\vga_control_unit|toggle_counter_sig_19\ & (\vga_control_unit|un1_toggle_counter_siglto18\) # !\vga_control_unit|toggle_counter_sig_20\
2240
2241 -- pragma translate_off
2242 GENERIC MAP (
2243         lut_mask => "7755",
2244         operation_mode => "normal",
2245         output_mode => "comb_only",
2246         register_cascade_mode => "off",
2247         sum_lutc_input => "datac",
2248         synch_mode => "off")
2249 -- pragma translate_on
2250 PORT MAP (
2251         dataa => \vga_control_unit|toggle_counter_sig_20\,
2252         datab => \vga_control_unit|toggle_counter_sig_19\,
2253         datad => \vga_control_unit|un1_toggle_counter_siglto18\,
2254         devclrn => ww_devclrn,
2255         devpor => ww_devpor,
2256         combout => \vga_control_unit|toggle_sig_0_0_0_g1\);
2257
2258 \vga_control_unit|toggle_sig_Z\ : stratix_lcell
2259 -- Equation(s):
2260 -- \vga_control_unit|toggle_sig\ = DFFEAS(\vga_control_unit|toggle_sig\ $ (!\vga_control_unit|toggle_sig_0_0_0_g1\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , )
2261
2262 -- pragma translate_off
2263 GENERIC MAP (
2264         lut_mask => "cc33",
2265         operation_mode => "normal",
2266         output_mode => "reg_only",
2267         register_cascade_mode => "off",
2268         sum_lutc_input => "datac",
2269         synch_mode => "off")
2270 -- pragma translate_on
2271 PORT MAP (
2272         clk => \clk_pin~combout\,
2273         datab => \vga_control_unit|toggle_sig\,
2274         datad => \vga_control_unit|toggle_sig_0_0_0_g1\,
2275         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
2276         devclrn => ww_devclrn,
2277         devpor => ww_devpor,
2278         regout => \vga_control_unit|toggle_sig\);
2279
2280 \vga_driver_unit|vsync_counter_0_\ : stratix_lcell
2281 -- Equation(s):
2282 -- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|vsync_counter_0\ $ \vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2283 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2284 -- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|d_set_hsync_counter\)
2285 -- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|d_set_hsync_counter\)
2286
2287 -- pragma translate_off
2288 GENERIC MAP (
2289         lut_mask => "6688",
2290         operation_mode => "arithmetic",
2291         output_mode => "reg_only",
2292         register_cascade_mode => "off",
2293         sum_lutc_input => "datac",
2294         synch_mode => "on")
2295 -- pragma translate_on
2296 PORT MAP (
2297         clk => \clk_pin~combout\,
2298         dataa => \vga_driver_unit|vsync_counter_0\,
2299         datab => \vga_driver_unit|d_set_hsync_counter\,
2300         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2301         aclr => GND,
2302         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2303         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2304         devclrn => ww_devclrn,
2305         devpor => ww_devpor,
2306         regout => \vga_driver_unit|vsync_counter_0\,
2307         cout0 => \vga_driver_unit|vsync_counter_cout\(0),
2308         cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\);
2309
2310 \vga_driver_unit|vsync_counter_1_\ : stratix_lcell
2311 -- Equation(s):
2312 -- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2313 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2314 -- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\)
2315 -- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\)
2316
2317 -- pragma translate_off
2318 GENERIC MAP (
2319         cin0_used => "true",
2320         cin1_used => "true",
2321         lut_mask => "3c3f",
2322         operation_mode => "arithmetic",
2323         output_mode => "reg_only",
2324         register_cascade_mode => "off",
2325         sum_lutc_input => "cin",
2326         synch_mode => "on")
2327 -- pragma translate_on
2328 PORT MAP (
2329         clk => \clk_pin~combout\,
2330         datab => \vga_driver_unit|vsync_counter_1\,
2331         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2332         aclr => GND,
2333         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2334         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2335         cin0 => \vga_driver_unit|vsync_counter_cout\(0),
2336         cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\,
2337         devclrn => ww_devclrn,
2338         devpor => ww_devpor,
2339         regout => \vga_driver_unit|vsync_counter_1\,
2340         cout0 => \vga_driver_unit|vsync_counter_cout\(1),
2341         cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\);
2342
2343 \vga_driver_unit|vsync_counter_2_\ : stratix_lcell
2344 -- Equation(s):
2345 -- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2346 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2347 -- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1)))
2348 -- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\))
2349
2350 -- pragma translate_off
2351 GENERIC MAP (
2352         cin0_used => "true",
2353         cin1_used => "true",
2354         lut_mask => "a50a",
2355         operation_mode => "arithmetic",
2356         output_mode => "reg_only",
2357         register_cascade_mode => "off",
2358         sum_lutc_input => "cin",
2359         synch_mode => "on")
2360 -- pragma translate_on
2361 PORT MAP (
2362         clk => \clk_pin~combout\,
2363         dataa => \vga_driver_unit|vsync_counter_2\,
2364         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2365         aclr => GND,
2366         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2367         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2368         cin0 => \vga_driver_unit|vsync_counter_cout\(1),
2369         cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\,
2370         devclrn => ww_devclrn,
2371         devpor => ww_devpor,
2372         regout => \vga_driver_unit|vsync_counter_2\,
2373         cout0 => \vga_driver_unit|vsync_counter_cout\(2),
2374         cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\);
2375
2376 \vga_driver_unit|vsync_counter_3_\ : stratix_lcell
2377 -- Equation(s):
2378 -- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2379 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2380 -- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\)
2381 -- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\)
2382
2383 -- pragma translate_off
2384 GENERIC MAP (
2385         cin0_used => "true",
2386         cin1_used => "true",
2387         lut_mask => "5a5f",
2388         operation_mode => "arithmetic",
2389         output_mode => "reg_only",
2390         register_cascade_mode => "off",
2391         sum_lutc_input => "cin",
2392         synch_mode => "on")
2393 -- pragma translate_on
2394 PORT MAP (
2395         clk => \clk_pin~combout\,
2396         dataa => \vga_driver_unit|vsync_counter_3\,
2397         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2398         aclr => GND,
2399         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2400         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2401         cin0 => \vga_driver_unit|vsync_counter_cout\(2),
2402         cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\,
2403         devclrn => ww_devclrn,
2404         devpor => ww_devpor,
2405         regout => \vga_driver_unit|vsync_counter_3\,
2406         cout0 => \vga_driver_unit|vsync_counter_cout\(3),
2407         cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\);
2408
2409 \vga_driver_unit|vsync_counter_4_\ : stratix_lcell
2410 -- Equation(s):
2411 -- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2412 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2413 -- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\))
2414
2415 -- pragma translate_off
2416 GENERIC MAP (
2417         cin0_used => "true",
2418         cin1_used => "true",
2419         lut_mask => "a50a",
2420         operation_mode => "arithmetic",
2421         output_mode => "reg_only",
2422         register_cascade_mode => "off",
2423         sum_lutc_input => "cin",
2424         synch_mode => "on")
2425 -- pragma translate_on
2426 PORT MAP (
2427         clk => \clk_pin~combout\,
2428         dataa => \vga_driver_unit|vsync_counter_4\,
2429         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2430         aclr => GND,
2431         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2432         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2433         cin0 => \vga_driver_unit|vsync_counter_cout\(3),
2434         cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\,
2435         devclrn => ww_devclrn,
2436         devpor => ww_devpor,
2437         regout => \vga_driver_unit|vsync_counter_4\,
2438         cout => \vga_driver_unit|vsync_counter_cout\(4));
2439
2440 \vga_driver_unit|vsync_counter_5_\ : stratix_lcell
2441 -- Equation(s):
2442 -- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2443 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2444 -- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2445 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2446
2447 -- pragma translate_off
2448 GENERIC MAP (
2449         cin_used => "true",
2450         lut_mask => "3c3f",
2451         operation_mode => "arithmetic",
2452         output_mode => "reg_only",
2453         register_cascade_mode => "off",
2454         sum_lutc_input => "cin",
2455         synch_mode => "on")
2456 -- pragma translate_on
2457 PORT MAP (
2458         clk => \clk_pin~combout\,
2459         datab => \vga_driver_unit|vsync_counter_5\,
2460         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2461         aclr => GND,
2462         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2463         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2464         cin => \vga_driver_unit|vsync_counter_cout\(4),
2465         devclrn => ww_devclrn,
2466         devpor => ww_devpor,
2467         regout => \vga_driver_unit|vsync_counter_5\,
2468         cout0 => \vga_driver_unit|vsync_counter_cout\(5),
2469         cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\);
2470
2471 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell
2472 -- Equation(s):
2473 -- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_0\ # !\vga_driver_unit|vsync_counter_2\ # !\vga_driver_unit|vsync_counter_3\
2474
2475 -- pragma translate_off
2476 GENERIC MAP (
2477         lut_mask => "7fff",
2478         operation_mode => "normal",
2479         output_mode => "comb_only",
2480         register_cascade_mode => "off",
2481         sum_lutc_input => "datac",
2482         synch_mode => "off")
2483 -- pragma translate_on
2484 PORT MAP (
2485         dataa => \vga_driver_unit|vsync_counter_3\,
2486         datab => \vga_driver_unit|vsync_counter_2\,
2487         datac => \vga_driver_unit|vsync_counter_0\,
2488         datad => \vga_driver_unit|vsync_counter_1\,
2489         devclrn => ww_devclrn,
2490         devpor => ww_devpor,
2491         combout => \vga_driver_unit|un9_vsync_counterlt9_6\);
2492
2493 \vga_driver_unit|vsync_counter_6_\ : stratix_lcell
2494 -- Equation(s):
2495 -- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2496 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2497 -- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5))
2498 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\)
2499
2500 -- pragma translate_off
2501 GENERIC MAP (
2502         cin0_used => "true",
2503         cin1_used => "true",
2504         cin_used => "true",
2505         lut_mask => "c30c",
2506         operation_mode => "arithmetic",
2507         output_mode => "reg_only",
2508         register_cascade_mode => "off",
2509         sum_lutc_input => "cin",
2510         synch_mode => "on")
2511 -- pragma translate_on
2512 PORT MAP (
2513         clk => \clk_pin~combout\,
2514         datab => \vga_driver_unit|vsync_counter_6\,
2515         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2516         aclr => GND,
2517         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2518         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2519         cin => \vga_driver_unit|vsync_counter_cout\(4),
2520         cin0 => \vga_driver_unit|vsync_counter_cout\(5),
2521         cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\,
2522         devclrn => ww_devclrn,
2523         devpor => ww_devpor,
2524         regout => \vga_driver_unit|vsync_counter_6\,
2525         cout0 => \vga_driver_unit|vsync_counter_cout\(6),
2526         cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\);
2527
2528 \vga_driver_unit|vsync_counter_7_\ : stratix_lcell
2529 -- Equation(s):
2530 -- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2531 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2532 -- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\)
2533 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\)
2534
2535 -- pragma translate_off
2536 GENERIC MAP (
2537         cin0_used => "true",
2538         cin1_used => "true",
2539         cin_used => "true",
2540         lut_mask => "5a5f",
2541         operation_mode => "arithmetic",
2542         output_mode => "reg_only",
2543         register_cascade_mode => "off",
2544         sum_lutc_input => "cin",
2545         synch_mode => "on")
2546 -- pragma translate_on
2547 PORT MAP (
2548         clk => \clk_pin~combout\,
2549         dataa => \vga_driver_unit|vsync_counter_7\,
2550         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2551         aclr => GND,
2552         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2553         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2554         cin => \vga_driver_unit|vsync_counter_cout\(4),
2555         cin0 => \vga_driver_unit|vsync_counter_cout\(6),
2556         cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\,
2557         devclrn => ww_devclrn,
2558         devpor => ww_devpor,
2559         regout => \vga_driver_unit|vsync_counter_7\,
2560         cout0 => \vga_driver_unit|vsync_counter_cout\(7),
2561         cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\);
2562
2563 \vga_driver_unit|vsync_counter_8_\ : stratix_lcell
2564 -- Equation(s):
2565 -- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2566 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2567 -- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7)))
2568 -- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\))
2569
2570 -- pragma translate_off
2571 GENERIC MAP (
2572         cin0_used => "true",
2573         cin1_used => "true",
2574         cin_used => "true",
2575         lut_mask => "a50a",
2576         operation_mode => "arithmetic",
2577         output_mode => "reg_only",
2578         register_cascade_mode => "off",
2579         sum_lutc_input => "cin",
2580         synch_mode => "on")
2581 -- pragma translate_on
2582 PORT MAP (
2583         clk => \clk_pin~combout\,
2584         dataa => \vga_driver_unit|vsync_counter_8\,
2585         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2586         aclr => GND,
2587         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2588         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2589         cin => \vga_driver_unit|vsync_counter_cout\(4),
2590         cin0 => \vga_driver_unit|vsync_counter_cout\(7),
2591         cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\,
2592         devclrn => ww_devclrn,
2593         devpor => ww_devpor,
2594         regout => \vga_driver_unit|vsync_counter_8\,
2595         cout0 => \vga_driver_unit|vsync_counter_cout\(8),
2596         cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\);
2597
2598 \vga_driver_unit|vsync_counter_9_\ : stratix_lcell
2599 -- Equation(s):
2600 -- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $
2601 -- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2602
2603 -- pragma translate_off
2604 GENERIC MAP (
2605         cin0_used => "true",
2606         cin1_used => "true",
2607         cin_used => "true",
2608         lut_mask => "0ff0",
2609         operation_mode => "normal",
2610         output_mode => "reg_only",
2611         register_cascade_mode => "off",
2612         sum_lutc_input => "cin",
2613         synch_mode => "on")
2614 -- pragma translate_on
2615 PORT MAP (
2616         clk => \clk_pin~combout\,
2617         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2618         datad => \vga_driver_unit|vsync_counter_9\,
2619         aclr => GND,
2620         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2621         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2622         cin => \vga_driver_unit|vsync_counter_cout\(4),
2623         cin0 => \vga_driver_unit|vsync_counter_cout\(8),
2624         cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\,
2625         devclrn => ww_devclrn,
2626         devpor => ww_devpor,
2627         regout => \vga_driver_unit|vsync_counter_9\);
2628
2629 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell
2630 -- Equation(s):
2631 -- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_8\ # !\vga_driver_unit|vsync_counter_7\
2632
2633 -- pragma translate_off
2634 GENERIC MAP (
2635         lut_mask => "7fff",
2636         operation_mode => "normal",
2637         output_mode => "comb_only",
2638         register_cascade_mode => "off",
2639         sum_lutc_input => "datac",
2640         synch_mode => "off")
2641 -- pragma translate_on
2642 PORT MAP (
2643         dataa => \vga_driver_unit|vsync_counter_7\,
2644         datab => \vga_driver_unit|vsync_counter_8\,
2645         datac => \vga_driver_unit|vsync_counter_6\,
2646         datad => \vga_driver_unit|vsync_counter_9\,
2647         devclrn => ww_devclrn,
2648         devpor => ww_devpor,
2649         combout => \vga_driver_unit|un9_vsync_counterlt9_5\);
2650
2651 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell
2652 -- Equation(s):
2653 -- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\
2654
2655 -- pragma translate_off
2656 GENERIC MAP (
2657         lut_mask => "ffdf",
2658         operation_mode => "normal",
2659         output_mode => "comb_only",
2660         register_cascade_mode => "off",
2661         sum_lutc_input => "datac",
2662         synch_mode => "off")
2663 -- pragma translate_on
2664 PORT MAP (
2665         dataa => \vga_driver_unit|vsync_counter_5\,
2666         datab => \vga_driver_unit|un9_vsync_counterlt9_6\,
2667         datac => \vga_driver_unit|vsync_counter_4\,
2668         datad => \vga_driver_unit|un9_vsync_counterlt9_5\,
2669         devclrn => ww_devclrn,
2670         devpor => ww_devpor,
2671         combout => \vga_driver_unit|un9_vsync_counterlt9\);
2672
2673 \vga_driver_unit|G_16\ : stratix_lcell
2674 -- Equation(s):
2675 -- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|vsync_state_6\ & !\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_vsync_counterlt9\
2676
2677 -- pragma translate_off
2678 GENERIC MAP (
2679         lut_mask => "01ff",
2680         operation_mode => "normal",
2681         output_mode => "comb_only",
2682         register_cascade_mode => "off",
2683         sum_lutc_input => "datac",
2684         synch_mode => "off")
2685 -- pragma translate_on
2686 PORT MAP (
2687         dataa => \vga_driver_unit|vsync_state_6\,
2688         datab => \vga_driver_unit|vsync_state_0\,
2689         datac => \vga_driver_unit|un6_dly_counter_0_x\,
2690         datad => \vga_driver_unit|un9_vsync_counterlt9\,
2691         devclrn => ww_devclrn,
2692         devpor => ww_devpor,
2693         combout => \vga_driver_unit|G_16_i\);
2694
2695 \vga_driver_unit|vsync_state_5_\ : stratix_lcell
2696 -- Equation(s):
2697 -- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2698
2699 -- pragma translate_off
2700 GENERIC MAP (
2701         lut_mask => "fff0",
2702         operation_mode => "normal",
2703         output_mode => "reg_only",
2704         register_cascade_mode => "off",
2705         sum_lutc_input => "datac",
2706         synch_mode => "on")
2707 -- pragma translate_on
2708 PORT MAP (
2709         clk => \clk_pin~combout\,
2710         datac => \vga_driver_unit|vsync_state_6\,
2711         datad => \vga_driver_unit|vsync_state_0\,
2712         aclr => GND,
2713         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2714         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2715         devclrn => ww_devclrn,
2716         devpor => ww_devpor,
2717         regout => \vga_driver_unit|vsync_state_5\);
2718
2719 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell
2720 -- Equation(s):
2721 -- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_5\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_7\
2722
2723 -- pragma translate_off
2724 GENERIC MAP (
2725         lut_mask => "0001",
2726         operation_mode => "normal",
2727         output_mode => "comb_only",
2728         register_cascade_mode => "off",
2729         sum_lutc_input => "datac",
2730         synch_mode => "off")
2731 -- pragma translate_on
2732 PORT MAP (
2733         dataa => \vga_driver_unit|vsync_counter_5\,
2734         datab => \vga_driver_unit|vsync_counter_6\,
2735         datac => \vga_driver_unit|vsync_counter_8\,
2736         datad => \vga_driver_unit|vsync_counter_7\,
2737         devclrn => ww_devclrn,
2738         devpor => ww_devpor,
2739         combout => \vga_driver_unit|un12_vsync_counter_6\);
2740
2741 \vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell
2742 -- Equation(s):
2743 -- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un12_vsync_counter_7\
2744
2745 -- pragma translate_off
2746 GENERIC MAP (
2747         lut_mask => "f000",
2748         operation_mode => "normal",
2749         output_mode => "comb_only",
2750         register_cascade_mode => "off",
2751         sum_lutc_input => "datac",
2752         synch_mode => "off")
2753 -- pragma translate_on
2754 PORT MAP (
2755         datac => \vga_driver_unit|un12_vsync_counter_6\,
2756         datad => \vga_driver_unit|un12_vsync_counter_7\,
2757         devclrn => ww_devclrn,
2758         devpor => ww_devpor,
2759         combout => \vga_driver_unit|un14_vsync_counter_8\);
2760
2761 \vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
2762 -- Equation(s):
2763 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\)
2764
2765 -- pragma translate_off
2766 GENERIC MAP (
2767         lut_mask => "d0f0",
2768         operation_mode => "normal",
2769         output_mode => "comb_only",
2770         register_cascade_mode => "off",
2771         sum_lutc_input => "datac",
2772         synch_mode => "off")
2773 -- pragma translate_on
2774 PORT MAP (
2775         dataa => \vga_driver_unit|vsync_counter_0\,
2776         datab => \vga_driver_unit|vsync_counter_9\,
2777         datac => \vga_driver_unit|vsync_state_5\,
2778         datad => \vga_driver_unit|un14_vsync_counter_8\,
2779         devclrn => ww_devclrn,
2780         devpor => ww_devpor,
2781         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\);
2782
2783 \vga_driver_unit|vsync_state_3_\ : stratix_lcell
2784 -- Equation(s):
2785 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\)
2786 -- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
2787
2788 -- pragma translate_off
2789 GENERIC MAP (
2790         lut_mask => "70f0",
2791         operation_mode => "normal",
2792         output_mode => "reg_and_comb",
2793         register_cascade_mode => "off",
2794         sum_lutc_input => "qfbk",
2795         synch_mode => "on")
2796 -- pragma translate_on
2797 PORT MAP (
2798         clk => \clk_pin~combout\,
2799         dataa => \vga_driver_unit|vsync_counter_0\,
2800         datab => \vga_driver_unit|vsync_counter_9\,
2801         datac => \vga_driver_unit|vsync_state_1\,
2802         datad => \vga_driver_unit|un14_vsync_counter_8\,
2803         aclr => GND,
2804         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2805         sload => VCC,
2806         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2807         devclrn => ww_devclrn,
2808         devpor => ww_devpor,
2809         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
2810         regout => \vga_driver_unit|vsync_state_3\);
2811
2812 \vga_driver_unit|vsync_state_2_\ : stratix_lcell
2813 -- Equation(s):
2814 -- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_state_3\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un14_vsync_counter_8\, GLOBAL(\clk_pin~combout\), VCC, ,
2815 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2816
2817 -- pragma translate_off
2818 GENERIC MAP (
2819         lut_mask => "8000",
2820         operation_mode => "normal",
2821         output_mode => "reg_only",
2822         register_cascade_mode => "off",
2823         sum_lutc_input => "datac",
2824         synch_mode => "on")
2825 -- pragma translate_on
2826 PORT MAP (
2827         clk => \clk_pin~combout\,
2828         dataa => \vga_driver_unit|vsync_counter_9\,
2829         datab => \vga_driver_unit|vsync_state_3\,
2830         datac => \vga_driver_unit|vsync_counter_0\,
2831         datad => \vga_driver_unit|un14_vsync_counter_8\,
2832         aclr => GND,
2833         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2834         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2835         devclrn => ww_devclrn,
2836         devpor => ww_devpor,
2837         regout => \vga_driver_unit|vsync_state_2\);
2838
2839 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell
2840 -- Equation(s):
2841 -- \vga_driver_unit|un15_vsync_counter_3\ = \vga_driver_unit|vsync_counter_3\ & \vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_0\ & !\vga_driver_unit|vsync_counter_2\
2842
2843 -- pragma translate_off
2844 GENERIC MAP (
2845         lut_mask => "0008",
2846         operation_mode => "normal",
2847         output_mode => "comb_only",
2848         register_cascade_mode => "off",
2849         sum_lutc_input => "datac",
2850         synch_mode => "off")
2851 -- pragma translate_on
2852 PORT MAP (
2853         dataa => \vga_driver_unit|vsync_counter_3\,
2854         datab => \vga_driver_unit|vsync_counter_9\,
2855         datac => \vga_driver_unit|vsync_counter_0\,
2856         datad => \vga_driver_unit|vsync_counter_2\,
2857         devclrn => ww_devclrn,
2858         devpor => ww_devpor,
2859         combout => \vga_driver_unit|un15_vsync_counter_3\);
2860
2861 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell
2862 -- Equation(s):
2863 -- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_4\ & \vga_driver_unit|un15_vsync_counter_3\
2864
2865 -- pragma translate_off
2866 GENERIC MAP (
2867         lut_mask => "0300",
2868         operation_mode => "normal",
2869         output_mode => "comb_only",
2870         register_cascade_mode => "off",
2871         sum_lutc_input => "datac",
2872         synch_mode => "off")
2873 -- pragma translate_on
2874 PORT MAP (
2875         datab => \vga_driver_unit|vsync_counter_1\,
2876         datac => \vga_driver_unit|vsync_counter_4\,
2877         datad => \vga_driver_unit|un15_vsync_counter_3\,
2878         devclrn => ww_devclrn,
2879         devpor => ww_devpor,
2880         combout => \vga_driver_unit|un15_vsync_counter_4\);
2881
2882 \vga_driver_unit|vsync_state_4_\ : stratix_lcell
2883 -- Equation(s):
2884 -- \vga_driver_unit|vsync_state_4\ = DFFEAS(\vga_driver_unit|vsync_state_5\ & !\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un14_vsync_counter_8\, GLOBAL(\clk_pin~combout\), VCC, ,
2885 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2886
2887 -- pragma translate_off
2888 GENERIC MAP (
2889         lut_mask => "2000",
2890         operation_mode => "normal",
2891         output_mode => "reg_only",
2892         register_cascade_mode => "off",
2893         sum_lutc_input => "datac",
2894         synch_mode => "on")
2895 -- pragma translate_on
2896 PORT MAP (
2897         clk => \clk_pin~combout\,
2898         dataa => \vga_driver_unit|vsync_state_5\,
2899         datab => \vga_driver_unit|vsync_counter_9\,
2900         datac => \vga_driver_unit|vsync_counter_0\,
2901         datad => \vga_driver_unit|un14_vsync_counter_8\,
2902         aclr => GND,
2903         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2904         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2905         devclrn => ww_devclrn,
2906         devpor => ww_devpor,
2907         regout => \vga_driver_unit|vsync_state_4\);
2908
2909 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell
2910 -- Equation(s):
2911 -- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_8\
2912
2913 -- pragma translate_off
2914 GENERIC MAP (
2915         lut_mask => "0001",
2916         operation_mode => "normal",
2917         output_mode => "comb_only",
2918         register_cascade_mode => "off",
2919         sum_lutc_input => "datac",
2920         synch_mode => "off")
2921 -- pragma translate_on
2922 PORT MAP (
2923         dataa => \vga_driver_unit|vsync_counter_7\,
2924         datab => \vga_driver_unit|vsync_counter_6\,
2925         datac => \vga_driver_unit|vsync_counter_9\,
2926         datad => \vga_driver_unit|vsync_counter_8\,
2927         devclrn => ww_devclrn,
2928         devpor => ww_devpor,
2929         combout => \vga_driver_unit|un13_vsync_counter_3\);
2930
2931 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell
2932 -- Equation(s):
2933 -- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & (\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\)
2934
2935 -- pragma translate_off
2936 GENERIC MAP (
2937         lut_mask => "a000",
2938         operation_mode => "normal",
2939         output_mode => "comb_only",
2940         register_cascade_mode => "off",
2941         sum_lutc_input => "datac",
2942         synch_mode => "off")
2943 -- pragma translate_on
2944 PORT MAP (
2945         dataa => \vga_driver_unit|vsync_counter_5\,
2946         datac => \vga_driver_unit|vsync_counter_0\,
2947         datad => \vga_driver_unit|un13_vsync_counter_3\,
2948         devclrn => ww_devclrn,
2949         devpor => ww_devpor,
2950         combout => \vga_driver_unit|un13_vsync_counter_4\);
2951
2952 \vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
2953 -- Equation(s):
2954 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un12_vsync_counter_7\ # !\vga_driver_unit|un13_vsync_counter_4\)
2955
2956 -- pragma translate_off
2957 GENERIC MAP (
2958         lut_mask => "0aaa",
2959         operation_mode => "normal",
2960         output_mode => "comb_only",
2961         register_cascade_mode => "off",
2962         sum_lutc_input => "datac",
2963         synch_mode => "off")
2964 -- pragma translate_on
2965 PORT MAP (
2966         dataa => \vga_driver_unit|vsync_state_4\,
2967         datac => \vga_driver_unit|un13_vsync_counter_4\,
2968         datad => \vga_driver_unit|un12_vsync_counter_7\,
2969         devclrn => ww_devclrn,
2970         devpor => ww_devpor,
2971         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\);
2972
2973 \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell
2974 -- Equation(s):
2975 -- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\)
2976
2977 -- pragma translate_off
2978 GENERIC MAP (
2979         lut_mask => "ff4c",
2980         operation_mode => "normal",
2981         output_mode => "comb_only",
2982         register_cascade_mode => "off",
2983         sum_lutc_input => "datac",
2984         synch_mode => "off")
2985 -- pragma translate_on
2986 PORT MAP (
2987         dataa => \vga_driver_unit|un12_vsync_counter_6\,
2988         datab => \vga_driver_unit|vsync_state_2\,
2989         datac => \vga_driver_unit|un15_vsync_counter_4\,
2990         datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\,
2991         devclrn => ww_devclrn,
2992         devpor => ww_devpor,
2993         combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\);
2994
2995 \vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell
2996 -- Equation(s):
2997 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\ & !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\
2998
2999 -- pragma translate_off
3000 GENERIC MAP (
3001         lut_mask => "aaab",
3002         operation_mode => "normal",
3003         output_mode => "comb_only",
3004         register_cascade_mode => "off",
3005         sum_lutc_input => "datac",
3006         synch_mode => "off")
3007 -- pragma translate_on
3008 PORT MAP (
3009         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
3010         datab => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\,
3011         datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
3012         datad => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\,
3013         devclrn => ww_devclrn,
3014         devpor => ww_devpor,
3015         combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\);
3016
3017 \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell
3018 -- Equation(s):
3019 -- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|un15_vsync_counter_4\ & \vga_driver_unit|un12_vsync_counter_6\
3020
3021 -- pragma translate_off
3022 GENERIC MAP (
3023         lut_mask => "c000",
3024         operation_mode => "normal",
3025         output_mode => "comb_only",
3026         register_cascade_mode => "off",
3027         sum_lutc_input => "datac",
3028         synch_mode => "off")
3029 -- pragma translate_on
3030 PORT MAP (
3031         datab => \vga_driver_unit|vsync_state_2\,
3032         datac => \vga_driver_unit|un15_vsync_counter_4\,
3033         datad => \vga_driver_unit|un12_vsync_counter_6\,
3034         devclrn => ww_devclrn,
3035         devpor => ww_devpor,
3036         combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\);
3037
3038 \vga_driver_unit|vsync_state_0_\ : stratix_lcell
3039 -- Equation(s):
3040 -- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\ # !\vga_driver_unit|un6_dly_counter_0_x\ & (\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ #
3041 -- \vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3042
3043 -- pragma translate_off
3044 GENERIC MAP (
3045         lut_mask => "5d0c",
3046         operation_mode => "normal",
3047         output_mode => "reg_only",
3048         register_cascade_mode => "off",
3049         sum_lutc_input => "datac",
3050         synch_mode => "off")
3051 -- pragma translate_on
3052 PORT MAP (
3053         clk => \clk_pin~combout\,
3054         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
3055         datab => \vga_driver_unit|vsync_state_0\,
3056         datac => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
3057         datad => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\,
3058         aclr => GND,
3059         devclrn => ww_devclrn,
3060         devpor => ww_devpor,
3061         regout => \vga_driver_unit|vsync_state_0\);
3062
3063 \vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell
3064 -- Equation(s):
3065 -- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\
3066
3067 -- pragma translate_off
3068 GENERIC MAP (
3069         lut_mask => "ffcc",
3070         operation_mode => "normal",
3071         output_mode => "comb_only",
3072         register_cascade_mode => "off",
3073         sum_lutc_input => "datac",
3074         synch_mode => "off")
3075 -- pragma translate_on
3076 PORT MAP (
3077         datab => \vga_driver_unit|vsync_state_0\,
3078         datad => \vga_driver_unit|vsync_state_6\,
3079         devclrn => ww_devclrn,
3080         devpor => ww_devpor,
3081         combout => \vga_driver_unit|d_set_vsync_counter\);
3082
3083 \vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
3084 -- Equation(s):
3085 -- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = !\vga_driver_unit|d_set_vsync_counter\ & dly_counter(1) & \reset_pin~combout\ & dly_counter(0)
3086
3087 -- pragma translate_off
3088 GENERIC MAP (
3089         lut_mask => "4000",
3090         operation_mode => "normal",
3091         output_mode => "comb_only",
3092         register_cascade_mode => "off",
3093         sum_lutc_input => "datac",
3094         synch_mode => "off")
3095 -- pragma translate_on
3096 PORT MAP (
3097         dataa => \vga_driver_unit|d_set_vsync_counter\,
3098         datab => dly_counter(1),
3099         datac => \reset_pin~combout\,
3100         datad => dly_counter(0),
3101         devclrn => ww_devclrn,
3102         devpor => ww_devpor,
3103         combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\);
3104
3105 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell
3106 -- Equation(s):
3107 -- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_4\
3108
3109 -- pragma translate_off
3110 GENERIC MAP (
3111         lut_mask => "0001",
3112         operation_mode => "normal",
3113         output_mode => "comb_only",
3114         register_cascade_mode => "off",
3115         sum_lutc_input => "datac",
3116         synch_mode => "off")
3117 -- pragma translate_on
3118 PORT MAP (
3119         dataa => \vga_driver_unit|vsync_counter_1\,
3120         datab => \vga_driver_unit|vsync_counter_2\,
3121         datac => \vga_driver_unit|vsync_counter_3\,
3122         datad => \vga_driver_unit|vsync_counter_4\,
3123         devclrn => ww_devclrn,
3124         devpor => ww_devpor,
3125         combout => \vga_driver_unit|un12_vsync_counter_7\);
3126
3127 \vga_driver_unit|vsync_state_1_\ : stratix_lcell
3128 -- Equation(s):
3129 -- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|un12_vsync_counter_7\ & \vga_driver_unit|un13_vsync_counter_4\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|vsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3130
3131 -- pragma translate_off
3132 GENERIC MAP (
3133         lut_mask => "0800",
3134         operation_mode => "normal",
3135         output_mode => "reg_only",
3136         register_cascade_mode => "off",
3137         sum_lutc_input => "datac",
3138         synch_mode => "off")
3139 -- pragma translate_on
3140 PORT MAP (
3141         clk => \clk_pin~combout\,
3142         dataa => \vga_driver_unit|un12_vsync_counter_7\,
3143         datab => \vga_driver_unit|un13_vsync_counter_4\,
3144         datac => \vga_driver_unit|un6_dly_counter_0_x\,
3145         datad => \vga_driver_unit|vsync_state_4\,
3146         aclr => GND,
3147         devclrn => ww_devclrn,
3148         devpor => ww_devpor,
3149         regout => \vga_driver_unit|vsync_state_1\);
3150
3151 \vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
3152 -- Equation(s):
3153 -- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|vsync_state_1\ & dly_counter(1)
3154
3155 -- pragma translate_off
3156 GENERIC MAP (
3157         lut_mask => "0800",
3158         operation_mode => "normal",
3159         output_mode => "comb_only",
3160         register_cascade_mode => "off",
3161         sum_lutc_input => "datac",
3162         synch_mode => "off")
3163 -- pragma translate_on
3164 PORT MAP (
3165         dataa => \reset_pin~combout\,
3166         datab => dly_counter(0),
3167         datac => \vga_driver_unit|vsync_state_1\,
3168         datad => dly_counter(1),
3169         devclrn => ww_devclrn,
3170         devpor => ww_devpor,
3171         combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\);
3172
3173 \vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell
3174 -- Equation(s):
3175 -- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|line_counter_sig_0\
3176 -- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
3177 -- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
3178
3179 -- pragma translate_off
3180 GENERIC MAP (
3181         lut_mask => "6688",
3182         operation_mode => "arithmetic",
3183         output_mode => "comb_only",
3184         register_cascade_mode => "off",
3185         sum_lutc_input => "datac",
3186         synch_mode => "off")
3187 -- pragma translate_on
3188 PORT MAP (
3189         dataa => \vga_driver_unit|d_set_hsync_counter\,
3190         datab => \vga_driver_unit|line_counter_sig_0\,
3191         devclrn => ww_devclrn,
3192         devpor => ww_devpor,
3193         combout => \vga_driver_unit|un1_line_counter_sig_combout\(1),
3194         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
3195         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\);
3196
3197 \vga_driver_unit|line_counter_sig_0_\ : stratix_lcell
3198 -- Equation(s):
3199 -- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3200
3201 -- pragma translate_off
3202 GENERIC MAP (
3203         lut_mask => "ff0f",
3204         operation_mode => "normal",
3205         output_mode => "reg_only",
3206         register_cascade_mode => "off",
3207         sum_lutc_input => "datac",
3208         synch_mode => "on")
3209 -- pragma translate_on
3210 PORT MAP (
3211         clk => \clk_pin~combout\,
3212         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3213         datad => \vga_driver_unit|un1_line_counter_sig_combout\(1),
3214         aclr => GND,
3215         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3216         devclrn => ww_devclrn,
3217         devpor => ww_devpor,
3218         regout => \vga_driver_unit|line_counter_sig_0\);
3219
3220 \vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell
3221 -- Equation(s):
3222 -- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3223 -- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3224
3225 -- pragma translate_off
3226 GENERIC MAP (
3227         lut_mask => "ff88",
3228         operation_mode => "arithmetic",
3229         output_mode => "none",
3230         register_cascade_mode => "off",
3231         sum_lutc_input => "datac",
3232         synch_mode => "off")
3233 -- pragma translate_on
3234 PORT MAP (
3235         dataa => \vga_driver_unit|line_counter_sig_0\,
3236         datab => \vga_driver_unit|d_set_hsync_counter\,
3237         devclrn => ww_devclrn,
3238         devpor => ww_devpor,
3239         combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\,
3240         cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3241         cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\);
3242
3243 \vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell
3244 -- Equation(s):
3245 -- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1)
3246 -- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3247 -- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3248
3249 -- pragma translate_off
3250 GENERIC MAP (
3251         cin0_used => "true",
3252         cin1_used => "true",
3253         lut_mask => "3c7f",
3254         operation_mode => "arithmetic",
3255         output_mode => "comb_only",
3256         register_cascade_mode => "off",
3257         sum_lutc_input => "cin",
3258         synch_mode => "off")
3259 -- pragma translate_on
3260 PORT MAP (
3261         dataa => \vga_driver_unit|line_counter_sig_2\,
3262         datab => \vga_driver_unit|line_counter_sig_1\,
3263         cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3264         cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\,
3265         devclrn => ww_devclrn,
3266         devpor => ww_devpor,
3267         combout => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3268         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3269         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\);
3270
3271 \vga_driver_unit|line_counter_sig_1_\ : stratix_lcell
3272 -- Equation(s):
3273 -- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3274
3275 -- pragma translate_off
3276 GENERIC MAP (
3277         lut_mask => "cfcf",
3278         operation_mode => "normal",
3279         output_mode => "reg_only",
3280         register_cascade_mode => "off",
3281         sum_lutc_input => "datac",
3282         synch_mode => "on")
3283 -- pragma translate_on
3284 PORT MAP (
3285         clk => \clk_pin~combout\,
3286         datab => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3287         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3288         aclr => GND,
3289         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3290         devclrn => ww_devclrn,
3291         devpor => ww_devpor,
3292         regout => \vga_driver_unit|line_counter_sig_1\);
3293
3294 \vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell
3295 -- Equation(s):
3296 -- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1))
3297 -- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3298 -- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3299
3300 -- pragma translate_off
3301 GENERIC MAP (
3302         cin0_used => "true",
3303         cin1_used => "true",
3304         lut_mask => "6a7f",
3305         operation_mode => "arithmetic",
3306         output_mode => "comb_only",
3307         register_cascade_mode => "off",
3308         sum_lutc_input => "cin",
3309         synch_mode => "off")
3310 -- pragma translate_on
3311 PORT MAP (
3312         dataa => \vga_driver_unit|line_counter_sig_2\,
3313         datab => \vga_driver_unit|line_counter_sig_1\,
3314         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
3315         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\,
3316         devclrn => ww_devclrn,
3317         devpor => ww_devpor,
3318         combout => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3319         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3320         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\);
3321
3322 \vga_driver_unit|line_counter_sig_2_\ : stratix_lcell
3323 -- Equation(s):
3324 -- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3325
3326 -- pragma translate_off
3327 GENERIC MAP (
3328         lut_mask => "ff0f",
3329         operation_mode => "normal",
3330         output_mode => "reg_only",
3331         register_cascade_mode => "off",
3332         sum_lutc_input => "datac",
3333         synch_mode => "on")
3334 -- pragma translate_on
3335 PORT MAP (
3336         clk => \clk_pin~combout\,
3337         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3338         datad => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3339         aclr => GND,
3340         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3341         devclrn => ww_devclrn,
3342         devpor => ww_devpor,
3343         regout => \vga_driver_unit|line_counter_sig_2\);
3344
3345 \vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell
3346 -- Equation(s):
3347 -- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(2)
3348 -- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2))
3349 -- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\)
3350
3351 -- pragma translate_off
3352 GENERIC MAP (
3353         cin0_used => "true",
3354         cin1_used => "true",
3355         lut_mask => "c308",
3356         operation_mode => "arithmetic",
3357         output_mode => "comb_only",
3358         register_cascade_mode => "off",
3359         sum_lutc_input => "cin",
3360         synch_mode => "off")
3361 -- pragma translate_on
3362 PORT MAP (
3363         dataa => \vga_driver_unit|line_counter_sig_4\,
3364         datab => \vga_driver_unit|line_counter_sig_3\,
3365         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3366         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\,
3367         devclrn => ww_devclrn,
3368         devpor => ww_devpor,
3369         combout => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3370         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3371         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\);
3372
3373 \vga_driver_unit|line_counter_sig_3_\ : stratix_lcell
3374 -- Equation(s):
3375 -- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3376
3377 -- pragma translate_off
3378 GENERIC MAP (
3379         lut_mask => "f5f5",
3380         operation_mode => "normal",
3381         output_mode => "reg_only",
3382         register_cascade_mode => "off",
3383         sum_lutc_input => "datac",
3384         synch_mode => "on")
3385 -- pragma translate_on
3386 PORT MAP (
3387         clk => \clk_pin~combout\,
3388         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3389         datac => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3390         aclr => GND,
3391         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3392         devclrn => ww_devclrn,
3393         devpor => ww_devpor,
3394         regout => \vga_driver_unit|line_counter_sig_3\);
3395
3396 \vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell
3397 -- Equation(s):
3398 -- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3399 -- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3400 -- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\)
3401
3402 -- pragma translate_off
3403 GENERIC MAP (
3404         cin0_used => "true",
3405         cin1_used => "true",
3406         lut_mask => "c608",
3407         operation_mode => "arithmetic",
3408         output_mode => "comb_only",
3409         register_cascade_mode => "off",
3410         sum_lutc_input => "cin",
3411         synch_mode => "off")
3412 -- pragma translate_on
3413 PORT MAP (
3414         dataa => \vga_driver_unit|line_counter_sig_3\,
3415         datab => \vga_driver_unit|line_counter_sig_4\,
3416         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3417         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\,
3418         devclrn => ww_devclrn,
3419         devpor => ww_devpor,
3420         combout => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3421         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3422         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\);
3423
3424 \vga_driver_unit|line_counter_sig_4_\ : stratix_lcell
3425 -- Equation(s):
3426 -- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3427
3428 -- pragma translate_off
3429 GENERIC MAP (
3430         lut_mask => "ff33",
3431         operation_mode => "normal",
3432         output_mode => "reg_only",
3433         register_cascade_mode => "off",
3434         sum_lutc_input => "datac",
3435         synch_mode => "on")
3436 -- pragma translate_on
3437 PORT MAP (
3438         clk => \clk_pin~combout\,
3439         datab => \vga_driver_unit|un10_line_counter_siglto8\,
3440         datad => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3441         aclr => GND,
3442         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3443         devclrn => ww_devclrn,
3444         devpor => ww_devpor,
3445         regout => \vga_driver_unit|line_counter_sig_4\);
3446
3447 \vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell
3448 -- Equation(s):
3449 -- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ (\vga_driver_unit|un1_line_counter_sig_cout\(4))
3450 -- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3451 -- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3452
3453 -- pragma translate_off
3454 GENERIC MAP (
3455         cin0_used => "true",
3456         cin1_used => "true",
3457         lut_mask => "5a7f",
3458         operation_mode => "arithmetic",
3459         output_mode => "comb_only",
3460         register_cascade_mode => "off",
3461         sum_lutc_input => "cin",
3462         synch_mode => "off")
3463 -- pragma translate_on
3464 PORT MAP (
3465         dataa => \vga_driver_unit|line_counter_sig_5\,
3466         datab => \vga_driver_unit|line_counter_sig_6\,
3467         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3468         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\,
3469         devclrn => ww_devclrn,
3470         devpor => ww_devpor,
3471         combout => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3472         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3473         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\);
3474
3475 \vga_driver_unit|line_counter_sig_5_\ : stratix_lcell
3476 -- Equation(s):
3477 -- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un1_line_counter_sig_combout\(6) & \vga_driver_unit|un10_line_counter_siglto8\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3478
3479 -- pragma translate_off
3480 GENERIC MAP (
3481         lut_mask => "a000",
3482         operation_mode => "normal",
3483         output_mode => "reg_only",
3484         register_cascade_mode => "off",
3485         sum_lutc_input => "datac",
3486         synch_mode => "off")
3487 -- pragma translate_on
3488 PORT MAP (
3489         clk => \clk_pin~combout\,
3490         dataa => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\,
3491         datac => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3492         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3493         aclr => GND,
3494         devclrn => ww_devclrn,
3495         devpor => ww_devpor,
3496         regout => \vga_driver_unit|line_counter_sig_5\);
3497
3498 \vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell
3499 -- Equation(s):
3500 -- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5))
3501 -- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3502 -- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3503
3504 -- pragma translate_off
3505 GENERIC MAP (
3506         cin0_used => "true",
3507         cin1_used => "true",
3508         lut_mask => "6c7f",
3509         operation_mode => "arithmetic",
3510         output_mode => "comb_only",
3511         register_cascade_mode => "off",
3512         sum_lutc_input => "cin",
3513         synch_mode => "off")
3514 -- pragma translate_on
3515 PORT MAP (
3516         dataa => \vga_driver_unit|line_counter_sig_5\,
3517         datab => \vga_driver_unit|line_counter_sig_6\,
3518         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3519         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\,
3520         devclrn => ww_devclrn,
3521         devpor => ww_devpor,
3522         combout => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3523         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3524         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\);
3525
3526 \vga_driver_unit|line_counter_sig_6_\ : stratix_lcell
3527 -- Equation(s):
3528 -- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3529
3530 -- pragma translate_off
3531 GENERIC MAP (
3532         lut_mask => "f0ff",
3533         operation_mode => "normal",
3534         output_mode => "reg_only",
3535         register_cascade_mode => "off",
3536         sum_lutc_input => "datac",
3537         synch_mode => "on")
3538 -- pragma translate_on
3539 PORT MAP (
3540         clk => \clk_pin~combout\,
3541         datac => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3542         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3543         aclr => GND,
3544         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3545         devclrn => ww_devclrn,
3546         devpor => ww_devpor,
3547         regout => \vga_driver_unit|line_counter_sig_6\);
3548
3549 \vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell
3550 -- Equation(s):
3551 -- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|line_counter_sig_7\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(6)
3552
3553 -- pragma translate_off
3554 GENERIC MAP (
3555         cin0_used => "true",
3556         cin1_used => "true",
3557         lut_mask => "c3c3",
3558         operation_mode => "normal",
3559         output_mode => "comb_only",
3560         register_cascade_mode => "off",
3561         sum_lutc_input => "cin",
3562         synch_mode => "off")
3563 -- pragma translate_on
3564 PORT MAP (
3565         datab => \vga_driver_unit|line_counter_sig_7\,
3566         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3567         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\,
3568         devclrn => ww_devclrn,
3569         devpor => ww_devpor,
3570         combout => \vga_driver_unit|un1_line_counter_sig_combout\(8));
3571
3572 \vga_driver_unit|line_counter_sig_7_\ : stratix_lcell
3573 -- Equation(s):
3574 -- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3575
3576 -- pragma translate_off
3577 GENERIC MAP (
3578         lut_mask => "f0ff",
3579         operation_mode => "normal",
3580         output_mode => "reg_only",
3581         register_cascade_mode => "off",
3582         sum_lutc_input => "datac",
3583         synch_mode => "on")
3584 -- pragma translate_on
3585 PORT MAP (
3586         clk => \clk_pin~combout\,
3587         datac => \vga_driver_unit|un1_line_counter_sig_combout\(8),
3588         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3589         aclr => GND,
3590         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3591         devclrn => ww_devclrn,
3592         devpor => ww_devpor,
3593         regout => \vga_driver_unit|line_counter_sig_7\);
3594
3595 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell
3596 -- Equation(s):
3597 -- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_4\ # !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\
3598
3599 -- pragma translate_off
3600 GENERIC MAP (
3601         lut_mask => "5fff",
3602         operation_mode => "normal",
3603         output_mode => "comb_only",
3604         register_cascade_mode => "off",
3605         sum_lutc_input => "datac",
3606         synch_mode => "off")
3607 -- pragma translate_on
3608 PORT MAP (
3609         dataa => \vga_driver_unit|line_counter_sig_3\,
3610         datac => \vga_driver_unit|line_counter_sig_0\,
3611         datad => \vga_driver_unit|line_counter_sig_4\,
3612         devclrn => ww_devclrn,
3613         devpor => ww_devpor,
3614         combout => \vga_driver_unit|un10_line_counter_siglt4_2\);
3615
3616 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell
3617 -- Equation(s):
3618 -- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3619
3620 -- pragma translate_off
3621 GENERIC MAP (
3622         lut_mask => "00f7",
3623         operation_mode => "normal",
3624         output_mode => "comb_only",
3625         register_cascade_mode => "off",
3626         sum_lutc_input => "datac",
3627         synch_mode => "off")
3628 -- pragma translate_on
3629 PORT MAP (
3630         dataa => \vga_driver_unit|line_counter_sig_2\,
3631         datab => \vga_driver_unit|line_counter_sig_1\,
3632         datac => \vga_driver_unit|un10_line_counter_siglt4_2\,
3633         datad => \vga_driver_unit|line_counter_sig_5\,
3634         devclrn => ww_devclrn,
3635         devpor => ww_devpor,
3636         combout => \vga_driver_unit|un10_line_counter_siglto5\);
3637
3638 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell
3639 -- Equation(s):
3640 -- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_7\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_8\
3641
3642 -- pragma translate_off
3643 GENERIC MAP (
3644         lut_mask => "ff7f",
3645         operation_mode => "normal",
3646         output_mode => "comb_only",
3647         register_cascade_mode => "off",
3648         sum_lutc_input => "datac",
3649         synch_mode => "off")
3650 -- pragma translate_on
3651 PORT MAP (
3652         dataa => \vga_driver_unit|line_counter_sig_8\,
3653         datab => \vga_driver_unit|line_counter_sig_6\,
3654         datac => \vga_driver_unit|line_counter_sig_7\,
3655         datad => \vga_driver_unit|un10_line_counter_siglto5\,
3656         devclrn => ww_devclrn,
3657         devpor => ww_devpor,
3658         combout => \vga_driver_unit|un10_line_counter_siglto8\);
3659
3660 \vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell
3661 -- Equation(s):
3662 -- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(7) & \vga_driver_unit|line_counter_sig_7\)
3663
3664 -- pragma translate_off
3665 GENERIC MAP (
3666         cin0_used => "true",
3667         cin1_used => "true",
3668         lut_mask => "c3cc",
3669         operation_mode => "normal",
3670         output_mode => "comb_only",
3671         register_cascade_mode => "off",
3672         sum_lutc_input => "cin",
3673         synch_mode => "off")
3674 -- pragma translate_on
3675 PORT MAP (
3676         datab => \vga_driver_unit|line_counter_sig_8\,
3677         datad => \vga_driver_unit|line_counter_sig_7\,
3678         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3679         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\,
3680         devclrn => ww_devclrn,
3681         devpor => ww_devpor,
3682         combout => \vga_driver_unit|un1_line_counter_sig_combout\(9));
3683
3684 \vga_driver_unit|line_counter_sig_8_\ : stratix_lcell
3685 -- Equation(s):
3686 -- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3687
3688 -- pragma translate_off
3689 GENERIC MAP (
3690         lut_mask => "ff33",
3691         operation_mode => "normal",
3692         output_mode => "reg_only",
3693         register_cascade_mode => "off",
3694         sum_lutc_input => "datac",
3695         synch_mode => "on")
3696 -- pragma translate_on
3697 PORT MAP (
3698         clk => \clk_pin~combout\,
3699         datab => \vga_driver_unit|un10_line_counter_siglto8\,
3700         datad => \vga_driver_unit|un1_line_counter_sig_combout\(9),
3701         aclr => GND,
3702         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3703         devclrn => ww_devclrn,
3704         devpor => ww_devpor,
3705         regout => \vga_driver_unit|line_counter_sig_8\);
3706
3707 \vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3\ : stratix_lcell
3708 -- Equation(s):
3709 -- \vga_control_unit|un17_v_enablelto3\ = \vga_driver_unit|line_counter_sig_3\ & (\vga_driver_unit|line_counter_sig_0\ # \vga_driver_unit|line_counter_sig_1\ # \vga_driver_unit|line_counter_sig_2\)
3710
3711 -- pragma translate_off
3712 GENERIC MAP (
3713         lut_mask => "f0e0",
3714         operation_mode => "normal",
3715         output_mode => "comb_only",
3716         register_cascade_mode => "off",
3717         sum_lutc_input => "datac",
3718         synch_mode => "off")
3719 -- pragma translate_on
3720 PORT MAP (
3721         dataa => \vga_driver_unit|line_counter_sig_0\,
3722         datab => \vga_driver_unit|line_counter_sig_1\,
3723         datac => \vga_driver_unit|line_counter_sig_3\,
3724         datad => \vga_driver_unit|line_counter_sig_2\,
3725         devclrn => ww_devclrn,
3726         devpor => ww_devpor,
3727         combout => \vga_control_unit|un17_v_enablelto3\);
3728
3729 \vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ\ : stratix_lcell
3730 -- Equation(s):
3731 -- \vga_control_unit|b_next_0_sqmuxa_7_4_a\ = !\vga_driver_unit|line_counter_sig_4\ & !\vga_control_unit|un17_v_enablelto3\ & !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\
3732
3733 -- pragma translate_off
3734 GENERIC MAP (
3735         lut_mask => "3337",
3736         operation_mode => "normal",
3737         output_mode => "comb_only",
3738         register_cascade_mode => "off",
3739         sum_lutc_input => "datac",
3740         synch_mode => "off")
3741 -- pragma translate_on
3742 PORT MAP (
3743         dataa => \vga_driver_unit|line_counter_sig_4\,
3744         datab => \vga_driver_unit|line_counter_sig_6\,
3745         datac => \vga_control_unit|un17_v_enablelto3\,
3746         datad => \vga_driver_unit|line_counter_sig_5\,
3747         devclrn => ww_devclrn,
3748         devpor => ww_devpor,
3749         combout => \vga_control_unit|b_next_0_sqmuxa_7_4_a\);
3750
3751 \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0\ : stratix_lcell
3752 -- Equation(s):
3753 -- \vga_control_unit|un13_v_enablelto4_0\ = !\vga_driver_unit|line_counter_sig_2\ & (!\vga_driver_unit|line_counter_sig_4\)
3754
3755 -- pragma translate_off
3756 GENERIC MAP (
3757         lut_mask => "0033",
3758         operation_mode => "normal",
3759         output_mode => "comb_only",
3760         register_cascade_mode => "off",
3761         sum_lutc_input => "datac",
3762         synch_mode => "off")
3763 -- pragma translate_on
3764 PORT MAP (
3765         datab => \vga_driver_unit|line_counter_sig_2\,
3766         datad => \vga_driver_unit|line_counter_sig_4\,
3767         devclrn => ww_devclrn,
3768         devpor => ww_devpor,
3769         combout => \vga_control_unit|un13_v_enablelto4_0\);
3770
3771 \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6\ : stratix_lcell
3772 -- Equation(s):
3773 -- \vga_control_unit|un13_v_enablelto6\ = !\vga_driver_unit|line_counter_sig_3\ & \vga_control_unit|un13_v_enablelto4_0\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\
3774
3775 -- pragma translate_off
3776 GENERIC MAP (
3777         lut_mask => "7f5f",
3778         operation_mode => "normal",
3779         output_mode => "comb_only",
3780         register_cascade_mode => "off",
3781         sum_lutc_input => "datac",
3782         synch_mode => "off")
3783 -- pragma translate_on
3784 PORT MAP (
3785         dataa => \vga_driver_unit|line_counter_sig_5\,
3786         datab => \vga_driver_unit|line_counter_sig_3\,
3787         datac => \vga_driver_unit|line_counter_sig_6\,
3788         datad => \vga_control_unit|un13_v_enablelto4_0\,
3789         devclrn => ww_devclrn,
3790         devpor => ww_devpor,
3791         combout => \vga_control_unit|un13_v_enablelto6\);
3792
3793 \vga_control_unit|b_next_0_sqmuxa_7_4_cZ\ : stratix_lcell
3794 -- Equation(s):
3795 -- \vga_control_unit|b_next_0_sqmuxa_7_4\ = \vga_driver_unit|line_counter_sig_7\ & (\vga_control_unit|b_next_0_sqmuxa_7_4_a\) # !\vga_driver_unit|line_counter_sig_7\ & (\vga_driver_unit|line_counter_sig_8\ # !\vga_control_unit|un13_v_enablelto6\)
3796
3797 -- pragma translate_off
3798 GENERIC MAP (
3799         lut_mask => "e2f3",
3800         operation_mode => "normal",
3801         output_mode => "comb_only",
3802         register_cascade_mode => "off",
3803         sum_lutc_input => "datac",
3804         synch_mode => "off")
3805 -- pragma translate_on
3806 PORT MAP (
3807         dataa => \vga_driver_unit|line_counter_sig_8\,
3808         datab => \vga_driver_unit|line_counter_sig_7\,
3809         datac => \vga_control_unit|b_next_0_sqmuxa_7_4_a\,
3810         datad => \vga_control_unit|un13_v_enablelto6\,
3811         devclrn => ww_devclrn,
3812         devpor => ww_devpor,
3813         combout => \vga_control_unit|b_next_0_sqmuxa_7_4\);
3814
3815 \vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
3816 -- Equation(s):
3817 -- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = !\vga_driver_unit|hsync_state_1\ & dly_counter(1) & \reset_pin~combout\ & dly_counter(0)
3818
3819 -- pragma translate_off
3820 GENERIC MAP (
3821         lut_mask => "4000",
3822         operation_mode => "normal",
3823         output_mode => "comb_only",
3824         register_cascade_mode => "off",
3825         sum_lutc_input => "datac",
3826         synch_mode => "off")
3827 -- pragma translate_on
3828 PORT MAP (
3829         dataa => \vga_driver_unit|hsync_state_1\,
3830         datab => dly_counter(1),
3831         datac => \reset_pin~combout\,
3832         datad => dly_counter(0),
3833         devclrn => ww_devclrn,
3834         devpor => ww_devpor,
3835         combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\);
3836
3837 \vga_driver_unit|column_counter_sig_0_\ : stratix_lcell
3838 -- Equation(s):
3839 -- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
3840
3841 -- pragma translate_off
3842 GENERIC MAP (
3843         lut_mask => "0fff",
3844         operation_mode => "normal",
3845         output_mode => "reg_only",
3846         register_cascade_mode => "off",
3847         sum_lutc_input => "datac",
3848         synch_mode => "on")
3849 -- pragma translate_on
3850 PORT MAP (
3851         clk => \clk_pin~combout\,
3852         datac => \vga_driver_unit|column_counter_sig_0\,
3853         datad => \vga_driver_unit|un10_column_counter_siglto9\,
3854         aclr => GND,
3855         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
3856         devclrn => ww_devclrn,
3857         devpor => ww_devpor,
3858         regout => \vga_driver_unit|column_counter_sig_0\);
3859
3860 \vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell
3861 -- Equation(s):
3862 -- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_1\ $ \vga_driver_unit|column_counter_sig_0\
3863 -- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
3864 -- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
3865
3866 -- pragma translate_off
3867 GENERIC MAP (
3868         lut_mask => "6688",
3869         operation_mode => "arithmetic",
3870         output_mode => "comb_only",
3871         register_cascade_mode => "off",
3872         sum_lutc_input => "datac",
3873         synch_mode => "off")
3874 -- pragma translate_on
3875 PORT MAP (
3876         dataa => \vga_driver_unit|column_counter_sig_1\,
3877         datab => \vga_driver_unit|column_counter_sig_0\,
3878         devclrn => ww_devclrn,
3879         devpor => ww_devpor,
3880         combout => \vga_driver_unit|un2_column_counter_next_combout\(1),
3881         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
3882         cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\);
3883
3884 \vga_driver_unit|column_counter_sig_1_\ : stratix_lcell
3885 -- Equation(s):
3886 -- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
3887
3888 -- pragma translate_off
3889 GENERIC MAP (
3890         lut_mask => "f0ff",
3891         operation_mode => "normal",
3892         output_mode => "reg_only",
3893         register_cascade_mode => "off",
3894         sum_lutc_input => "datac",
3895         synch_mode => "on")
3896 -- pragma translate_on
3897 PORT MAP (
3898         clk => \clk_pin~combout\,
3899         datac => \vga_driver_unit|un2_column_counter_next_combout\(1),
3900         datad => \vga_driver_unit|un10_column_counter_siglto9\,
3901         aclr => GND,
3902         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
3903         devclrn => ww_devclrn,
3904         devpor => ww_devpor,
3905         regout => \vga_driver_unit|column_counter_sig_1\);
3906
3907 \vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell
3908 -- Equation(s):
3909 -- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1))
3910 -- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
3911 -- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
3912
3913 -- pragma translate_off
3914 GENERIC MAP (
3915         cin0_used => "true",
3916         cin1_used => "true",
3917         lut_mask => "6c7f",
3918         operation_mode => "arithmetic",
3919         output_mode => "comb_only",
3920         register_cascade_mode => "off",
3921         sum_lutc_input => "cin",
3922         synch_mode => "off")
3923 -- pragma translate_on
3924 PORT MAP (
3925         dataa => \vga_driver_unit|column_counter_sig_2\,
3926         datab => \vga_driver_unit|column_counter_sig_3\,
3927         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
3928         cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\,
3929         devclrn => ww_devclrn,
3930         devpor => ww_devpor,
3931         combout => \vga_driver_unit|un2_column_counter_next_combout\(3),
3932         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
3933         cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\);
3934
3935 \vga_driver_unit|column_counter_sig_3_\ : stratix_lcell
3936 -- Equation(s):
3937 -- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
3938
3939 -- pragma translate_off
3940 GENERIC MAP (
3941         lut_mask => "f0ff",
3942         operation_mode => "normal",
3943         output_mode => "reg_only",
3944         register_cascade_mode => "off",
3945         sum_lutc_input => "datac",
3946         synch_mode => "on")
3947 -- pragma translate_on
3948 PORT MAP (
3949         clk => \clk_pin~combout\,
3950         datac => \vga_driver_unit|un2_column_counter_next_combout\(3),
3951         datad => \vga_driver_unit|un10_column_counter_siglto9\,
3952         aclr => GND,
3953         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
3954         devclrn => ww_devclrn,
3955         devpor => ww_devpor,
3956         regout => \vga_driver_unit|column_counter_sig_3\);
3957
3958 \vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell
3959 -- Equation(s):
3960 -- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
3961 -- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
3962
3963 -- pragma translate_off
3964 GENERIC MAP (
3965         lut_mask => "ff88",
3966         operation_mode => "arithmetic",
3967         output_mode => "none",
3968         register_cascade_mode => "off",
3969         sum_lutc_input => "datac",
3970         synch_mode => "off")
3971 -- pragma translate_on
3972 PORT MAP (
3973         dataa => \vga_driver_unit|column_counter_sig_0\,
3974         datab => \vga_driver_unit|column_counter_sig_1\,
3975         devclrn => ww_devclrn,
3976         devpor => ww_devpor,
3977         combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\,
3978         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
3979         cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\);
3980
3981 \vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell
3982 -- Equation(s):
3983 -- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0))
3984 -- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
3985 -- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
3986
3987 -- pragma translate_off
3988 GENERIC MAP (
3989         cin0_used => "true",
3990         cin1_used => "true",
3991         lut_mask => "5a7f",
3992         operation_mode => "arithmetic",
3993         output_mode => "comb_only",
3994         register_cascade_mode => "off",
3995         sum_lutc_input => "cin",
3996         synch_mode => "off")
3997 -- pragma translate_on
3998 PORT MAP (
3999         dataa => \vga_driver_unit|column_counter_sig_2\,
4000         datab => \vga_driver_unit|column_counter_sig_3\,
4001         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
4002         cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\,
4003         devclrn => ww_devclrn,
4004         devpor => ww_devpor,
4005         combout => \vga_driver_unit|un2_column_counter_next_combout\(2),
4006         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
4007         cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\);
4008
4009 \vga_driver_unit|column_counter_sig_2_\ : stratix_lcell
4010 -- Equation(s):
4011 -- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
4012
4013 -- pragma translate_off
4014 GENERIC MAP (
4015         lut_mask => "ccff",
4016         operation_mode => "normal",
4017         output_mode => "reg_only",
4018         register_cascade_mode => "off",
4019         sum_lutc_input => "datac",
4020         synch_mode => "on")
4021 -- pragma translate_on
4022 PORT MAP (
4023         clk => \clk_pin~combout\,
4024         datab => \vga_driver_unit|un2_column_counter_next_combout\(2),
4025         datad => \vga_driver_unit|un10_column_counter_siglto9\,
4026         aclr => GND,
4027         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
4028         devclrn => ww_devclrn,
4029         devpor => ww_devpor,
4030         regout => \vga_driver_unit|column_counter_sig_2\);
4031
4032 \vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell
4033 -- Equation(s):
4034 -- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
4035 -- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
4036 -- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\)
4037
4038 -- pragma translate_off
4039 GENERIC MAP (
4040         cin0_used => "true",
4041         cin1_used => "true",
4042         lut_mask => "a608",
4043         operation_mode => "arithmetic",
4044         output_mode => "comb_only",
4045         register_cascade_mode => "off",
4046         sum_lutc_input => "cin",
4047         synch_mode => "off")
4048 -- pragma translate_on
4049 PORT MAP (
4050         dataa => \vga_driver_unit|column_counter_sig_5\,
4051         datab => \vga_driver_unit|column_counter_sig_4\,
4052         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
4053         cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\,
4054         devclrn => ww_devclrn,
4055         devpor => ww_devpor,
4056         combout => \vga_driver_unit|un2_column_counter_next_combout\(5),
4057         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
4058         cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\);
4059
4060 \vga_driver_unit|column_counter_sig_5_\ : stratix_lcell
4061 -- Equation(s):
4062 -- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
4063
4064 -- pragma translate_off
4065 GENERIC MAP (
4066         lut_mask => "afaf",
4067         operation_mode => "normal",
4068         output_mode => "reg_only",
4069         register_cascade_mode => "off",
4070         sum_lutc_input => "datac",
4071         synch_mode => "on")
4072 -- pragma translate_on
4073 PORT MAP (
4074         clk => \clk_pin~combout\,
4075         dataa => \vga_driver_unit|un2_column_counter_next_combout\(5),
4076         datac => \vga_driver_unit|un10_column_counter_siglto9\,
4077         aclr => GND,
4078         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
4079         devclrn => ww_devclrn,
4080         devpor => ww_devpor,
4081         regout => \vga_driver_unit|column_counter_sig_5\);
4082
4083 \vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell
4084 -- Equation(s):
4085 -- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ (!\vga_driver_unit|un2_column_counter_next_cout\(2))
4086 -- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_4\ & \vga_driver_unit|column_counter_sig_5\ & !\vga_driver_unit|un2_column_counter_next_cout\(2))
4087 -- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_4\ & \vga_driver_unit|column_counter_sig_5\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\)
4088
4089 -- pragma translate_off
4090 GENERIC MAP (
4091         cin0_used => "true",
4092         cin1_used => "true",
4093         lut_mask => "a508",
4094         operation_mode => "arithmetic",
4095         output_mode => "comb_only",
4096         register_cascade_mode => "off",
4097         sum_lutc_input => "cin",
4098         synch_mode => "off")
4099 -- pragma translate_on
4100 PORT MAP (
4101         dataa => \vga_driver_unit|column_counter_sig_4\,
4102         datab => \vga_driver_unit|column_counter_sig_5\,
4103         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
4104         cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\,
4105         devclrn => ww_devclrn,
4106         devpor => ww_devpor,
4107         combout => \vga_driver_unit|un2_column_counter_next_combout\(4),
4108         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
4109         cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\);
4110
4111 \vga_driver_unit|column_counter_sig_4_\ : stratix_lcell
4112 -- Equation(s):
4113 -- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
4114
4115 -- pragma translate_off
4116 GENERIC MAP (
4117         lut_mask => "f0ff",
4118         operation_mode => "normal",
4119         output_mode => "reg_only",
4120         register_cascade_mode => "off",
4121         sum_lutc_input => "datac",
4122         synch_mode => "on")
4123 -- pragma translate_on
4124 PORT MAP (
4125         clk => \clk_pin~combout\,
4126         datac => \vga_driver_unit|un2_column_counter_next_combout\(4),
4127         datad => \vga_driver_unit|un10_column_counter_siglto9\,
4128         aclr => GND,
4129         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
4130         devclrn => ww_devclrn,
4131         devpor => ww_devpor,
4132         regout => \vga_driver_unit|column_counter_sig_4\);
4133
4134 \vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell
4135 -- Equation(s):
4136 -- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ (\vga_driver_unit|un2_column_counter_next_cout\(4))
4137 -- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
4138 -- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
4139
4140 -- pragma translate_off
4141 GENERIC MAP (
4142         cin0_used => "true",
4143         cin1_used => "true",
4144         lut_mask => "5a7f",
4145         operation_mode => "arithmetic",
4146         output_mode => "comb_only",
4147         register_cascade_mode => "off",
4148         sum_lutc_input => "cin",
4149         synch_mode => "off")
4150 -- pragma translate_on
4151 PORT MAP (
4152         dataa => \vga_driver_unit|column_counter_sig_6\,
4153         datab => \vga_driver_unit|column_counter_sig_7\,
4154         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
4155         cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\,
4156         devclrn => ww_devclrn,
4157         devpor => ww_devpor,
4158         combout => \vga_driver_unit|un2_column_counter_next_combout\(6),
4159         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
4160         cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\);
4161
4162 \vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell
4163 -- Equation(s):
4164 -- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\
4165
4166 -- pragma translate_off
4167 GENERIC MAP (
4168         cin0_used => "true",
4169         cin1_used => "true",
4170         lut_mask => "f00f",
4171         operation_mode => "normal",
4172         output_mode => "comb_only",
4173         register_cascade_mode => "off",
4174         sum_lutc_input => "cin",
4175         synch_mode => "off")
4176 -- pragma translate_on
4177 PORT MAP (
4178         datad => \vga_driver_unit|column_counter_sig_8\,
4179         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
4180         cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\,
4181         devclrn => ww_devclrn,
4182         devpor => ww_devpor,
4183         combout => \vga_driver_unit|un2_column_counter_next_combout\(8));
4184
4185 \vga_driver_unit|column_counter_sig_8_\ : stratix_lcell
4186 -- Equation(s):
4187 -- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un2_column_counter_next_combout\(8) & \vga_driver_unit|un10_column_counter_siglto9\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4188
4189 -- pragma translate_off
4190 GENERIC MAP (
4191         lut_mask => "a000",
4192         operation_mode => "normal",
4193         output_mode => "reg_only",
4194         register_cascade_mode => "off",
4195         sum_lutc_input => "datac",
4196         synch_mode => "off")
4197 -- pragma translate_on
4198 PORT MAP (
4199         clk => \clk_pin~combout\,
4200         dataa => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
4201         datac => \vga_driver_unit|un2_column_counter_next_combout\(8),
4202         datad => \vga_driver_unit|un10_column_counter_siglto9\,
4203         aclr => GND,
4204         devclrn => ww_devclrn,
4205         devpor => ww_devpor,
4206         regout => \vga_driver_unit|column_counter_sig_8\);
4207
4208 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4\ : stratix_lcell
4209 -- Equation(s):
4210 -- \vga_driver_unit|un10_column_counter_siglt6_4\ = !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_0\ # !\vga_driver_unit|column_counter_sig_3\
4211
4212 -- pragma translate_off
4213 GENERIC MAP (
4214         lut_mask => "7fff",
4215         operation_mode => "normal",
4216         output_mode => "comb_only",
4217         register_cascade_mode => "off",
4218         sum_lutc_input => "datac",
4219         synch_mode => "off")
4220 -- pragma translate_on
4221 PORT MAP (
4222         dataa => \vga_driver_unit|column_counter_sig_3\,
4223         datab => \vga_driver_unit|column_counter_sig_0\,
4224         datac => \vga_driver_unit|column_counter_sig_2\,
4225         datad => \vga_driver_unit|column_counter_sig_1\,
4226         devclrn => ww_devclrn,
4227         devpor => ww_devpor,
4228         combout => \vga_driver_unit|un10_column_counter_siglt6_4\);
4229
4230 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell
4231 -- Equation(s):
4232 -- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_4\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_5\
4233
4234 -- pragma translate_off
4235 GENERIC MAP (
4236         lut_mask => "ff7f",
4237         operation_mode => "normal",
4238         output_mode => "comb_only",
4239         register_cascade_mode => "off",
4240         sum_lutc_input => "datac",
4241         synch_mode => "off")
4242 -- pragma translate_on
4243 PORT MAP (
4244         dataa => \vga_driver_unit|column_counter_sig_5\,
4245         datab => \vga_driver_unit|column_counter_sig_4\,
4246         datac => \vga_driver_unit|column_counter_sig_6\,
4247         datad => \vga_driver_unit|un10_column_counter_siglt6_4\,
4248         devclrn => ww_devclrn,
4249         devpor => ww_devpor,
4250         combout => \vga_driver_unit|un10_column_counter_siglt6\);
4251
4252 \vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell
4253 -- Equation(s):
4254 -- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5))
4255 -- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
4256 -- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
4257
4258 -- pragma translate_off
4259 GENERIC MAP (
4260         cin0_used => "true",
4261         cin1_used => "true",
4262         lut_mask => "6c7f",
4263         operation_mode => "arithmetic",
4264         output_mode => "comb_only",
4265         register_cascade_mode => "off",
4266         sum_lutc_input => "cin",
4267         synch_mode => "off")
4268 -- pragma translate_on
4269 PORT MAP (
4270         dataa => \vga_driver_unit|column_counter_sig_6\,
4271         datab => \vga_driver_unit|column_counter_sig_7\,
4272         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
4273         cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\,
4274         devclrn => ww_devclrn,
4275         devpor => ww_devpor,
4276         combout => \vga_driver_unit|un2_column_counter_next_combout\(7),
4277         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
4278         cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\);
4279
4280 \vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell
4281 -- Equation(s):
4282 -- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un2_column_counter_next_cout\(7))
4283
4284 -- pragma translate_off
4285 GENERIC MAP (
4286         cin0_used => "true",
4287         cin1_used => "true",
4288         lut_mask => "c6c6",
4289         operation_mode => "normal",
4290         output_mode => "comb_only",
4291         register_cascade_mode => "off",
4292         sum_lutc_input => "cin",
4293         synch_mode => "off")
4294 -- pragma translate_on
4295 PORT MAP (
4296         dataa => \vga_driver_unit|column_counter_sig_8\,
4297         datab => \vga_driver_unit|column_counter_sig_9\,
4298         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
4299         cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\,
4300         devclrn => ww_devclrn,
4301         devpor => ww_devpor,
4302         combout => \vga_driver_unit|un2_column_counter_next_combout\(9));
4303
4304 \vga_driver_unit|column_counter_sig_9_\ : stratix_lcell
4305 -- Equation(s):
4306 -- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
4307
4308 -- pragma translate_off
4309 GENERIC MAP (
4310         lut_mask => "cfcf",
4311         operation_mode => "normal",
4312         output_mode => "reg_only",
4313         register_cascade_mode => "off",
4314         sum_lutc_input => "datac",
4315         synch_mode => "on")
4316 -- pragma translate_on
4317 PORT MAP (
4318         clk => \clk_pin~combout\,
4319         datab => \vga_driver_unit|un2_column_counter_next_combout\(9),
4320         datac => \vga_driver_unit|un10_column_counter_siglto9\,
4321         aclr => GND,
4322         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
4323         devclrn => ww_devclrn,
4324         devpor => ww_devpor,
4325         regout => \vga_driver_unit|column_counter_sig_9\);
4326
4327 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell
4328 -- Equation(s):
4329 -- \vga_driver_unit|un10_column_counter_siglto9\ = !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & \vga_driver_unit|un10_column_counter_siglt6\ # !\vga_driver_unit|column_counter_sig_9\
4330
4331 -- pragma translate_off
4332 GENERIC MAP (
4333         lut_mask => "10ff",
4334         operation_mode => "normal",
4335         output_mode => "comb_only",
4336         register_cascade_mode => "off",
4337         sum_lutc_input => "datac",
4338         synch_mode => "off")
4339 -- pragma translate_on
4340 PORT MAP (
4341         dataa => \vga_driver_unit|column_counter_sig_8\,
4342         datab => \vga_driver_unit|column_counter_sig_7\,
4343         datac => \vga_driver_unit|un10_column_counter_siglt6\,
4344         datad => \vga_driver_unit|column_counter_sig_9\,
4345         devclrn => ww_devclrn,
4346         devpor => ww_devpor,
4347         combout => \vga_driver_unit|un10_column_counter_siglto9\);
4348
4349 \vga_driver_unit|column_counter_sig_7_\ : stratix_lcell
4350 -- Equation(s):
4351 -- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|un2_column_counter_next_combout\(7), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4352
4353 -- pragma translate_off
4354 GENERIC MAP (
4355         lut_mask => "c000",
4356         operation_mode => "normal",
4357         output_mode => "reg_only",
4358         register_cascade_mode => "off",
4359         sum_lutc_input => "datac",
4360         synch_mode => "off")
4361 -- pragma translate_on
4362 PORT MAP (
4363         clk => \clk_pin~combout\,
4364         datab => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
4365         datac => \vga_driver_unit|un10_column_counter_siglto9\,
4366         datad => \vga_driver_unit|un2_column_counter_next_combout\(7),
4367         aclr => GND,
4368         devclrn => ww_devclrn,
4369         devpor => ww_devpor,
4370         regout => \vga_driver_unit|column_counter_sig_7\);
4371
4372 \vga_driver_unit|column_counter_sig_6_\ : stratix_lcell
4373 -- Equation(s):
4374 -- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
4375
4376 -- pragma translate_off
4377 GENERIC MAP (
4378         lut_mask => "aaff",
4379         operation_mode => "normal",
4380         output_mode => "reg_only",
4381         register_cascade_mode => "off",
4382         sum_lutc_input => "datac",
4383         synch_mode => "on")
4384 -- pragma translate_on
4385 PORT MAP (
4386         clk => \clk_pin~combout\,
4387         dataa => \vga_driver_unit|un2_column_counter_next_combout\(6),
4388         datad => \vga_driver_unit|un10_column_counter_siglto9\,
4389         aclr => GND,
4390         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
4391         devclrn => ww_devclrn,
4392         devpor => ww_devpor,
4393         regout => \vga_driver_unit|column_counter_sig_6\);
4394
4395 \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2\ : stratix_lcell
4396 -- Equation(s):
4397 -- \vga_control_unit|un5_v_enablelt2\ = \vga_driver_unit|column_counter_sig_2\ # \vga_driver_unit|column_counter_sig_1\ # \vga_driver_unit|column_counter_sig_0\
4398
4399 -- pragma translate_off
4400 GENERIC MAP (
4401         lut_mask => "ffee",
4402         operation_mode => "normal",
4403         output_mode => "comb_only",
4404         register_cascade_mode => "off",
4405         sum_lutc_input => "datac",
4406         synch_mode => "off")
4407 -- pragma translate_on
4408 PORT MAP (
4409         dataa => \vga_driver_unit|column_counter_sig_2\,
4410         datab => \vga_driver_unit|column_counter_sig_1\,
4411         datad => \vga_driver_unit|column_counter_sig_0\,
4412         devclrn => ww_devclrn,
4413         devpor => ww_devpor,
4414         combout => \vga_control_unit|un5_v_enablelt2\);
4415
4416 \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5\ : stratix_lcell
4417 -- Equation(s):
4418 -- \vga_control_unit|un5_v_enablelto5\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_5\ # \vga_control_unit|un5_v_enablelt2\ & \vga_driver_unit|column_counter_sig_3\
4419
4420 -- pragma translate_off
4421 GENERIC MAP (
4422         lut_mask => "fefc",
4423         operation_mode => "normal",
4424         output_mode => "comb_only",
4425         register_cascade_mode => "off",
4426         sum_lutc_input => "datac",
4427         synch_mode => "off")
4428 -- pragma translate_on
4429 PORT MAP (
4430         dataa => \vga_control_unit|un5_v_enablelt2\,
4431         datab => \vga_driver_unit|column_counter_sig_4\,
4432         datac => \vga_driver_unit|column_counter_sig_5\,
4433         datad => \vga_driver_unit|column_counter_sig_3\,
4434         devclrn => ww_devclrn,
4435         devpor => ww_devpor,
4436         combout => \vga_control_unit|un5_v_enablelto5\);
4437
4438 \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
4439 -- Equation(s):
4440 -- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_4\ & !\vga_driver_unit|vsync_state_5\
4441
4442 -- pragma translate_off
4443 GENERIC MAP (
4444         lut_mask => "ff03",
4445         operation_mode => "normal",
4446         output_mode => "comb_only",
4447         register_cascade_mode => "off",
4448         sum_lutc_input => "datac",
4449         synch_mode => "off")
4450 -- pragma translate_on
4451 PORT MAP (
4452         datab => \vga_driver_unit|vsync_state_4\,
4453         datac => \vga_driver_unit|vsync_state_5\,
4454         datad => \vga_driver_unit|un6_dly_counter_0_x\,
4455         devclrn => ww_devclrn,
4456         devpor => ww_devpor,
4457         combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\);
4458
4459 \vga_driver_unit|h_enable_sig_Z\ : stratix_lcell
4460 -- Equation(s):
4461 -- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
4462
4463 -- pragma translate_off
4464 GENERIC MAP (
4465         lut_mask => "fff0",
4466         operation_mode => "normal",
4467         output_mode => "reg_only",
4468         register_cascade_mode => "off",
4469         sum_lutc_input => "datac",
4470         synch_mode => "on")
4471 -- pragma translate_on
4472 PORT MAP (
4473         clk => \clk_pin~combout\,
4474         datac => \vga_driver_unit|vsync_state_1\,
4475         datad => \vga_driver_unit|vsync_state_3\,
4476         aclr => GND,
4477         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
4478         ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\,
4479         devclrn => ww_devclrn,
4480         devpor => ww_devpor,
4481         regout => \vga_driver_unit|h_enable_sig\);
4482
4483 \vga_control_unit|b_next_0_sqmuxa_7_2_cZ\ : stratix_lcell
4484 -- Equation(s):
4485 -- \vga_control_unit|b_next_0_sqmuxa_7_2\ = !\vga_driver_unit|line_counter_sig_8\ & \vga_driver_unit|h_enable_sig\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_9\
4486
4487 -- pragma translate_off
4488 GENERIC MAP (
4489         lut_mask => "0004",
4490         operation_mode => "normal",
4491         output_mode => "comb_only",
4492         register_cascade_mode => "off",
4493         sum_lutc_input => "datac",
4494         synch_mode => "off")
4495 -- pragma translate_on
4496 PORT MAP (
4497         dataa => \vga_driver_unit|line_counter_sig_8\,
4498         datab => \vga_driver_unit|h_enable_sig\,
4499         datac => \vga_driver_unit|column_counter_sig_8\,
4500         datad => \vga_driver_unit|column_counter_sig_9\,
4501         devclrn => ww_devclrn,
4502         devpor => ww_devpor,
4503         combout => \vga_control_unit|b_next_0_sqmuxa_7_2\);
4504
4505 \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4\ : stratix_lcell
4506 -- Equation(s):
4507 -- \vga_control_unit|un9_v_enablelto4\ = !\vga_driver_unit|column_counter_sig_3\ & (!\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_4\)
4508
4509 -- pragma translate_off
4510 GENERIC MAP (
4511         lut_mask => "0005",
4512         operation_mode => "normal",
4513         output_mode => "comb_only",
4514         register_cascade_mode => "off",
4515         sum_lutc_input => "datac",
4516         synch_mode => "off")
4517 -- pragma translate_on
4518 PORT MAP (
4519         dataa => \vga_driver_unit|column_counter_sig_3\,
4520         datac => \vga_driver_unit|column_counter_sig_2\,
4521         datad => \vga_driver_unit|column_counter_sig_4\,
4522         devclrn => ww_devclrn,
4523         devpor => ww_devpor,
4524         combout => \vga_control_unit|un9_v_enablelto4\);
4525
4526 \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6\ : stratix_lcell
4527 -- Equation(s):
4528 -- \vga_control_unit|un9_v_enablelto6\ = \vga_control_unit|un9_v_enablelto4\ # !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\
4529
4530 -- pragma translate_off
4531 GENERIC MAP (
4532         lut_mask => "ff77",
4533         operation_mode => "normal",
4534         output_mode => "comb_only",
4535         register_cascade_mode => "off",
4536         sum_lutc_input => "datac",
4537         synch_mode => "off")
4538 -- pragma translate_on
4539 PORT MAP (
4540         dataa => \vga_driver_unit|column_counter_sig_6\,
4541         datab => \vga_driver_unit|column_counter_sig_5\,
4542         datad => \vga_control_unit|un9_v_enablelto4\,
4543         devclrn => ww_devclrn,
4544         devpor => ww_devpor,
4545         combout => \vga_control_unit|un9_v_enablelto6\);
4546
4547 \vga_control_unit|b_next_0_sqmuxa_7_3_cZ\ : stratix_lcell
4548 -- Equation(s):
4549 -- \vga_control_unit|b_next_0_sqmuxa_7_3\ = \vga_control_unit|b_next_0_sqmuxa_7_2\ & (\vga_driver_unit|column_counter_sig_9\ # \vga_driver_unit|column_counter_sig_7\ # !\vga_control_unit|un9_v_enablelto6\)
4550
4551 -- pragma translate_off
4552 GENERIC MAP (
4553         lut_mask => "c8cc",
4554         operation_mode => "normal",
4555         output_mode => "comb_only",
4556         register_cascade_mode => "off",
4557         sum_lutc_input => "datac",
4558         synch_mode => "off")
4559 -- pragma translate_on
4560 PORT MAP (
4561         dataa => \vga_driver_unit|column_counter_sig_9\,
4562         datab => \vga_control_unit|b_next_0_sqmuxa_7_2\,
4563         datac => \vga_driver_unit|column_counter_sig_7\,
4564         datad => \vga_control_unit|un9_v_enablelto6\,
4565         devclrn => ww_devclrn,
4566         devpor => ww_devpor,
4567         combout => \vga_control_unit|b_next_0_sqmuxa_7_3\);
4568
4569 \vga_control_unit|b_next_0_sqmuxa_7_5_cZ\ : stratix_lcell
4570 -- Equation(s):
4571 -- \vga_control_unit|b_next_0_sqmuxa_7_5\ = \vga_control_unit|b_next_0_sqmuxa_7_3\ & (!\vga_control_unit|un5_v_enablelto5\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
4572
4573 -- pragma translate_off
4574 GENERIC MAP (
4575         lut_mask => "7f00",
4576         operation_mode => "normal",
4577         output_mode => "comb_only",
4578         register_cascade_mode => "off",
4579         sum_lutc_input => "datac",
4580         synch_mode => "off")
4581 -- pragma translate_on
4582 PORT MAP (
4583         dataa => \vga_driver_unit|column_counter_sig_6\,
4584         datab => \vga_driver_unit|column_counter_sig_7\,
4585         datac => \vga_control_unit|un5_v_enablelto5\,
4586         datad => \vga_control_unit|b_next_0_sqmuxa_7_3\,
4587         devclrn => ww_devclrn,
4588         devpor => ww_devpor,
4589         combout => \vga_control_unit|b_next_0_sqmuxa_7_5\);
4590
4591 \vga_control_unit|r_Z\ : stratix_lcell
4592 -- Equation(s):
4593 -- \vga_control_unit|r\ = DFFEAS(\vga_driver_unit|v_enable_sig\ & \vga_control_unit|toggle_sig\ & \vga_control_unit|b_next_0_sqmuxa_7_4\ & \vga_control_unit|b_next_0_sqmuxa_7_5\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , ,
4594 -- , , , )
4595
4596 -- pragma translate_off
4597 GENERIC MAP (
4598         lut_mask => "8000",
4599         operation_mode => "normal",
4600         output_mode => "reg_only",
4601         register_cascade_mode => "off",
4602         sum_lutc_input => "datac",
4603         synch_mode => "off")
4604 -- pragma translate_on
4605 PORT MAP (
4606         clk => \clk_pin~combout\,
4607         dataa => \vga_driver_unit|v_enable_sig\,
4608         datab => \vga_control_unit|toggle_sig\,
4609         datac => \vga_control_unit|b_next_0_sqmuxa_7_4\,
4610         datad => \vga_control_unit|b_next_0_sqmuxa_7_5\,
4611         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4612         devclrn => ww_devclrn,
4613         devpor => ww_devpor,
4614         regout => \vga_control_unit|r\);
4615
4616 \~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell
4617 -- Equation(s):
4618 -- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND
4619
4620 -- pragma translate_off
4621 GENERIC MAP (
4622         lut_mask => "0000",
4623         operation_mode => "normal",
4624         output_mode => "comb_only",
4625         register_cascade_mode => "off",
4626         sum_lutc_input => "datac",
4627         synch_mode => "off")
4628 -- pragma translate_on
4629 PORT MAP (
4630         devclrn => ww_devclrn,
4631         devpor => ww_devpor,
4632         combout => \~STRATIX_FITTER_CREATED_GND~I_combout\);
4633
4634 \vga_control_unit|b_Z\ : stratix_lcell
4635 -- Equation(s):
4636 -- \vga_control_unit|b\ = DFFEAS(\vga_driver_unit|v_enable_sig\ & !\vga_control_unit|toggle_sig\ & \vga_control_unit|b_next_0_sqmuxa_7_4\ & \vga_control_unit|b_next_0_sqmuxa_7_5\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , ,
4637 -- , , , )
4638
4639 -- pragma translate_off
4640 GENERIC MAP (
4641         lut_mask => "2000",
4642         operation_mode => "normal",
4643         output_mode => "reg_only",
4644         register_cascade_mode => "off",
4645         sum_lutc_input => "datac",
4646         synch_mode => "off")
4647 -- pragma translate_on
4648 PORT MAP (
4649         clk => \clk_pin~combout\,
4650         dataa => \vga_driver_unit|v_enable_sig\,
4651         datab => \vga_control_unit|toggle_sig\,
4652         datac => \vga_control_unit|b_next_0_sqmuxa_7_4\,
4653         datad => \vga_control_unit|b_next_0_sqmuxa_7_5\,
4654         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4655         devclrn => ww_devclrn,
4656         devpor => ww_devpor,
4657         regout => \vga_control_unit|b\);
4658
4659 \vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell
4660 -- Equation(s):
4661 -- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\
4662
4663 -- pragma translate_off
4664 GENERIC MAP (
4665         lut_mask => "fcfc",
4666         operation_mode => "normal",
4667         output_mode => "comb_only",
4668         register_cascade_mode => "off",
4669         sum_lutc_input => "datac",
4670         synch_mode => "off")
4671 -- pragma translate_on
4672 PORT MAP (
4673         datab => \vga_driver_unit|hsync_state_3\,
4674         datac => \vga_driver_unit|hsync_state_1\,
4675         devclrn => ww_devclrn,
4676         devpor => ww_devpor,
4677         combout => \vga_driver_unit|un1_hsync_state_3_0\);
4678
4679 \vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell
4680 -- Equation(s):
4681 -- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ &
4682 -- \vga_driver_unit|hsync_state_4\)
4683
4684 -- pragma translate_off
4685 GENERIC MAP (
4686         lut_mask => "fe04",
4687         operation_mode => "normal",
4688         output_mode => "comb_only",
4689         register_cascade_mode => "off",
4690         sum_lutc_input => "datac",
4691         synch_mode => "off")
4692 -- pragma translate_on
4693 PORT MAP (
4694         dataa => \vga_driver_unit|hsync_state_2\,
4695         datab => \vga_driver_unit|hsync_state_4\,
4696         datac => \vga_driver_unit|un1_hsync_state_3_0\,
4697         datad => \vga_driver_unit|h_sync\,
4698         devclrn => ww_devclrn,
4699         devpor => ww_devpor,
4700         combout => \vga_driver_unit|h_sync_1_0_0_0_g1\);
4701
4702 \vga_driver_unit|h_sync_Z\ : stratix_lcell
4703 -- Equation(s):
4704 -- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !dly_counter(0) # !\reset_pin~combout\ # !dly_counter(1), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4705
4706 -- pragma translate_off
4707 GENERIC MAP (
4708         lut_mask => "ff7f",
4709         operation_mode => "normal",
4710         output_mode => "reg_only",
4711         register_cascade_mode => "off",
4712         sum_lutc_input => "datac",
4713         synch_mode => "off")
4714 -- pragma translate_on
4715 PORT MAP (
4716         clk => \clk_pin~combout\,
4717         dataa => dly_counter(1),
4718         datab => \reset_pin~combout\,
4719         datac => dly_counter(0),
4720         datad => \vga_driver_unit|h_sync_1_0_0_0_g1\,
4721         aclr => GND,
4722         devclrn => ww_devclrn,
4723         devpor => ww_devpor,
4724         regout => \vga_driver_unit|h_sync\);
4725
4726 \vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell
4727 -- Equation(s):
4728 -- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_3\ # \vga_driver_unit|vsync_state_1\
4729
4730 -- pragma translate_off
4731 GENERIC MAP (
4732         lut_mask => "ffaa",
4733         operation_mode => "normal",
4734         output_mode => "comb_only",
4735         register_cascade_mode => "off",
4736         sum_lutc_input => "datac",
4737         synch_mode => "off")
4738 -- pragma translate_on
4739 PORT MAP (
4740         dataa => \vga_driver_unit|vsync_state_3\,
4741         datad => \vga_driver_unit|vsync_state_1\,
4742         devclrn => ww_devclrn,
4743         devpor => ww_devpor,
4744         combout => \vga_driver_unit|un1_vsync_state_2_0\);
4745
4746 \vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell
4747 -- Equation(s):
4748 -- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|un1_vsync_state_2_0\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|un1_vsync_state_2_0\ &
4749 -- \vga_driver_unit|vsync_state_4\)
4750
4751 -- pragma translate_off
4752 GENERIC MAP (
4753         lut_mask => "fe02",
4754         operation_mode => "normal",
4755         output_mode => "comb_only",
4756         register_cascade_mode => "off",
4757         sum_lutc_input => "datac",
4758         synch_mode => "off")
4759 -- pragma translate_on
4760 PORT MAP (
4761         dataa => \vga_driver_unit|vsync_state_4\,
4762         datab => \vga_driver_unit|vsync_state_2\,
4763         datac => \vga_driver_unit|un1_vsync_state_2_0\,
4764         datad => \vga_driver_unit|v_sync\,
4765         devclrn => ww_devclrn,
4766         devpor => ww_devpor,
4767         combout => \vga_driver_unit|v_sync_1_0_0_0_g1\);
4768
4769 \vga_driver_unit|v_sync_Z\ : stratix_lcell
4770 -- Equation(s):
4771 -- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !dly_counter(1) # !\reset_pin~combout\ # !dly_counter(0), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4772
4773 -- pragma translate_off
4774 GENERIC MAP (
4775         lut_mask => "dfff",
4776         operation_mode => "normal",
4777         output_mode => "reg_only",
4778         register_cascade_mode => "off",
4779         sum_lutc_input => "datac",
4780         synch_mode => "off")
4781 -- pragma translate_on
4782 PORT MAP (
4783         clk => \clk_pin~combout\,
4784         dataa => dly_counter(0),
4785         datab => \vga_driver_unit|v_sync_1_0_0_0_g1\,
4786         datac => \reset_pin~combout\,
4787         datad => dly_counter(1),
4788         aclr => GND,
4789         devclrn => ww_devclrn,
4790         devpor => ww_devpor,
4791         regout => \vga_driver_unit|v_sync\);
4792
4793 r0_pin_out : stratix_io
4794 -- pragma translate_off
4795 GENERIC MAP (
4796         ddio_mode => "none",
4797         input_async_reset => "none",
4798         input_power_up => "low",
4799         input_register_mode => "none",
4800         input_sync_reset => "none",
4801         oe_async_reset => "none",
4802         oe_power_up => "low",
4803         oe_register_mode => "none",
4804         oe_sync_reset => "none",
4805         operation_mode => "output",
4806         output_async_reset => "none",
4807         output_power_up => "low",
4808         output_register_mode => "none",
4809         output_sync_reset => "none")
4810 -- pragma translate_on
4811 PORT MAP (
4812         datain => \vga_control_unit|r\,
4813         devclrn => ww_devclrn,
4814         devpor => ww_devpor,
4815         devoe => ww_devoe,
4816         oe => VCC,
4817         padio => ww_r0_pin);
4818
4819 r1_pin_out : stratix_io
4820 -- pragma translate_off
4821 GENERIC MAP (
4822         ddio_mode => "none",
4823         input_async_reset => "none",
4824         input_power_up => "low",
4825         input_register_mode => "none",
4826         input_sync_reset => "none",
4827         oe_async_reset => "none",
4828         oe_power_up => "low",
4829         oe_register_mode => "none",
4830         oe_sync_reset => "none",
4831         operation_mode => "output",
4832         output_async_reset => "none",
4833         output_power_up => "low",
4834         output_register_mode => "none",
4835         output_sync_reset => "none")
4836 -- pragma translate_on
4837 PORT MAP (
4838         datain => \vga_control_unit|r\,
4839         devclrn => ww_devclrn,
4840         devpor => ww_devpor,
4841         devoe => ww_devoe,
4842         oe => VCC,
4843         padio => ww_r1_pin);
4844
4845 r2_pin_out : stratix_io
4846 -- pragma translate_off
4847 GENERIC MAP (
4848         ddio_mode => "none",
4849         input_async_reset => "none",
4850         input_power_up => "low",
4851         input_register_mode => "none",
4852         input_sync_reset => "none",
4853         oe_async_reset => "none",
4854         oe_power_up => "low",
4855         oe_register_mode => "none",
4856         oe_sync_reset => "none",
4857         operation_mode => "output",
4858         output_async_reset => "none",
4859         output_power_up => "low",
4860         output_register_mode => "none",
4861         output_sync_reset => "none")
4862 -- pragma translate_on
4863 PORT MAP (
4864         datain => \vga_control_unit|r\,
4865         devclrn => ww_devclrn,
4866         devpor => ww_devpor,
4867         devoe => ww_devoe,
4868         oe => VCC,
4869         padio => ww_r2_pin);
4870
4871 g0_pin_out : stratix_io
4872 -- pragma translate_off
4873 GENERIC MAP (
4874         ddio_mode => "none",
4875         input_async_reset => "none",
4876         input_power_up => "low",
4877         input_register_mode => "none",
4878         input_sync_reset => "none",
4879         oe_async_reset => "none",
4880         oe_power_up => "low",
4881         oe_register_mode => "none",
4882         oe_sync_reset => "none",
4883         operation_mode => "output",
4884         output_async_reset => "none",
4885         output_power_up => "low",
4886         output_register_mode => "none",
4887         output_sync_reset => "none")
4888 -- pragma translate_on
4889 PORT MAP (
4890         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4891         devclrn => ww_devclrn,
4892         devpor => ww_devpor,
4893         devoe => ww_devoe,
4894         oe => VCC,
4895         padio => ww_g0_pin);
4896
4897 g1_pin_out : stratix_io
4898 -- pragma translate_off
4899 GENERIC MAP (
4900         ddio_mode => "none",
4901         input_async_reset => "none",
4902         input_power_up => "low",
4903         input_register_mode => "none",
4904         input_sync_reset => "none",
4905         oe_async_reset => "none",
4906         oe_power_up => "low",
4907         oe_register_mode => "none",
4908         oe_sync_reset => "none",
4909         operation_mode => "output",
4910         output_async_reset => "none",
4911         output_power_up => "low",
4912         output_register_mode => "none",
4913         output_sync_reset => "none")
4914 -- pragma translate_on
4915 PORT MAP (
4916         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4917         devclrn => ww_devclrn,
4918         devpor => ww_devpor,
4919         devoe => ww_devoe,
4920         oe => VCC,
4921         padio => ww_g1_pin);
4922
4923 g2_pin_out : stratix_io
4924 -- pragma translate_off
4925 GENERIC MAP (
4926         ddio_mode => "none",
4927         input_async_reset => "none",
4928         input_power_up => "low",
4929         input_register_mode => "none",
4930         input_sync_reset => "none",
4931         oe_async_reset => "none",
4932         oe_power_up => "low",
4933         oe_register_mode => "none",
4934         oe_sync_reset => "none",
4935         operation_mode => "output",
4936         output_async_reset => "none",
4937         output_power_up => "low",
4938         output_register_mode => "none",
4939         output_sync_reset => "none")
4940 -- pragma translate_on
4941 PORT MAP (
4942         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4943         devclrn => ww_devclrn,
4944         devpor => ww_devpor,
4945         devoe => ww_devoe,
4946         oe => VCC,
4947         padio => ww_g2_pin);
4948
4949 b0_pin_out : stratix_io
4950 -- pragma translate_off
4951 GENERIC MAP (
4952         ddio_mode => "none",
4953         input_async_reset => "none",
4954         input_power_up => "low",
4955         input_register_mode => "none",
4956         input_sync_reset => "none",
4957         oe_async_reset => "none",
4958         oe_power_up => "low",
4959         oe_register_mode => "none",
4960         oe_sync_reset => "none",
4961         operation_mode => "output",
4962         output_async_reset => "none",
4963         output_power_up => "low",
4964         output_register_mode => "none",
4965         output_sync_reset => "none")
4966 -- pragma translate_on
4967 PORT MAP (
4968         datain => \vga_control_unit|b\,
4969         devclrn => ww_devclrn,
4970         devpor => ww_devpor,
4971         devoe => ww_devoe,
4972         oe => VCC,
4973         padio => ww_b0_pin);
4974
4975 b1_pin_out : stratix_io
4976 -- pragma translate_off
4977 GENERIC MAP (
4978         ddio_mode => "none",
4979         input_async_reset => "none",
4980         input_power_up => "low",
4981         input_register_mode => "none",
4982         input_sync_reset => "none",
4983         oe_async_reset => "none",
4984         oe_power_up => "low",
4985         oe_register_mode => "none",
4986         oe_sync_reset => "none",
4987         operation_mode => "output",
4988         output_async_reset => "none",
4989         output_power_up => "low",
4990         output_register_mode => "none",
4991         output_sync_reset => "none")
4992 -- pragma translate_on
4993 PORT MAP (
4994         datain => \vga_control_unit|b\,
4995         devclrn => ww_devclrn,
4996         devpor => ww_devpor,
4997         devoe => ww_devoe,
4998         oe => VCC,
4999         padio => ww_b1_pin);
5000
5001 hsync_pin_out : stratix_io
5002 -- pragma translate_off
5003 GENERIC MAP (
5004         ddio_mode => "none",
5005         input_async_reset => "none",
5006         input_power_up => "low",
5007         input_register_mode => "none",
5008         input_sync_reset => "none",
5009         oe_async_reset => "none",
5010         oe_power_up => "low",
5011         oe_register_mode => "none",
5012         oe_sync_reset => "none",
5013         operation_mode => "output",
5014         output_async_reset => "none",
5015         output_power_up => "low",
5016         output_register_mode => "none",
5017         output_sync_reset => "none")
5018 -- pragma translate_on
5019 PORT MAP (
5020         datain => \vga_driver_unit|h_sync\,
5021         devclrn => ww_devclrn,
5022         devpor => ww_devpor,
5023         devoe => ww_devoe,
5024         oe => VCC,
5025         padio => ww_hsync_pin);
5026
5027 vsync_pin_out : stratix_io
5028 -- pragma translate_off
5029 GENERIC MAP (
5030         ddio_mode => "none",
5031         input_async_reset => "none",
5032         input_power_up => "low",
5033         input_register_mode => "none",
5034         input_sync_reset => "none",
5035         oe_async_reset => "none",
5036         oe_power_up => "low",
5037         oe_register_mode => "none",
5038         oe_sync_reset => "none",
5039         operation_mode => "output",
5040         output_async_reset => "none",
5041         output_power_up => "low",
5042         output_register_mode => "none",
5043         output_sync_reset => "none")
5044 -- pragma translate_on
5045 PORT MAP (
5046         datain => \vga_driver_unit|v_sync\,
5047         devclrn => ww_devclrn,
5048         devpor => ww_devpor,
5049         devoe => ww_devoe,
5050         oe => VCC,
5051         padio => ww_vsync_pin);
5052
5053 \seven_seg_pin_tri_0_\ : stratix_io
5054 -- pragma translate_off
5055 GENERIC MAP (
5056         ddio_mode => "none",
5057         input_async_reset => "none",
5058         input_power_up => "low",
5059         input_register_mode => "none",
5060         input_sync_reset => "none",
5061         oe_async_reset => "none",
5062         oe_power_up => "low",
5063         oe_register_mode => "none",
5064         oe_sync_reset => "none",
5065         operation_mode => "output",
5066         output_async_reset => "none",
5067         output_power_up => "low",
5068         output_register_mode => "none",
5069         output_sync_reset => "none")
5070 -- pragma translate_on
5071 PORT MAP (
5072         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5073         devclrn => ww_devclrn,
5074         devpor => ww_devpor,
5075         devoe => ww_devoe,
5076         oe => VCC,
5077         padio => ww_seven_seg_pin(0));
5078
5079 \seven_seg_pin_out_1_\ : stratix_io
5080 -- pragma translate_off
5081 GENERIC MAP (
5082         ddio_mode => "none",
5083         input_async_reset => "none",
5084         input_power_up => "low",
5085         input_register_mode => "none",
5086         input_sync_reset => "none",
5087         oe_async_reset => "none",
5088         oe_power_up => "low",
5089         oe_register_mode => "none",
5090         oe_sync_reset => "none",
5091         operation_mode => "output",
5092         output_async_reset => "none",
5093         output_power_up => "low",
5094         output_register_mode => "none",
5095         output_sync_reset => "none")
5096 -- pragma translate_on
5097 PORT MAP (
5098         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5099         devclrn => ww_devclrn,
5100         devpor => ww_devpor,
5101         devoe => ww_devoe,
5102         oe => VCC,
5103         padio => ww_seven_seg_pin(1));
5104
5105 \seven_seg_pin_out_2_\ : stratix_io
5106 -- pragma translate_off
5107 GENERIC MAP (
5108         ddio_mode => "none",
5109         input_async_reset => "none",
5110         input_power_up => "low",
5111         input_register_mode => "none",
5112         input_sync_reset => "none",
5113         oe_async_reset => "none",
5114         oe_power_up => "low",
5115         oe_register_mode => "none",
5116         oe_sync_reset => "none",
5117         operation_mode => "output",
5118         output_async_reset => "none",
5119         output_power_up => "low",
5120         output_register_mode => "none",
5121         output_sync_reset => "none")
5122 -- pragma translate_on
5123 PORT MAP (
5124         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5125         devclrn => ww_devclrn,
5126         devpor => ww_devpor,
5127         devoe => ww_devoe,
5128         oe => VCC,
5129         padio => ww_seven_seg_pin(2));
5130
5131 \seven_seg_pin_tri_3_\ : stratix_io
5132 -- pragma translate_off
5133 GENERIC MAP (
5134         ddio_mode => "none",
5135         input_async_reset => "none",
5136         input_power_up => "low",
5137         input_register_mode => "none",
5138         input_sync_reset => "none",
5139         oe_async_reset => "none",
5140         oe_power_up => "low",
5141         oe_register_mode => "none",
5142         oe_sync_reset => "none",
5143         operation_mode => "output",
5144         output_async_reset => "none",
5145         output_power_up => "low",
5146         output_register_mode => "none",
5147         output_sync_reset => "none")
5148 -- pragma translate_on
5149 PORT MAP (
5150         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5151         devclrn => ww_devclrn,
5152         devpor => ww_devpor,
5153         devoe => ww_devoe,
5154         oe => VCC,
5155         padio => ww_seven_seg_pin(3));
5156
5157 \seven_seg_pin_tri_4_\ : stratix_io
5158 -- pragma translate_off
5159 GENERIC MAP (
5160         ddio_mode => "none",
5161         input_async_reset => "none",
5162         input_power_up => "low",
5163         input_register_mode => "none",
5164         input_sync_reset => "none",
5165         oe_async_reset => "none",
5166         oe_power_up => "low",
5167         oe_register_mode => "none",
5168         oe_sync_reset => "none",
5169         operation_mode => "output",
5170         output_async_reset => "none",
5171         output_power_up => "low",
5172         output_register_mode => "none",
5173         output_sync_reset => "none")
5174 -- pragma translate_on
5175 PORT MAP (
5176         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5177         devclrn => ww_devclrn,
5178         devpor => ww_devpor,
5179         devoe => ww_devoe,
5180         oe => VCC,
5181         padio => ww_seven_seg_pin(4));
5182
5183 \seven_seg_pin_tri_5_\ : stratix_io
5184 -- pragma translate_off
5185 GENERIC MAP (
5186         ddio_mode => "none",
5187         input_async_reset => "none",
5188         input_power_up => "low",
5189         input_register_mode => "none",
5190         input_sync_reset => "none",
5191         oe_async_reset => "none",
5192         oe_power_up => "low",
5193         oe_register_mode => "none",
5194         oe_sync_reset => "none",
5195         operation_mode => "output",
5196         output_async_reset => "none",
5197         output_power_up => "low",
5198         output_register_mode => "none",
5199         output_sync_reset => "none")
5200 -- pragma translate_on
5201 PORT MAP (
5202         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5203         devclrn => ww_devclrn,
5204         devpor => ww_devpor,
5205         devoe => ww_devoe,
5206         oe => VCC,
5207         padio => ww_seven_seg_pin(5));
5208
5209 \seven_seg_pin_tri_6_\ : stratix_io
5210 -- pragma translate_off
5211 GENERIC MAP (
5212         ddio_mode => "none",
5213         input_async_reset => "none",
5214         input_power_up => "low",
5215         input_register_mode => "none",
5216         input_sync_reset => "none",
5217         oe_async_reset => "none",
5218         oe_power_up => "low",
5219         oe_register_mode => "none",
5220         oe_sync_reset => "none",
5221         operation_mode => "output",
5222         output_async_reset => "none",
5223         output_power_up => "low",
5224         output_register_mode => "none",
5225         output_sync_reset => "none")
5226 -- pragma translate_on
5227 PORT MAP (
5228         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5229         devclrn => ww_devclrn,
5230         devpor => ww_devpor,
5231         devoe => ww_devoe,
5232         oe => VCC,
5233         padio => ww_seven_seg_pin(6));
5234
5235 \seven_seg_pin_out_7_\ : stratix_io
5236 -- pragma translate_off
5237 GENERIC MAP (
5238         ddio_mode => "none",
5239         input_async_reset => "none",
5240         input_power_up => "low",
5241         input_register_mode => "none",
5242         input_sync_reset => "none",
5243         oe_async_reset => "none",
5244         oe_power_up => "low",
5245         oe_register_mode => "none",
5246         oe_sync_reset => "none",
5247         operation_mode => "output",
5248         output_async_reset => "none",
5249         output_power_up => "low",
5250         output_register_mode => "none",
5251         output_sync_reset => "none")
5252 -- pragma translate_on
5253 PORT MAP (
5254         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5255         devclrn => ww_devclrn,
5256         devpor => ww_devpor,
5257         devoe => ww_devoe,
5258         oe => VCC,
5259         padio => ww_seven_seg_pin(7));
5260
5261 \seven_seg_pin_out_8_\ : stratix_io
5262 -- pragma translate_off
5263 GENERIC MAP (
5264         ddio_mode => "none",
5265         input_async_reset => "none",
5266         input_power_up => "low",
5267         input_register_mode => "none",
5268         input_sync_reset => "none",
5269         oe_async_reset => "none",
5270         oe_power_up => "low",
5271         oe_register_mode => "none",
5272         oe_sync_reset => "none",
5273         operation_mode => "output",
5274         output_async_reset => "none",
5275         output_power_up => "low",
5276         output_register_mode => "none",
5277         output_sync_reset => "none")
5278 -- pragma translate_on
5279 PORT MAP (
5280         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5281         devclrn => ww_devclrn,
5282         devpor => ww_devpor,
5283         devoe => ww_devoe,
5284         oe => VCC,
5285         padio => ww_seven_seg_pin(8));
5286
5287 \seven_seg_pin_out_9_\ : stratix_io
5288 -- pragma translate_off
5289 GENERIC MAP (
5290         ddio_mode => "none",
5291         input_async_reset => "none",
5292         input_power_up => "low",
5293         input_register_mode => "none",
5294         input_sync_reset => "none",
5295         oe_async_reset => "none",
5296         oe_power_up => "low",
5297         oe_register_mode => "none",
5298         oe_sync_reset => "none",
5299         operation_mode => "output",
5300         output_async_reset => "none",
5301         output_power_up => "low",
5302         output_register_mode => "none",
5303         output_sync_reset => "none")
5304 -- pragma translate_on
5305 PORT MAP (
5306         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5307         devclrn => ww_devclrn,
5308         devpor => ww_devpor,
5309         devoe => ww_devoe,
5310         oe => VCC,
5311         padio => ww_seven_seg_pin(9));
5312
5313 \seven_seg_pin_out_10_\ : stratix_io
5314 -- pragma translate_off
5315 GENERIC MAP (
5316         ddio_mode => "none",
5317         input_async_reset => "none",
5318         input_power_up => "low",
5319         input_register_mode => "none",
5320         input_sync_reset => "none",
5321         oe_async_reset => "none",
5322         oe_power_up => "low",
5323         oe_register_mode => "none",
5324         oe_sync_reset => "none",
5325         operation_mode => "output",
5326         output_async_reset => "none",
5327         output_power_up => "low",
5328         output_register_mode => "none",
5329         output_sync_reset => "none")
5330 -- pragma translate_on
5331 PORT MAP (
5332         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5333         devclrn => ww_devclrn,
5334         devpor => ww_devpor,
5335         devoe => ww_devoe,
5336         oe => VCC,
5337         padio => ww_seven_seg_pin(10));
5338
5339 \seven_seg_pin_out_11_\ : stratix_io
5340 -- pragma translate_off
5341 GENERIC MAP (
5342         ddio_mode => "none",
5343         input_async_reset => "none",
5344         input_power_up => "low",
5345         input_register_mode => "none",
5346         input_sync_reset => "none",
5347         oe_async_reset => "none",
5348         oe_power_up => "low",
5349         oe_register_mode => "none",
5350         oe_sync_reset => "none",
5351         operation_mode => "output",
5352         output_async_reset => "none",
5353         output_power_up => "low",
5354         output_register_mode => "none",
5355         output_sync_reset => "none")
5356 -- pragma translate_on
5357 PORT MAP (
5358         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5359         devclrn => ww_devclrn,
5360         devpor => ww_devpor,
5361         devoe => ww_devoe,
5362         oe => VCC,
5363         padio => ww_seven_seg_pin(11));
5364
5365 \seven_seg_pin_out_12_\ : stratix_io
5366 -- pragma translate_off
5367 GENERIC MAP (
5368         ddio_mode => "none",
5369         input_async_reset => "none",
5370         input_power_up => "low",
5371         input_register_mode => "none",
5372         input_sync_reset => "none",
5373         oe_async_reset => "none",
5374         oe_power_up => "low",
5375         oe_register_mode => "none",
5376         oe_sync_reset => "none",
5377         operation_mode => "output",
5378         output_async_reset => "none",
5379         output_power_up => "low",
5380         output_register_mode => "none",
5381         output_sync_reset => "none")
5382 -- pragma translate_on
5383 PORT MAP (
5384         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5385         devclrn => ww_devclrn,
5386         devpor => ww_devpor,
5387         devoe => ww_devoe,
5388         oe => VCC,
5389         padio => ww_seven_seg_pin(12));
5390
5391 \seven_seg_pin_tri_13_\ : stratix_io
5392 -- pragma translate_off
5393 GENERIC MAP (
5394         ddio_mode => "none",
5395         input_async_reset => "none",
5396         input_power_up => "low",
5397         input_register_mode => "none",
5398         input_sync_reset => "none",
5399         oe_async_reset => "none",
5400         oe_power_up => "low",
5401         oe_register_mode => "none",
5402         oe_sync_reset => "none",
5403         operation_mode => "output",
5404         output_async_reset => "none",
5405         output_power_up => "low",
5406         output_register_mode => "none",
5407         output_sync_reset => "none")
5408 -- pragma translate_on
5409 PORT MAP (
5410         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5411         devclrn => ww_devclrn,
5412         devpor => ww_devpor,
5413         devoe => ww_devoe,
5414         oe => VCC,
5415         padio => ww_seven_seg_pin(13));
5416
5417 d_hsync_out : stratix_io
5418 -- pragma translate_off
5419 GENERIC MAP (
5420         ddio_mode => "none",
5421         input_async_reset => "none",
5422         input_power_up => "low",
5423         input_register_mode => "none",
5424         input_sync_reset => "none",
5425         oe_async_reset => "none",
5426         oe_power_up => "low",
5427         oe_register_mode => "none",
5428         oe_sync_reset => "none",
5429         operation_mode => "output",
5430         output_async_reset => "none",
5431         output_power_up => "low",
5432         output_register_mode => "none",
5433         output_sync_reset => "none")
5434 -- pragma translate_on
5435 PORT MAP (
5436         datain => \vga_driver_unit|h_sync\,
5437         devclrn => ww_devclrn,
5438         devpor => ww_devpor,
5439         devoe => ww_devoe,
5440         oe => VCC,
5441         padio => ww_d_hsync);
5442
5443 d_vsync_out : stratix_io
5444 -- pragma translate_off
5445 GENERIC MAP (
5446         ddio_mode => "none",
5447         input_async_reset => "none",
5448         input_power_up => "low",
5449         input_register_mode => "none",
5450         input_sync_reset => "none",
5451         oe_async_reset => "none",
5452         oe_power_up => "low",
5453         oe_register_mode => "none",
5454         oe_sync_reset => "none",
5455         operation_mode => "output",
5456         output_async_reset => "none",
5457         output_power_up => "low",
5458         output_register_mode => "none",
5459         output_sync_reset => "none")
5460 -- pragma translate_on
5461 PORT MAP (
5462         datain => \vga_driver_unit|v_sync\,
5463         devclrn => ww_devclrn,
5464         devpor => ww_devpor,
5465         devoe => ww_devoe,
5466         oe => VCC,
5467         padio => ww_d_vsync);
5468
5469 \d_column_counter_out_0_\ : stratix_io
5470 -- pragma translate_off
5471 GENERIC MAP (
5472         ddio_mode => "none",
5473         input_async_reset => "none",
5474         input_power_up => "low",
5475         input_register_mode => "none",
5476         input_sync_reset => "none",
5477         oe_async_reset => "none",
5478         oe_power_up => "low",
5479         oe_register_mode => "none",
5480         oe_sync_reset => "none",
5481         operation_mode => "output",
5482         output_async_reset => "none",
5483         output_power_up => "low",
5484         output_register_mode => "none",
5485         output_sync_reset => "none")
5486 -- pragma translate_on
5487 PORT MAP (
5488         datain => \vga_driver_unit|column_counter_sig_0\,
5489         devclrn => ww_devclrn,
5490         devpor => ww_devpor,
5491         devoe => ww_devoe,
5492         oe => VCC,
5493         padio => ww_d_column_counter(0));
5494
5495 \d_column_counter_out_1_\ : stratix_io
5496 -- pragma translate_off
5497 GENERIC MAP (
5498         ddio_mode => "none",
5499         input_async_reset => "none",
5500         input_power_up => "low",
5501         input_register_mode => "none",
5502         input_sync_reset => "none",
5503         oe_async_reset => "none",
5504         oe_power_up => "low",
5505         oe_register_mode => "none",
5506         oe_sync_reset => "none",
5507         operation_mode => "output",
5508         output_async_reset => "none",
5509         output_power_up => "low",
5510         output_register_mode => "none",
5511         output_sync_reset => "none")
5512 -- pragma translate_on
5513 PORT MAP (
5514         datain => \vga_driver_unit|column_counter_sig_1\,
5515         devclrn => ww_devclrn,
5516         devpor => ww_devpor,
5517         devoe => ww_devoe,
5518         oe => VCC,
5519         padio => ww_d_column_counter(1));
5520
5521 \d_column_counter_out_2_\ : stratix_io
5522 -- pragma translate_off
5523 GENERIC MAP (
5524         ddio_mode => "none",
5525         input_async_reset => "none",
5526         input_power_up => "low",
5527         input_register_mode => "none",
5528         input_sync_reset => "none",
5529         oe_async_reset => "none",
5530         oe_power_up => "low",
5531         oe_register_mode => "none",
5532         oe_sync_reset => "none",
5533         operation_mode => "output",
5534         output_async_reset => "none",
5535         output_power_up => "low",
5536         output_register_mode => "none",
5537         output_sync_reset => "none")
5538 -- pragma translate_on
5539 PORT MAP (
5540         datain => \vga_driver_unit|column_counter_sig_2\,
5541         devclrn => ww_devclrn,
5542         devpor => ww_devpor,
5543         devoe => ww_devoe,
5544         oe => VCC,
5545         padio => ww_d_column_counter(2));
5546
5547 \d_column_counter_out_3_\ : stratix_io
5548 -- pragma translate_off
5549 GENERIC MAP (
5550         ddio_mode => "none",
5551         input_async_reset => "none",
5552         input_power_up => "low",
5553         input_register_mode => "none",
5554         input_sync_reset => "none",
5555         oe_async_reset => "none",
5556         oe_power_up => "low",
5557         oe_register_mode => "none",
5558         oe_sync_reset => "none",
5559         operation_mode => "output",
5560         output_async_reset => "none",
5561         output_power_up => "low",
5562         output_register_mode => "none",
5563         output_sync_reset => "none")
5564 -- pragma translate_on
5565 PORT MAP (
5566         datain => \vga_driver_unit|column_counter_sig_3\,
5567         devclrn => ww_devclrn,
5568         devpor => ww_devpor,
5569         devoe => ww_devoe,
5570         oe => VCC,
5571         padio => ww_d_column_counter(3));
5572
5573 \d_column_counter_out_4_\ : stratix_io
5574 -- pragma translate_off
5575 GENERIC MAP (
5576         ddio_mode => "none",
5577         input_async_reset => "none",
5578         input_power_up => "low",
5579         input_register_mode => "none",
5580         input_sync_reset => "none",
5581         oe_async_reset => "none",
5582         oe_power_up => "low",
5583         oe_register_mode => "none",
5584         oe_sync_reset => "none",
5585         operation_mode => "output",
5586         output_async_reset => "none",
5587         output_power_up => "low",
5588         output_register_mode => "none",
5589         output_sync_reset => "none")
5590 -- pragma translate_on
5591 PORT MAP (
5592         datain => \vga_driver_unit|column_counter_sig_4\,
5593         devclrn => ww_devclrn,
5594         devpor => ww_devpor,
5595         devoe => ww_devoe,
5596         oe => VCC,
5597         padio => ww_d_column_counter(4));
5598
5599 \d_column_counter_out_5_\ : stratix_io
5600 -- pragma translate_off
5601 GENERIC MAP (
5602         ddio_mode => "none",
5603         input_async_reset => "none",
5604         input_power_up => "low",
5605         input_register_mode => "none",
5606         input_sync_reset => "none",
5607         oe_async_reset => "none",
5608         oe_power_up => "low",
5609         oe_register_mode => "none",
5610         oe_sync_reset => "none",
5611         operation_mode => "output",
5612         output_async_reset => "none",
5613         output_power_up => "low",
5614         output_register_mode => "none",
5615         output_sync_reset => "none")
5616 -- pragma translate_on
5617 PORT MAP (
5618         datain => \vga_driver_unit|column_counter_sig_5\,
5619         devclrn => ww_devclrn,
5620         devpor => ww_devpor,
5621         devoe => ww_devoe,
5622         oe => VCC,
5623         padio => ww_d_column_counter(5));
5624
5625 \d_column_counter_out_6_\ : stratix_io
5626 -- pragma translate_off
5627 GENERIC MAP (
5628         ddio_mode => "none",
5629         input_async_reset => "none",
5630         input_power_up => "low",
5631         input_register_mode => "none",
5632         input_sync_reset => "none",
5633         oe_async_reset => "none",
5634         oe_power_up => "low",
5635         oe_register_mode => "none",
5636         oe_sync_reset => "none",
5637         operation_mode => "output",
5638         output_async_reset => "none",
5639         output_power_up => "low",
5640         output_register_mode => "none",
5641         output_sync_reset => "none")
5642 -- pragma translate_on
5643 PORT MAP (
5644         datain => \vga_driver_unit|column_counter_sig_6\,
5645         devclrn => ww_devclrn,
5646         devpor => ww_devpor,
5647         devoe => ww_devoe,
5648         oe => VCC,
5649         padio => ww_d_column_counter(6));
5650
5651 \d_column_counter_out_7_\ : stratix_io
5652 -- pragma translate_off
5653 GENERIC MAP (
5654         ddio_mode => "none",
5655         input_async_reset => "none",
5656         input_power_up => "low",
5657         input_register_mode => "none",
5658         input_sync_reset => "none",
5659         oe_async_reset => "none",
5660         oe_power_up => "low",
5661         oe_register_mode => "none",
5662         oe_sync_reset => "none",
5663         operation_mode => "output",
5664         output_async_reset => "none",
5665         output_power_up => "low",
5666         output_register_mode => "none",
5667         output_sync_reset => "none")
5668 -- pragma translate_on
5669 PORT MAP (
5670         datain => \vga_driver_unit|column_counter_sig_7\,
5671         devclrn => ww_devclrn,
5672         devpor => ww_devpor,
5673         devoe => ww_devoe,
5674         oe => VCC,
5675         padio => ww_d_column_counter(7));
5676
5677 \d_column_counter_out_8_\ : stratix_io
5678 -- pragma translate_off
5679 GENERIC MAP (
5680         ddio_mode => "none",
5681         input_async_reset => "none",
5682         input_power_up => "low",
5683         input_register_mode => "none",
5684         input_sync_reset => "none",
5685         oe_async_reset => "none",
5686         oe_power_up => "low",
5687         oe_register_mode => "none",
5688         oe_sync_reset => "none",
5689         operation_mode => "output",
5690         output_async_reset => "none",
5691         output_power_up => "low",
5692         output_register_mode => "none",
5693         output_sync_reset => "none")
5694 -- pragma translate_on
5695 PORT MAP (
5696         datain => \vga_driver_unit|column_counter_sig_8\,
5697         devclrn => ww_devclrn,
5698         devpor => ww_devpor,
5699         devoe => ww_devoe,
5700         oe => VCC,
5701         padio => ww_d_column_counter(8));
5702
5703 \d_column_counter_out_9_\ : stratix_io
5704 -- pragma translate_off
5705 GENERIC MAP (
5706         ddio_mode => "none",
5707         input_async_reset => "none",
5708         input_power_up => "low",
5709         input_register_mode => "none",
5710         input_sync_reset => "none",
5711         oe_async_reset => "none",
5712         oe_power_up => "low",
5713         oe_register_mode => "none",
5714         oe_sync_reset => "none",
5715         operation_mode => "output",
5716         output_async_reset => "none",
5717         output_power_up => "low",
5718         output_register_mode => "none",
5719         output_sync_reset => "none")
5720 -- pragma translate_on
5721 PORT MAP (
5722         datain => \vga_driver_unit|column_counter_sig_9\,
5723         devclrn => ww_devclrn,
5724         devpor => ww_devpor,
5725         devoe => ww_devoe,
5726         oe => VCC,
5727         padio => ww_d_column_counter(9));
5728
5729 \d_line_counter_out_0_\ : stratix_io
5730 -- pragma translate_off
5731 GENERIC MAP (
5732         ddio_mode => "none",
5733         input_async_reset => "none",
5734         input_power_up => "low",
5735         input_register_mode => "none",
5736         input_sync_reset => "none",
5737         oe_async_reset => "none",
5738         oe_power_up => "low",
5739         oe_register_mode => "none",
5740         oe_sync_reset => "none",
5741         operation_mode => "output",
5742         output_async_reset => "none",
5743         output_power_up => "low",
5744         output_register_mode => "none",
5745         output_sync_reset => "none")
5746 -- pragma translate_on
5747 PORT MAP (
5748         datain => \vga_driver_unit|line_counter_sig_0\,
5749         devclrn => ww_devclrn,
5750         devpor => ww_devpor,
5751         devoe => ww_devoe,
5752         oe => VCC,
5753         padio => ww_d_line_counter(0));
5754
5755 \d_line_counter_out_1_\ : stratix_io
5756 -- pragma translate_off
5757 GENERIC MAP (
5758         ddio_mode => "none",
5759         input_async_reset => "none",
5760         input_power_up => "low",
5761         input_register_mode => "none",
5762         input_sync_reset => "none",
5763         oe_async_reset => "none",
5764         oe_power_up => "low",
5765         oe_register_mode => "none",
5766         oe_sync_reset => "none",
5767         operation_mode => "output",
5768         output_async_reset => "none",
5769         output_power_up => "low",
5770         output_register_mode => "none",
5771         output_sync_reset => "none")
5772 -- pragma translate_on
5773 PORT MAP (
5774         datain => \vga_driver_unit|line_counter_sig_1\,
5775         devclrn => ww_devclrn,
5776         devpor => ww_devpor,
5777         devoe => ww_devoe,
5778         oe => VCC,
5779         padio => ww_d_line_counter(1));
5780
5781 \d_line_counter_out_2_\ : stratix_io
5782 -- pragma translate_off
5783 GENERIC MAP (
5784         ddio_mode => "none",
5785         input_async_reset => "none",
5786         input_power_up => "low",
5787         input_register_mode => "none",
5788         input_sync_reset => "none",
5789         oe_async_reset => "none",
5790         oe_power_up => "low",
5791         oe_register_mode => "none",
5792         oe_sync_reset => "none",
5793         operation_mode => "output",
5794         output_async_reset => "none",
5795         output_power_up => "low",
5796         output_register_mode => "none",
5797         output_sync_reset => "none")
5798 -- pragma translate_on
5799 PORT MAP (
5800         datain => \vga_driver_unit|line_counter_sig_2\,
5801         devclrn => ww_devclrn,
5802         devpor => ww_devpor,
5803         devoe => ww_devoe,
5804         oe => VCC,
5805         padio => ww_d_line_counter(2));
5806
5807 \d_line_counter_out_3_\ : stratix_io
5808 -- pragma translate_off
5809 GENERIC MAP (
5810         ddio_mode => "none",
5811         input_async_reset => "none",
5812         input_power_up => "low",
5813         input_register_mode => "none",
5814         input_sync_reset => "none",
5815         oe_async_reset => "none",
5816         oe_power_up => "low",
5817         oe_register_mode => "none",
5818         oe_sync_reset => "none",
5819         operation_mode => "output",
5820         output_async_reset => "none",
5821         output_power_up => "low",
5822         output_register_mode => "none",
5823         output_sync_reset => "none")
5824 -- pragma translate_on
5825 PORT MAP (
5826         datain => \vga_driver_unit|line_counter_sig_3\,
5827         devclrn => ww_devclrn,
5828         devpor => ww_devpor,
5829         devoe => ww_devoe,
5830         oe => VCC,
5831         padio => ww_d_line_counter(3));
5832
5833 \d_line_counter_out_4_\ : stratix_io
5834 -- pragma translate_off
5835 GENERIC MAP (
5836         ddio_mode => "none",
5837         input_async_reset => "none",
5838         input_power_up => "low",
5839         input_register_mode => "none",
5840         input_sync_reset => "none",
5841         oe_async_reset => "none",
5842         oe_power_up => "low",
5843         oe_register_mode => "none",
5844         oe_sync_reset => "none",
5845         operation_mode => "output",
5846         output_async_reset => "none",
5847         output_power_up => "low",
5848         output_register_mode => "none",
5849         output_sync_reset => "none")
5850 -- pragma translate_on
5851 PORT MAP (
5852         datain => \vga_driver_unit|line_counter_sig_4\,
5853         devclrn => ww_devclrn,
5854         devpor => ww_devpor,
5855         devoe => ww_devoe,
5856         oe => VCC,
5857         padio => ww_d_line_counter(4));
5858
5859 \d_line_counter_out_5_\ : stratix_io
5860 -- pragma translate_off
5861 GENERIC MAP (
5862         ddio_mode => "none",
5863         input_async_reset => "none",
5864         input_power_up => "low",
5865         input_register_mode => "none",
5866         input_sync_reset => "none",
5867         oe_async_reset => "none",
5868         oe_power_up => "low",
5869         oe_register_mode => "none",
5870         oe_sync_reset => "none",
5871         operation_mode => "output",
5872         output_async_reset => "none",
5873         output_power_up => "low",
5874         output_register_mode => "none",
5875         output_sync_reset => "none")
5876 -- pragma translate_on
5877 PORT MAP (
5878         datain => \vga_driver_unit|line_counter_sig_5\,
5879         devclrn => ww_devclrn,
5880         devpor => ww_devpor,
5881         devoe => ww_devoe,
5882         oe => VCC,
5883         padio => ww_d_line_counter(5));
5884
5885 \d_line_counter_out_6_\ : stratix_io
5886 -- pragma translate_off
5887 GENERIC MAP (
5888         ddio_mode => "none",
5889         input_async_reset => "none",
5890         input_power_up => "low",
5891         input_register_mode => "none",
5892         input_sync_reset => "none",
5893         oe_async_reset => "none",
5894         oe_power_up => "low",
5895         oe_register_mode => "none",
5896         oe_sync_reset => "none",
5897         operation_mode => "output",
5898         output_async_reset => "none",
5899         output_power_up => "low",
5900         output_register_mode => "none",
5901         output_sync_reset => "none")
5902 -- pragma translate_on
5903 PORT MAP (
5904         datain => \vga_driver_unit|line_counter_sig_6\,
5905         devclrn => ww_devclrn,
5906         devpor => ww_devpor,
5907         devoe => ww_devoe,
5908         oe => VCC,
5909         padio => ww_d_line_counter(6));
5910
5911 \d_line_counter_out_7_\ : stratix_io
5912 -- pragma translate_off
5913 GENERIC MAP (
5914         ddio_mode => "none",
5915         input_async_reset => "none",
5916         input_power_up => "low",
5917         input_register_mode => "none",
5918         input_sync_reset => "none",
5919         oe_async_reset => "none",
5920         oe_power_up => "low",
5921         oe_register_mode => "none",
5922         oe_sync_reset => "none",
5923         operation_mode => "output",
5924         output_async_reset => "none",
5925         output_power_up => "low",
5926         output_register_mode => "none",
5927         output_sync_reset => "none")
5928 -- pragma translate_on
5929 PORT MAP (
5930         datain => \vga_driver_unit|line_counter_sig_7\,
5931         devclrn => ww_devclrn,
5932         devpor => ww_devpor,
5933         devoe => ww_devoe,
5934         oe => VCC,
5935         padio => ww_d_line_counter(7));
5936
5937 \d_line_counter_out_8_\ : stratix_io
5938 -- pragma translate_off
5939 GENERIC MAP (
5940         ddio_mode => "none",
5941         input_async_reset => "none",
5942         input_power_up => "low",
5943         input_register_mode => "none",
5944         input_sync_reset => "none",
5945         oe_async_reset => "none",
5946         oe_power_up => "low",
5947         oe_register_mode => "none",
5948         oe_sync_reset => "none",
5949         operation_mode => "output",
5950         output_async_reset => "none",
5951         output_power_up => "low",
5952         output_register_mode => "none",
5953         output_sync_reset => "none")
5954 -- pragma translate_on
5955 PORT MAP (
5956         datain => \vga_driver_unit|line_counter_sig_8\,
5957         devclrn => ww_devclrn,
5958         devpor => ww_devpor,
5959         devoe => ww_devoe,
5960         oe => VCC,
5961         padio => ww_d_line_counter(8));
5962
5963 d_set_column_counter_out : stratix_io
5964 -- pragma translate_off
5965 GENERIC MAP (
5966         ddio_mode => "none",
5967         input_async_reset => "none",
5968         input_power_up => "low",
5969         input_register_mode => "none",
5970         input_sync_reset => "none",
5971         oe_async_reset => "none",
5972         oe_power_up => "low",
5973         oe_register_mode => "none",
5974         oe_sync_reset => "none",
5975         operation_mode => "output",
5976         output_async_reset => "none",
5977         output_power_up => "low",
5978         output_register_mode => "none",
5979         output_sync_reset => "none")
5980 -- pragma translate_on
5981 PORT MAP (
5982         datain => \vga_driver_unit|hsync_state_1\,
5983         devclrn => ww_devclrn,
5984         devpor => ww_devpor,
5985         devoe => ww_devoe,
5986         oe => VCC,
5987         padio => ww_d_set_column_counter);
5988
5989 d_set_line_counter_out : stratix_io
5990 -- pragma translate_off
5991 GENERIC MAP (
5992         ddio_mode => "none",
5993         input_async_reset => "none",
5994         input_power_up => "low",
5995         input_register_mode => "none",
5996         input_sync_reset => "none",
5997         oe_async_reset => "none",
5998         oe_power_up => "low",
5999         oe_register_mode => "none",
6000         oe_sync_reset => "none",
6001         operation_mode => "output",
6002         output_async_reset => "none",
6003         output_power_up => "low",
6004         output_register_mode => "none",
6005         output_sync_reset => "none")
6006 -- pragma translate_on
6007 PORT MAP (
6008         datain => \vga_driver_unit|vsync_state_1\,
6009         devclrn => ww_devclrn,
6010         devpor => ww_devpor,
6011         devoe => ww_devoe,
6012         oe => VCC,
6013         padio => ww_d_set_line_counter);
6014
6015 \d_hsync_counter_out_0_\ : stratix_io
6016 -- pragma translate_off
6017 GENERIC MAP (
6018         ddio_mode => "none",
6019         input_async_reset => "none",
6020         input_power_up => "low",
6021         input_register_mode => "none",
6022         input_sync_reset => "none",
6023         oe_async_reset => "none",
6024         oe_power_up => "low",
6025         oe_register_mode => "none",
6026         oe_sync_reset => "none",
6027         operation_mode => "output",
6028         output_async_reset => "none",
6029         output_power_up => "low",
6030         output_register_mode => "none",
6031         output_sync_reset => "none")
6032 -- pragma translate_on
6033 PORT MAP (
6034         datain => \vga_driver_unit|hsync_counter_0\,
6035         devclrn => ww_devclrn,
6036         devpor => ww_devpor,
6037         devoe => ww_devoe,
6038         oe => VCC,
6039         padio => ww_d_hsync_counter(0));
6040
6041 \d_hsync_counter_out_1_\ : stratix_io
6042 -- pragma translate_off
6043 GENERIC MAP (
6044         ddio_mode => "none",
6045         input_async_reset => "none",
6046         input_power_up => "low",
6047         input_register_mode => "none",
6048         input_sync_reset => "none",
6049         oe_async_reset => "none",
6050         oe_power_up => "low",
6051         oe_register_mode => "none",
6052         oe_sync_reset => "none",
6053         operation_mode => "output",
6054         output_async_reset => "none",
6055         output_power_up => "low",
6056         output_register_mode => "none",
6057         output_sync_reset => "none")
6058 -- pragma translate_on
6059 PORT MAP (
6060         datain => \vga_driver_unit|hsync_counter_1\,
6061         devclrn => ww_devclrn,
6062         devpor => ww_devpor,
6063         devoe => ww_devoe,
6064         oe => VCC,
6065         padio => ww_d_hsync_counter(1));
6066
6067 \d_hsync_counter_out_2_\ : stratix_io
6068 -- pragma translate_off
6069 GENERIC MAP (
6070         ddio_mode => "none",
6071         input_async_reset => "none",
6072         input_power_up => "low",
6073         input_register_mode => "none",
6074         input_sync_reset => "none",
6075         oe_async_reset => "none",
6076         oe_power_up => "low",
6077         oe_register_mode => "none",
6078         oe_sync_reset => "none",
6079         operation_mode => "output",
6080         output_async_reset => "none",
6081         output_power_up => "low",
6082         output_register_mode => "none",
6083         output_sync_reset => "none")
6084 -- pragma translate_on
6085 PORT MAP (
6086         datain => \vga_driver_unit|hsync_counter_2\,
6087         devclrn => ww_devclrn,
6088         devpor => ww_devpor,
6089         devoe => ww_devoe,
6090         oe => VCC,
6091         padio => ww_d_hsync_counter(2));
6092
6093 \d_hsync_counter_out_3_\ : stratix_io
6094 -- pragma translate_off
6095 GENERIC MAP (
6096         ddio_mode => "none",
6097         input_async_reset => "none",
6098         input_power_up => "low",
6099         input_register_mode => "none",
6100         input_sync_reset => "none",
6101         oe_async_reset => "none",
6102         oe_power_up => "low",
6103         oe_register_mode => "none",
6104         oe_sync_reset => "none",
6105         operation_mode => "output",
6106         output_async_reset => "none",
6107         output_power_up => "low",
6108         output_register_mode => "none",
6109         output_sync_reset => "none")
6110 -- pragma translate_on
6111 PORT MAP (
6112         datain => \vga_driver_unit|hsync_counter_3\,
6113         devclrn => ww_devclrn,
6114         devpor => ww_devpor,
6115         devoe => ww_devoe,
6116         oe => VCC,
6117         padio => ww_d_hsync_counter(3));
6118
6119 \d_hsync_counter_out_4_\ : stratix_io
6120 -- pragma translate_off
6121 GENERIC MAP (
6122         ddio_mode => "none",
6123         input_async_reset => "none",
6124         input_power_up => "low",
6125         input_register_mode => "none",
6126         input_sync_reset => "none",
6127         oe_async_reset => "none",
6128         oe_power_up => "low",
6129         oe_register_mode => "none",
6130         oe_sync_reset => "none",
6131         operation_mode => "output",
6132         output_async_reset => "none",
6133         output_power_up => "low",
6134         output_register_mode => "none",
6135         output_sync_reset => "none")
6136 -- pragma translate_on
6137 PORT MAP (
6138         datain => \vga_driver_unit|hsync_counter_4\,
6139         devclrn => ww_devclrn,
6140         devpor => ww_devpor,
6141         devoe => ww_devoe,
6142         oe => VCC,
6143         padio => ww_d_hsync_counter(4));
6144
6145 \d_hsync_counter_out_5_\ : stratix_io
6146 -- pragma translate_off
6147 GENERIC MAP (
6148         ddio_mode => "none",
6149         input_async_reset => "none",
6150         input_power_up => "low",
6151         input_register_mode => "none",
6152         input_sync_reset => "none",
6153         oe_async_reset => "none",
6154         oe_power_up => "low",
6155         oe_register_mode => "none",
6156         oe_sync_reset => "none",
6157         operation_mode => "output",
6158         output_async_reset => "none",
6159         output_power_up => "low",
6160         output_register_mode => "none",
6161         output_sync_reset => "none")
6162 -- pragma translate_on
6163 PORT MAP (
6164         datain => \vga_driver_unit|hsync_counter_5\,
6165         devclrn => ww_devclrn,
6166         devpor => ww_devpor,
6167         devoe => ww_devoe,
6168         oe => VCC,
6169         padio => ww_d_hsync_counter(5));
6170
6171 \d_hsync_counter_out_6_\ : stratix_io
6172 -- pragma translate_off
6173 GENERIC MAP (
6174         ddio_mode => "none",
6175         input_async_reset => "none",
6176         input_power_up => "low",
6177         input_register_mode => "none",
6178         input_sync_reset => "none",
6179         oe_async_reset => "none",
6180         oe_power_up => "low",
6181         oe_register_mode => "none",
6182         oe_sync_reset => "none",
6183         operation_mode => "output",
6184         output_async_reset => "none",
6185         output_power_up => "low",
6186         output_register_mode => "none",
6187         output_sync_reset => "none")
6188 -- pragma translate_on
6189 PORT MAP (
6190         datain => \vga_driver_unit|hsync_counter_6\,
6191         devclrn => ww_devclrn,
6192         devpor => ww_devpor,
6193         devoe => ww_devoe,
6194         oe => VCC,
6195         padio => ww_d_hsync_counter(6));
6196
6197 \d_hsync_counter_out_7_\ : stratix_io
6198 -- pragma translate_off
6199 GENERIC MAP (
6200         ddio_mode => "none",
6201         input_async_reset => "none",
6202         input_power_up => "low",
6203         input_register_mode => "none",
6204         input_sync_reset => "none",
6205         oe_async_reset => "none",
6206         oe_power_up => "low",
6207         oe_register_mode => "none",
6208         oe_sync_reset => "none",
6209         operation_mode => "output",
6210         output_async_reset => "none",
6211         output_power_up => "low",
6212         output_register_mode => "none",
6213         output_sync_reset => "none")
6214 -- pragma translate_on
6215 PORT MAP (
6216         datain => \vga_driver_unit|hsync_counter_7\,
6217         devclrn => ww_devclrn,
6218         devpor => ww_devpor,
6219         devoe => ww_devoe,
6220         oe => VCC,
6221         padio => ww_d_hsync_counter(7));
6222
6223 \d_hsync_counter_out_8_\ : stratix_io
6224 -- pragma translate_off
6225 GENERIC MAP (
6226         ddio_mode => "none",
6227         input_async_reset => "none",
6228         input_power_up => "low",
6229         input_register_mode => "none",
6230         input_sync_reset => "none",
6231         oe_async_reset => "none",
6232         oe_power_up => "low",
6233         oe_register_mode => "none",
6234         oe_sync_reset => "none",
6235         operation_mode => "output",
6236         output_async_reset => "none",
6237         output_power_up => "low",
6238         output_register_mode => "none",
6239         output_sync_reset => "none")
6240 -- pragma translate_on
6241 PORT MAP (
6242         datain => \vga_driver_unit|hsync_counter_8\,
6243         devclrn => ww_devclrn,
6244         devpor => ww_devpor,
6245         devoe => ww_devoe,
6246         oe => VCC,
6247         padio => ww_d_hsync_counter(8));
6248
6249 \d_hsync_counter_out_9_\ : stratix_io
6250 -- pragma translate_off
6251 GENERIC MAP (
6252         ddio_mode => "none",
6253         input_async_reset => "none",
6254         input_power_up => "low",
6255         input_register_mode => "none",
6256         input_sync_reset => "none",
6257         oe_async_reset => "none",
6258         oe_power_up => "low",
6259         oe_register_mode => "none",
6260         oe_sync_reset => "none",
6261         operation_mode => "output",
6262         output_async_reset => "none",
6263         output_power_up => "low",
6264         output_register_mode => "none",
6265         output_sync_reset => "none")
6266 -- pragma translate_on
6267 PORT MAP (
6268         datain => \vga_driver_unit|hsync_counter_9\,
6269         devclrn => ww_devclrn,
6270         devpor => ww_devpor,
6271         devoe => ww_devoe,
6272         oe => VCC,
6273         padio => ww_d_hsync_counter(9));
6274
6275 \d_vsync_counter_out_0_\ : stratix_io
6276 -- pragma translate_off
6277 GENERIC MAP (
6278         ddio_mode => "none",
6279         input_async_reset => "none",
6280         input_power_up => "low",
6281         input_register_mode => "none",
6282         input_sync_reset => "none",
6283         oe_async_reset => "none",
6284         oe_power_up => "low",
6285         oe_register_mode => "none",
6286         oe_sync_reset => "none",
6287         operation_mode => "output",
6288         output_async_reset => "none",
6289         output_power_up => "low",
6290         output_register_mode => "none",
6291         output_sync_reset => "none")
6292 -- pragma translate_on
6293 PORT MAP (
6294         datain => \vga_driver_unit|vsync_counter_0\,
6295         devclrn => ww_devclrn,
6296         devpor => ww_devpor,
6297         devoe => ww_devoe,
6298         oe => VCC,
6299         padio => ww_d_vsync_counter(0));
6300
6301 \d_vsync_counter_out_1_\ : stratix_io
6302 -- pragma translate_off
6303 GENERIC MAP (
6304         ddio_mode => "none",
6305         input_async_reset => "none",
6306         input_power_up => "low",
6307         input_register_mode => "none",
6308         input_sync_reset => "none",
6309         oe_async_reset => "none",
6310         oe_power_up => "low",
6311         oe_register_mode => "none",
6312         oe_sync_reset => "none",
6313         operation_mode => "output",
6314         output_async_reset => "none",
6315         output_power_up => "low",
6316         output_register_mode => "none",
6317         output_sync_reset => "none")
6318 -- pragma translate_on
6319 PORT MAP (
6320         datain => \vga_driver_unit|vsync_counter_1\,
6321         devclrn => ww_devclrn,
6322         devpor => ww_devpor,
6323         devoe => ww_devoe,
6324         oe => VCC,
6325         padio => ww_d_vsync_counter(1));
6326
6327 \d_vsync_counter_out_2_\ : stratix_io
6328 -- pragma translate_off
6329 GENERIC MAP (
6330         ddio_mode => "none",
6331         input_async_reset => "none",
6332         input_power_up => "low",
6333         input_register_mode => "none",
6334         input_sync_reset => "none",
6335         oe_async_reset => "none",
6336         oe_power_up => "low",
6337         oe_register_mode => "none",
6338         oe_sync_reset => "none",
6339         operation_mode => "output",
6340         output_async_reset => "none",
6341         output_power_up => "low",
6342         output_register_mode => "none",
6343         output_sync_reset => "none")
6344 -- pragma translate_on
6345 PORT MAP (
6346         datain => \vga_driver_unit|vsync_counter_2\,
6347         devclrn => ww_devclrn,
6348         devpor => ww_devpor,
6349         devoe => ww_devoe,
6350         oe => VCC,
6351         padio => ww_d_vsync_counter(2));
6352
6353 \d_vsync_counter_out_3_\ : stratix_io
6354 -- pragma translate_off
6355 GENERIC MAP (
6356         ddio_mode => "none",
6357         input_async_reset => "none",
6358         input_power_up => "low",
6359         input_register_mode => "none",
6360         input_sync_reset => "none",
6361         oe_async_reset => "none",
6362         oe_power_up => "low",
6363         oe_register_mode => "none",
6364         oe_sync_reset => "none",
6365         operation_mode => "output",
6366         output_async_reset => "none",
6367         output_power_up => "low",
6368         output_register_mode => "none",
6369         output_sync_reset => "none")
6370 -- pragma translate_on
6371 PORT MAP (
6372         datain => \vga_driver_unit|vsync_counter_3\,
6373         devclrn => ww_devclrn,
6374         devpor => ww_devpor,
6375         devoe => ww_devoe,
6376         oe => VCC,
6377         padio => ww_d_vsync_counter(3));
6378
6379 \d_vsync_counter_out_4_\ : stratix_io
6380 -- pragma translate_off
6381 GENERIC MAP (
6382         ddio_mode => "none",
6383         input_async_reset => "none",
6384         input_power_up => "low",
6385         input_register_mode => "none",
6386         input_sync_reset => "none",
6387         oe_async_reset => "none",
6388         oe_power_up => "low",
6389         oe_register_mode => "none",
6390         oe_sync_reset => "none",
6391         operation_mode => "output",
6392         output_async_reset => "none",
6393         output_power_up => "low",
6394         output_register_mode => "none",
6395         output_sync_reset => "none")
6396 -- pragma translate_on
6397 PORT MAP (
6398         datain => \vga_driver_unit|vsync_counter_4\,
6399         devclrn => ww_devclrn,
6400         devpor => ww_devpor,
6401         devoe => ww_devoe,
6402         oe => VCC,
6403         padio => ww_d_vsync_counter(4));
6404
6405 \d_vsync_counter_out_5_\ : stratix_io
6406 -- pragma translate_off
6407 GENERIC MAP (
6408         ddio_mode => "none",
6409         input_async_reset => "none",
6410         input_power_up => "low",
6411         input_register_mode => "none",
6412         input_sync_reset => "none",
6413         oe_async_reset => "none",
6414         oe_power_up => "low",
6415         oe_register_mode => "none",
6416         oe_sync_reset => "none",
6417         operation_mode => "output",
6418         output_async_reset => "none",
6419         output_power_up => "low",
6420         output_register_mode => "none",
6421         output_sync_reset => "none")
6422 -- pragma translate_on
6423 PORT MAP (
6424         datain => \vga_driver_unit|vsync_counter_5\,
6425         devclrn => ww_devclrn,
6426         devpor => ww_devpor,
6427         devoe => ww_devoe,
6428         oe => VCC,
6429         padio => ww_d_vsync_counter(5));
6430
6431 \d_vsync_counter_out_6_\ : stratix_io
6432 -- pragma translate_off
6433 GENERIC MAP (
6434         ddio_mode => "none",
6435         input_async_reset => "none",
6436         input_power_up => "low",
6437         input_register_mode => "none",
6438         input_sync_reset => "none",
6439         oe_async_reset => "none",
6440         oe_power_up => "low",
6441         oe_register_mode => "none",
6442         oe_sync_reset => "none",
6443         operation_mode => "output",
6444         output_async_reset => "none",
6445         output_power_up => "low",
6446         output_register_mode => "none",
6447         output_sync_reset => "none")
6448 -- pragma translate_on
6449 PORT MAP (
6450         datain => \vga_driver_unit|vsync_counter_6\,
6451         devclrn => ww_devclrn,
6452         devpor => ww_devpor,
6453         devoe => ww_devoe,
6454         oe => VCC,
6455         padio => ww_d_vsync_counter(6));
6456
6457 \d_vsync_counter_out_7_\ : stratix_io
6458 -- pragma translate_off
6459 GENERIC MAP (
6460         ddio_mode => "none",
6461         input_async_reset => "none",
6462         input_power_up => "low",
6463         input_register_mode => "none",
6464         input_sync_reset => "none",
6465         oe_async_reset => "none",
6466         oe_power_up => "low",
6467         oe_register_mode => "none",
6468         oe_sync_reset => "none",
6469         operation_mode => "output",
6470         output_async_reset => "none",
6471         output_power_up => "low",
6472         output_register_mode => "none",
6473         output_sync_reset => "none")
6474 -- pragma translate_on
6475 PORT MAP (
6476         datain => \vga_driver_unit|vsync_counter_7\,
6477         devclrn => ww_devclrn,
6478         devpor => ww_devpor,
6479         devoe => ww_devoe,
6480         oe => VCC,
6481         padio => ww_d_vsync_counter(7));
6482
6483 \d_vsync_counter_out_8_\ : stratix_io
6484 -- pragma translate_off
6485 GENERIC MAP (
6486         ddio_mode => "none",
6487         input_async_reset => "none",
6488         input_power_up => "low",
6489         input_register_mode => "none",
6490         input_sync_reset => "none",
6491         oe_async_reset => "none",
6492         oe_power_up => "low",
6493         oe_register_mode => "none",
6494         oe_sync_reset => "none",
6495         operation_mode => "output",
6496         output_async_reset => "none",
6497         output_power_up => "low",
6498         output_register_mode => "none",
6499         output_sync_reset => "none")
6500 -- pragma translate_on
6501 PORT MAP (
6502         datain => \vga_driver_unit|vsync_counter_8\,
6503         devclrn => ww_devclrn,
6504         devpor => ww_devpor,
6505         devoe => ww_devoe,
6506         oe => VCC,
6507         padio => ww_d_vsync_counter(8));
6508
6509 \d_vsync_counter_out_9_\ : stratix_io
6510 -- pragma translate_off
6511 GENERIC MAP (
6512         ddio_mode => "none",
6513         input_async_reset => "none",
6514         input_power_up => "low",
6515         input_register_mode => "none",
6516         input_sync_reset => "none",
6517         oe_async_reset => "none",
6518         oe_power_up => "low",
6519         oe_register_mode => "none",
6520         oe_sync_reset => "none",
6521         operation_mode => "output",
6522         output_async_reset => "none",
6523         output_power_up => "low",
6524         output_register_mode => "none",
6525         output_sync_reset => "none")
6526 -- pragma translate_on
6527 PORT MAP (
6528         datain => \vga_driver_unit|vsync_counter_9\,
6529         devclrn => ww_devclrn,
6530         devpor => ww_devpor,
6531         devoe => ww_devoe,
6532         oe => VCC,
6533         padio => ww_d_vsync_counter(9));
6534
6535 d_set_hsync_counter_out : stratix_io
6536 -- pragma translate_off
6537 GENERIC MAP (
6538         ddio_mode => "none",
6539         input_async_reset => "none",
6540         input_power_up => "low",
6541         input_register_mode => "none",
6542         input_sync_reset => "none",
6543         oe_async_reset => "none",
6544         oe_power_up => "low",
6545         oe_register_mode => "none",
6546         oe_sync_reset => "none",
6547         operation_mode => "output",
6548         output_async_reset => "none",
6549         output_power_up => "low",
6550         output_register_mode => "none",
6551         output_sync_reset => "none")
6552 -- pragma translate_on
6553 PORT MAP (
6554         datain => \vga_driver_unit|d_set_hsync_counter\,
6555         devclrn => ww_devclrn,
6556         devpor => ww_devpor,
6557         devoe => ww_devoe,
6558         oe => VCC,
6559         padio => ww_d_set_hsync_counter);
6560
6561 d_set_vsync_counter_out : stratix_io
6562 -- pragma translate_off
6563 GENERIC MAP (
6564         ddio_mode => "none",
6565         input_async_reset => "none",
6566         input_power_up => "low",
6567         input_register_mode => "none",
6568         input_sync_reset => "none",
6569         oe_async_reset => "none",
6570         oe_power_up => "low",
6571         oe_register_mode => "none",
6572         oe_sync_reset => "none",
6573         operation_mode => "output",
6574         output_async_reset => "none",
6575         output_power_up => "low",
6576         output_register_mode => "none",
6577         output_sync_reset => "none")
6578 -- pragma translate_on
6579 PORT MAP (
6580         datain => \vga_driver_unit|d_set_vsync_counter\,
6581         devclrn => ww_devclrn,
6582         devpor => ww_devpor,
6583         devoe => ww_devoe,
6584         oe => VCC,
6585         padio => ww_d_set_vsync_counter);
6586
6587 d_h_enable_out : stratix_io
6588 -- pragma translate_off
6589 GENERIC MAP (
6590         ddio_mode => "none",
6591         input_async_reset => "none",
6592         input_power_up => "low",
6593         input_register_mode => "none",
6594         input_sync_reset => "none",
6595         oe_async_reset => "none",
6596         oe_power_up => "low",
6597         oe_register_mode => "none",
6598         oe_sync_reset => "none",
6599         operation_mode => "output",
6600         output_async_reset => "none",
6601         output_power_up => "low",
6602         output_register_mode => "none",
6603         output_sync_reset => "none")
6604 -- pragma translate_on
6605 PORT MAP (
6606         datain => \vga_driver_unit|h_enable_sig\,
6607         devclrn => ww_devclrn,
6608         devpor => ww_devpor,
6609         devoe => ww_devoe,
6610         oe => VCC,
6611         padio => ww_d_h_enable);
6612
6613 d_v_enable_out : stratix_io
6614 -- pragma translate_off
6615 GENERIC MAP (
6616         ddio_mode => "none",
6617         input_async_reset => "none",
6618         input_power_up => "low",
6619         input_register_mode => "none",
6620         input_sync_reset => "none",
6621         oe_async_reset => "none",
6622         oe_power_up => "low",
6623         oe_register_mode => "none",
6624         oe_sync_reset => "none",
6625         operation_mode => "output",
6626         output_async_reset => "none",
6627         output_power_up => "low",
6628         output_register_mode => "none",
6629         output_sync_reset => "none")
6630 -- pragma translate_on
6631 PORT MAP (
6632         datain => \vga_driver_unit|v_enable_sig\,
6633         devclrn => ww_devclrn,
6634         devpor => ww_devpor,
6635         devoe => ww_devoe,
6636         oe => VCC,
6637         padio => ww_d_v_enable);
6638
6639 d_r_out : stratix_io
6640 -- pragma translate_off
6641 GENERIC MAP (
6642         ddio_mode => "none",
6643         input_async_reset => "none",
6644         input_power_up => "low",
6645         input_register_mode => "none",
6646         input_sync_reset => "none",
6647         oe_async_reset => "none",
6648         oe_power_up => "low",
6649         oe_register_mode => "none",
6650         oe_sync_reset => "none",
6651         operation_mode => "output",
6652         output_async_reset => "none",
6653         output_power_up => "low",
6654         output_register_mode => "none",
6655         output_sync_reset => "none")
6656 -- pragma translate_on
6657 PORT MAP (
6658         datain => \vga_control_unit|r\,
6659         devclrn => ww_devclrn,
6660         devpor => ww_devpor,
6661         devoe => ww_devoe,
6662         oe => VCC,
6663         padio => ww_d_r);
6664
6665 d_g_out : stratix_io
6666 -- pragma translate_off
6667 GENERIC MAP (
6668         ddio_mode => "none",
6669         input_async_reset => "none",
6670         input_power_up => "low",
6671         input_register_mode => "none",
6672         input_sync_reset => "none",
6673         oe_async_reset => "none",
6674         oe_power_up => "low",
6675         oe_register_mode => "none",
6676         oe_sync_reset => "none",
6677         operation_mode => "output",
6678         output_async_reset => "none",
6679         output_power_up => "low",
6680         output_register_mode => "none",
6681         output_sync_reset => "none")
6682 -- pragma translate_on
6683 PORT MAP (
6684         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
6685         devclrn => ww_devclrn,
6686         devpor => ww_devpor,
6687         devoe => ww_devoe,
6688         oe => VCC,
6689         padio => ww_d_g);
6690
6691 d_b_out : stratix_io
6692 -- pragma translate_off
6693 GENERIC MAP (
6694         ddio_mode => "none",
6695         input_async_reset => "none",
6696         input_power_up => "low",
6697         input_register_mode => "none",
6698         input_sync_reset => "none",
6699         oe_async_reset => "none",
6700         oe_power_up => "low",
6701         oe_register_mode => "none",
6702         oe_sync_reset => "none",
6703         operation_mode => "output",
6704         output_async_reset => "none",
6705         output_power_up => "low",
6706         output_register_mode => "none",
6707         output_sync_reset => "none")
6708 -- pragma translate_on
6709 PORT MAP (
6710         datain => \vga_control_unit|b\,
6711         devclrn => ww_devclrn,
6712         devpor => ww_devpor,
6713         devoe => ww_devoe,
6714         oe => VCC,
6715         padio => ww_d_b);
6716
6717 \d_hsync_state_out_6_\ : stratix_io
6718 -- pragma translate_off
6719 GENERIC MAP (
6720         ddio_mode => "none",
6721         input_async_reset => "none",
6722         input_power_up => "low",
6723         input_register_mode => "none",
6724         input_sync_reset => "none",
6725         oe_async_reset => "none",
6726         oe_power_up => "low",
6727         oe_register_mode => "none",
6728         oe_sync_reset => "none",
6729         operation_mode => "output",
6730         output_async_reset => "none",
6731         output_power_up => "low",
6732         output_register_mode => "none",
6733         output_sync_reset => "none")
6734 -- pragma translate_on
6735 PORT MAP (
6736         datain => \vga_driver_unit|hsync_state_6\,
6737         devclrn => ww_devclrn,
6738         devpor => ww_devpor,
6739         devoe => ww_devoe,
6740         oe => VCC,
6741         padio => ww_d_hsync_state(6));
6742
6743 \d_hsync_state_out_5_\ : stratix_io
6744 -- pragma translate_off
6745 GENERIC MAP (
6746         ddio_mode => "none",
6747         input_async_reset => "none",
6748         input_power_up => "low",
6749         input_register_mode => "none",
6750         input_sync_reset => "none",
6751         oe_async_reset => "none",
6752         oe_power_up => "low",
6753         oe_register_mode => "none",
6754         oe_sync_reset => "none",
6755         operation_mode => "output",
6756         output_async_reset => "none",
6757         output_power_up => "low",
6758         output_register_mode => "none",
6759         output_sync_reset => "none")
6760 -- pragma translate_on
6761 PORT MAP (
6762         datain => \vga_driver_unit|hsync_state_5\,
6763         devclrn => ww_devclrn,
6764         devpor => ww_devpor,
6765         devoe => ww_devoe,
6766         oe => VCC,
6767         padio => ww_d_hsync_state(5));
6768
6769 \d_hsync_state_out_4_\ : stratix_io
6770 -- pragma translate_off
6771 GENERIC MAP (
6772         ddio_mode => "none",
6773         input_async_reset => "none",
6774         input_power_up => "low",
6775         input_register_mode => "none",
6776         input_sync_reset => "none",
6777         oe_async_reset => "none",
6778         oe_power_up => "low",
6779         oe_register_mode => "none",
6780         oe_sync_reset => "none",
6781         operation_mode => "output",
6782         output_async_reset => "none",
6783         output_power_up => "low",
6784         output_register_mode => "none",
6785         output_sync_reset => "none")
6786 -- pragma translate_on
6787 PORT MAP (
6788         datain => \vga_driver_unit|hsync_state_4\,
6789         devclrn => ww_devclrn,
6790         devpor => ww_devpor,
6791         devoe => ww_devoe,
6792         oe => VCC,
6793         padio => ww_d_hsync_state(4));
6794
6795 \d_hsync_state_out_3_\ : stratix_io
6796 -- pragma translate_off
6797 GENERIC MAP (
6798         ddio_mode => "none",
6799         input_async_reset => "none",
6800         input_power_up => "low",
6801         input_register_mode => "none",
6802         input_sync_reset => "none",
6803         oe_async_reset => "none",
6804         oe_power_up => "low",
6805         oe_register_mode => "none",
6806         oe_sync_reset => "none",
6807         operation_mode => "output",
6808         output_async_reset => "none",
6809         output_power_up => "low",
6810         output_register_mode => "none",
6811         output_sync_reset => "none")
6812 -- pragma translate_on
6813 PORT MAP (
6814         datain => \vga_driver_unit|hsync_state_3\,
6815         devclrn => ww_devclrn,
6816         devpor => ww_devpor,
6817         devoe => ww_devoe,
6818         oe => VCC,
6819         padio => ww_d_hsync_state(3));
6820
6821 \d_hsync_state_out_2_\ : stratix_io
6822 -- pragma translate_off
6823 GENERIC MAP (
6824         ddio_mode => "none",
6825         input_async_reset => "none",
6826         input_power_up => "low",
6827         input_register_mode => "none",
6828         input_sync_reset => "none",
6829         oe_async_reset => "none",
6830         oe_power_up => "low",
6831         oe_register_mode => "none",
6832         oe_sync_reset => "none",
6833         operation_mode => "output",
6834         output_async_reset => "none",
6835         output_power_up => "low",
6836         output_register_mode => "none",
6837         output_sync_reset => "none")
6838 -- pragma translate_on
6839 PORT MAP (
6840         datain => \vga_driver_unit|hsync_state_2\,
6841         devclrn => ww_devclrn,
6842         devpor => ww_devpor,
6843         devoe => ww_devoe,
6844         oe => VCC,
6845         padio => ww_d_hsync_state(2));
6846
6847 \d_hsync_state_out_1_\ : stratix_io
6848 -- pragma translate_off
6849 GENERIC MAP (
6850         ddio_mode => "none",
6851         input_async_reset => "none",
6852         input_power_up => "low",
6853         input_register_mode => "none",
6854         input_sync_reset => "none",
6855         oe_async_reset => "none",
6856         oe_power_up => "low",
6857         oe_register_mode => "none",
6858         oe_sync_reset => "none",
6859         operation_mode => "output",
6860         output_async_reset => "none",
6861         output_power_up => "low",
6862         output_register_mode => "none",
6863         output_sync_reset => "none")
6864 -- pragma translate_on
6865 PORT MAP (
6866         datain => \vga_driver_unit|hsync_state_1\,
6867         devclrn => ww_devclrn,
6868         devpor => ww_devpor,
6869         devoe => ww_devoe,
6870         oe => VCC,
6871         padio => ww_d_hsync_state(1));
6872
6873 \d_hsync_state_out_0_\ : stratix_io
6874 -- pragma translate_off
6875 GENERIC MAP (
6876         ddio_mode => "none",
6877         input_async_reset => "none",
6878         input_power_up => "low",
6879         input_register_mode => "none",
6880         input_sync_reset => "none",
6881         oe_async_reset => "none",
6882         oe_power_up => "low",
6883         oe_register_mode => "none",
6884         oe_sync_reset => "none",
6885         operation_mode => "output",
6886         output_async_reset => "none",
6887         output_power_up => "low",
6888         output_register_mode => "none",
6889         output_sync_reset => "none")
6890 -- pragma translate_on
6891 PORT MAP (
6892         datain => \vga_driver_unit|hsync_state_0\,
6893         devclrn => ww_devclrn,
6894         devpor => ww_devpor,
6895         devoe => ww_devoe,
6896         oe => VCC,
6897         padio => ww_d_hsync_state(0));
6898
6899 \d_vsync_state_out_6_\ : stratix_io
6900 -- pragma translate_off
6901 GENERIC MAP (
6902         ddio_mode => "none",
6903         input_async_reset => "none",
6904         input_power_up => "low",
6905         input_register_mode => "none",
6906         input_sync_reset => "none",
6907         oe_async_reset => "none",
6908         oe_power_up => "low",
6909         oe_register_mode => "none",
6910         oe_sync_reset => "none",
6911         operation_mode => "output",
6912         output_async_reset => "none",
6913         output_power_up => "low",
6914         output_register_mode => "none",
6915         output_sync_reset => "none")
6916 -- pragma translate_on
6917 PORT MAP (
6918         datain => \vga_driver_unit|vsync_state_6\,
6919         devclrn => ww_devclrn,
6920         devpor => ww_devpor,
6921         devoe => ww_devoe,
6922         oe => VCC,
6923         padio => ww_d_vsync_state(6));
6924
6925 \d_vsync_state_out_5_\ : stratix_io
6926 -- pragma translate_off
6927 GENERIC MAP (
6928         ddio_mode => "none",
6929         input_async_reset => "none",
6930         input_power_up => "low",
6931         input_register_mode => "none",
6932         input_sync_reset => "none",
6933         oe_async_reset => "none",
6934         oe_power_up => "low",
6935         oe_register_mode => "none",
6936         oe_sync_reset => "none",
6937         operation_mode => "output",
6938         output_async_reset => "none",
6939         output_power_up => "low",
6940         output_register_mode => "none",
6941         output_sync_reset => "none")
6942 -- pragma translate_on
6943 PORT MAP (
6944         datain => \vga_driver_unit|vsync_state_5\,
6945         devclrn => ww_devclrn,
6946         devpor => ww_devpor,
6947         devoe => ww_devoe,
6948         oe => VCC,
6949         padio => ww_d_vsync_state(5));
6950
6951 \d_vsync_state_out_4_\ : stratix_io
6952 -- pragma translate_off
6953 GENERIC MAP (
6954         ddio_mode => "none",
6955         input_async_reset => "none",
6956         input_power_up => "low",
6957         input_register_mode => "none",
6958         input_sync_reset => "none",
6959         oe_async_reset => "none",
6960         oe_power_up => "low",
6961         oe_register_mode => "none",
6962         oe_sync_reset => "none",
6963         operation_mode => "output",
6964         output_async_reset => "none",
6965         output_power_up => "low",
6966         output_register_mode => "none",
6967         output_sync_reset => "none")
6968 -- pragma translate_on
6969 PORT MAP (
6970         datain => \vga_driver_unit|vsync_state_4\,
6971         devclrn => ww_devclrn,
6972         devpor => ww_devpor,
6973         devoe => ww_devoe,
6974         oe => VCC,
6975         padio => ww_d_vsync_state(4));
6976
6977 \d_vsync_state_out_3_\ : stratix_io
6978 -- pragma translate_off
6979 GENERIC MAP (
6980         ddio_mode => "none",
6981         input_async_reset => "none",
6982         input_power_up => "low",
6983         input_register_mode => "none",
6984         input_sync_reset => "none",
6985         oe_async_reset => "none",
6986         oe_power_up => "low",
6987         oe_register_mode => "none",
6988         oe_sync_reset => "none",
6989         operation_mode => "output",
6990         output_async_reset => "none",
6991         output_power_up => "low",
6992         output_register_mode => "none",
6993         output_sync_reset => "none")
6994 -- pragma translate_on
6995 PORT MAP (
6996         datain => \vga_driver_unit|vsync_state_3\,
6997         devclrn => ww_devclrn,
6998         devpor => ww_devpor,
6999         devoe => ww_devoe,
7000         oe => VCC,
7001         padio => ww_d_vsync_state(3));
7002
7003 \d_vsync_state_out_2_\ : stratix_io
7004 -- pragma translate_off
7005 GENERIC MAP (
7006         ddio_mode => "none",
7007         input_async_reset => "none",
7008         input_power_up => "low",
7009         input_register_mode => "none",
7010         input_sync_reset => "none",
7011         oe_async_reset => "none",
7012         oe_power_up => "low",
7013         oe_register_mode => "none",
7014         oe_sync_reset => "none",
7015         operation_mode => "output",
7016         output_async_reset => "none",
7017         output_power_up => "low",
7018         output_register_mode => "none",
7019         output_sync_reset => "none")
7020 -- pragma translate_on
7021 PORT MAP (
7022         datain => \vga_driver_unit|vsync_state_2\,
7023         devclrn => ww_devclrn,
7024         devpor => ww_devpor,
7025         devoe => ww_devoe,
7026         oe => VCC,
7027         padio => ww_d_vsync_state(2));
7028
7029 \d_vsync_state_out_1_\ : stratix_io
7030 -- pragma translate_off
7031 GENERIC MAP (
7032         ddio_mode => "none",
7033         input_async_reset => "none",
7034         input_power_up => "low",
7035         input_register_mode => "none",
7036         input_sync_reset => "none",
7037         oe_async_reset => "none",
7038         oe_power_up => "low",
7039         oe_register_mode => "none",
7040         oe_sync_reset => "none",
7041         operation_mode => "output",
7042         output_async_reset => "none",
7043         output_power_up => "low",
7044         output_register_mode => "none",
7045         output_sync_reset => "none")
7046 -- pragma translate_on
7047 PORT MAP (
7048         datain => \vga_driver_unit|vsync_state_1\,
7049         devclrn => ww_devclrn,
7050         devpor => ww_devpor,
7051         devoe => ww_devoe,
7052         oe => VCC,
7053         padio => ww_d_vsync_state(1));
7054
7055 \d_vsync_state_out_0_\ : stratix_io
7056 -- pragma translate_off
7057 GENERIC MAP (
7058         ddio_mode => "none",
7059         input_async_reset => "none",
7060         input_power_up => "low",
7061         input_register_mode => "none",
7062         input_sync_reset => "none",
7063         oe_async_reset => "none",
7064         oe_power_up => "low",
7065         oe_register_mode => "none",
7066         oe_sync_reset => "none",
7067         operation_mode => "output",
7068         output_async_reset => "none",
7069         output_power_up => "low",
7070         output_register_mode => "none",
7071         output_sync_reset => "none")
7072 -- pragma translate_on
7073 PORT MAP (
7074         datain => \vga_driver_unit|vsync_state_0\,
7075         devclrn => ww_devclrn,
7076         devpor => ww_devpor,
7077         devoe => ww_devoe,
7078         oe => VCC,
7079         padio => ww_d_vsync_state(0));
7080
7081 d_state_clk_out : stratix_io
7082 -- pragma translate_off
7083 GENERIC MAP (
7084         ddio_mode => "none",
7085         input_async_reset => "none",
7086         input_power_up => "low",
7087         input_register_mode => "none",
7088         input_sync_reset => "none",
7089         oe_async_reset => "none",
7090         oe_power_up => "low",
7091         oe_register_mode => "none",
7092         oe_sync_reset => "none",
7093         operation_mode => "output",
7094         output_async_reset => "none",
7095         output_power_up => "low",
7096         output_register_mode => "none",
7097         output_sync_reset => "none")
7098 -- pragma translate_on
7099 PORT MAP (
7100         datain => \clk_pin~combout\,
7101         devclrn => ww_devclrn,
7102         devpor => ww_devpor,
7103         devoe => ww_devoe,
7104         oe => VCC,
7105         padio => ww_d_state_clk);
7106
7107 d_toggle_out : stratix_io
7108 -- pragma translate_off
7109 GENERIC MAP (
7110         ddio_mode => "none",
7111         input_async_reset => "none",
7112         input_power_up => "low",
7113         input_register_mode => "none",
7114         input_sync_reset => "none",
7115         oe_async_reset => "none",
7116         oe_power_up => "low",
7117         oe_register_mode => "none",
7118         oe_sync_reset => "none",
7119         operation_mode => "output",
7120         output_async_reset => "none",
7121         output_power_up => "low",
7122         output_register_mode => "none",
7123         output_sync_reset => "none")
7124 -- pragma translate_on
7125 PORT MAP (
7126         datain => \vga_control_unit|toggle_sig\,
7127         devclrn => ww_devclrn,
7128         devpor => ww_devpor,
7129         devoe => ww_devoe,
7130         oe => VCC,
7131         padio => ww_d_toggle);
7132
7133 \d_toggle_counter_out_0_\ : stratix_io
7134 -- pragma translate_off
7135 GENERIC MAP (
7136         ddio_mode => "none",
7137         input_async_reset => "none",
7138         input_power_up => "low",
7139         input_register_mode => "none",
7140         input_sync_reset => "none",
7141         oe_async_reset => "none",
7142         oe_power_up => "low",
7143         oe_register_mode => "none",
7144         oe_sync_reset => "none",
7145         operation_mode => "output",
7146         output_async_reset => "none",
7147         output_power_up => "low",
7148         output_register_mode => "none",
7149         output_sync_reset => "none")
7150 -- pragma translate_on
7151 PORT MAP (
7152         datain => \vga_control_unit|toggle_counter_sig_0\,
7153         devclrn => ww_devclrn,
7154         devpor => ww_devpor,
7155         devoe => ww_devoe,
7156         oe => VCC,
7157         padio => ww_d_toggle_counter(0));
7158
7159 \d_toggle_counter_out_1_\ : stratix_io
7160 -- pragma translate_off
7161 GENERIC MAP (
7162         ddio_mode => "none",
7163         input_async_reset => "none",
7164         input_power_up => "low",
7165         input_register_mode => "none",
7166         input_sync_reset => "none",
7167         oe_async_reset => "none",
7168         oe_power_up => "low",
7169         oe_register_mode => "none",
7170         oe_sync_reset => "none",
7171         operation_mode => "output",
7172         output_async_reset => "none",
7173         output_power_up => "low",
7174         output_register_mode => "none",
7175         output_sync_reset => "none")
7176 -- pragma translate_on
7177 PORT MAP (
7178         datain => \vga_control_unit|toggle_counter_sig_1\,
7179         devclrn => ww_devclrn,
7180         devpor => ww_devpor,
7181         devoe => ww_devoe,
7182         oe => VCC,
7183         padio => ww_d_toggle_counter(1));
7184
7185 \d_toggle_counter_out_2_\ : stratix_io
7186 -- pragma translate_off
7187 GENERIC MAP (
7188         ddio_mode => "none",
7189         input_async_reset => "none",
7190         input_power_up => "low",
7191         input_register_mode => "none",
7192         input_sync_reset => "none",
7193         oe_async_reset => "none",
7194         oe_power_up => "low",
7195         oe_register_mode => "none",
7196         oe_sync_reset => "none",
7197         operation_mode => "output",
7198         output_async_reset => "none",
7199         output_power_up => "low",
7200         output_register_mode => "none",
7201         output_sync_reset => "none")
7202 -- pragma translate_on
7203 PORT MAP (
7204         datain => \vga_control_unit|toggle_counter_sig_2\,
7205         devclrn => ww_devclrn,
7206         devpor => ww_devpor,
7207         devoe => ww_devoe,
7208         oe => VCC,
7209         padio => ww_d_toggle_counter(2));
7210
7211 \d_toggle_counter_out_3_\ : stratix_io
7212 -- pragma translate_off
7213 GENERIC MAP (
7214         ddio_mode => "none",
7215         input_async_reset => "none",
7216         input_power_up => "low",
7217         input_register_mode => "none",
7218         input_sync_reset => "none",
7219         oe_async_reset => "none",
7220         oe_power_up => "low",
7221         oe_register_mode => "none",
7222         oe_sync_reset => "none",
7223         operation_mode => "output",
7224         output_async_reset => "none",
7225         output_power_up => "low",
7226         output_register_mode => "none",
7227         output_sync_reset => "none")
7228 -- pragma translate_on
7229 PORT MAP (
7230         datain => \vga_control_unit|toggle_counter_sig_3\,
7231         devclrn => ww_devclrn,
7232         devpor => ww_devpor,
7233         devoe => ww_devoe,
7234         oe => VCC,
7235         padio => ww_d_toggle_counter(3));
7236
7237 \d_toggle_counter_out_4_\ : stratix_io
7238 -- pragma translate_off
7239 GENERIC MAP (
7240         ddio_mode => "none",
7241         input_async_reset => "none",
7242         input_power_up => "low",
7243         input_register_mode => "none",
7244         input_sync_reset => "none",
7245         oe_async_reset => "none",
7246         oe_power_up => "low",
7247         oe_register_mode => "none",
7248         oe_sync_reset => "none",
7249         operation_mode => "output",
7250         output_async_reset => "none",
7251         output_power_up => "low",
7252         output_register_mode => "none",
7253         output_sync_reset => "none")
7254 -- pragma translate_on
7255 PORT MAP (
7256         datain => \vga_control_unit|toggle_counter_sig_4\,
7257         devclrn => ww_devclrn,
7258         devpor => ww_devpor,
7259         devoe => ww_devoe,
7260         oe => VCC,
7261         padio => ww_d_toggle_counter(4));
7262
7263 \d_toggle_counter_out_5_\ : stratix_io
7264 -- pragma translate_off
7265 GENERIC MAP (
7266         ddio_mode => "none",
7267         input_async_reset => "none",
7268         input_power_up => "low",
7269         input_register_mode => "none",
7270         input_sync_reset => "none",
7271         oe_async_reset => "none",
7272         oe_power_up => "low",
7273         oe_register_mode => "none",
7274         oe_sync_reset => "none",
7275         operation_mode => "output",
7276         output_async_reset => "none",
7277         output_power_up => "low",
7278         output_register_mode => "none",
7279         output_sync_reset => "none")
7280 -- pragma translate_on
7281 PORT MAP (
7282         datain => \vga_control_unit|toggle_counter_sig_5\,
7283         devclrn => ww_devclrn,
7284         devpor => ww_devpor,
7285         devoe => ww_devoe,
7286         oe => VCC,
7287         padio => ww_d_toggle_counter(5));
7288
7289 \d_toggle_counter_out_6_\ : stratix_io
7290 -- pragma translate_off
7291 GENERIC MAP (
7292         ddio_mode => "none",
7293         input_async_reset => "none",
7294         input_power_up => "low",
7295         input_register_mode => "none",
7296         input_sync_reset => "none",
7297         oe_async_reset => "none",
7298         oe_power_up => "low",
7299         oe_register_mode => "none",
7300         oe_sync_reset => "none",
7301         operation_mode => "output",
7302         output_async_reset => "none",
7303         output_power_up => "low",
7304         output_register_mode => "none",
7305         output_sync_reset => "none")
7306 -- pragma translate_on
7307 PORT MAP (
7308         datain => \vga_control_unit|toggle_counter_sig_6\,
7309         devclrn => ww_devclrn,
7310         devpor => ww_devpor,
7311         devoe => ww_devoe,
7312         oe => VCC,
7313         padio => ww_d_toggle_counter(6));
7314
7315 \d_toggle_counter_out_7_\ : stratix_io
7316 -- pragma translate_off
7317 GENERIC MAP (
7318         ddio_mode => "none",
7319         input_async_reset => "none",
7320         input_power_up => "low",
7321         input_register_mode => "none",
7322         input_sync_reset => "none",
7323         oe_async_reset => "none",
7324         oe_power_up => "low",
7325         oe_register_mode => "none",
7326         oe_sync_reset => "none",
7327         operation_mode => "output",
7328         output_async_reset => "none",
7329         output_power_up => "low",
7330         output_register_mode => "none",
7331         output_sync_reset => "none")
7332 -- pragma translate_on
7333 PORT MAP (
7334         datain => \vga_control_unit|toggle_counter_sig_7\,
7335         devclrn => ww_devclrn,
7336         devpor => ww_devpor,
7337         devoe => ww_devoe,
7338         oe => VCC,
7339         padio => ww_d_toggle_counter(7));
7340
7341 \d_toggle_counter_out_8_\ : stratix_io
7342 -- pragma translate_off
7343 GENERIC MAP (
7344         ddio_mode => "none",
7345         input_async_reset => "none",
7346         input_power_up => "low",
7347         input_register_mode => "none",
7348         input_sync_reset => "none",
7349         oe_async_reset => "none",
7350         oe_power_up => "low",
7351         oe_register_mode => "none",
7352         oe_sync_reset => "none",
7353         operation_mode => "output",
7354         output_async_reset => "none",
7355         output_power_up => "low",
7356         output_register_mode => "none",
7357         output_sync_reset => "none")
7358 -- pragma translate_on
7359 PORT MAP (
7360         datain => \vga_control_unit|toggle_counter_sig_8\,
7361         devclrn => ww_devclrn,
7362         devpor => ww_devpor,
7363         devoe => ww_devoe,
7364         oe => VCC,
7365         padio => ww_d_toggle_counter(8));
7366
7367 \d_toggle_counter_out_9_\ : stratix_io
7368 -- pragma translate_off
7369 GENERIC MAP (
7370         ddio_mode => "none",
7371         input_async_reset => "none",
7372         input_power_up => "low",
7373         input_register_mode => "none",
7374         input_sync_reset => "none",
7375         oe_async_reset => "none",
7376         oe_power_up => "low",
7377         oe_register_mode => "none",
7378         oe_sync_reset => "none",
7379         operation_mode => "output",
7380         output_async_reset => "none",
7381         output_power_up => "low",
7382         output_register_mode => "none",
7383         output_sync_reset => "none")
7384 -- pragma translate_on
7385 PORT MAP (
7386         datain => \vga_control_unit|toggle_counter_sig_9\,
7387         devclrn => ww_devclrn,
7388         devpor => ww_devpor,
7389         devoe => ww_devoe,
7390         oe => VCC,
7391         padio => ww_d_toggle_counter(9));
7392
7393 \d_toggle_counter_out_10_\ : stratix_io
7394 -- pragma translate_off
7395 GENERIC MAP (
7396         ddio_mode => "none",
7397         input_async_reset => "none",
7398         input_power_up => "low",
7399         input_register_mode => "none",
7400         input_sync_reset => "none",
7401         oe_async_reset => "none",
7402         oe_power_up => "low",
7403         oe_register_mode => "none",
7404         oe_sync_reset => "none",
7405         operation_mode => "output",
7406         output_async_reset => "none",
7407         output_power_up => "low",
7408         output_register_mode => "none",
7409         output_sync_reset => "none")
7410 -- pragma translate_on
7411 PORT MAP (
7412         datain => \vga_control_unit|toggle_counter_sig_10\,
7413         devclrn => ww_devclrn,
7414         devpor => ww_devpor,
7415         devoe => ww_devoe,
7416         oe => VCC,
7417         padio => ww_d_toggle_counter(10));
7418
7419 \d_toggle_counter_out_11_\ : stratix_io
7420 -- pragma translate_off
7421 GENERIC MAP (
7422         ddio_mode => "none",
7423         input_async_reset => "none",
7424         input_power_up => "low",
7425         input_register_mode => "none",
7426         input_sync_reset => "none",
7427         oe_async_reset => "none",
7428         oe_power_up => "low",
7429         oe_register_mode => "none",
7430         oe_sync_reset => "none",
7431         operation_mode => "output",
7432         output_async_reset => "none",
7433         output_power_up => "low",
7434         output_register_mode => "none",
7435         output_sync_reset => "none")
7436 -- pragma translate_on
7437 PORT MAP (
7438         datain => \vga_control_unit|toggle_counter_sig_11\,
7439         devclrn => ww_devclrn,
7440         devpor => ww_devpor,
7441         devoe => ww_devoe,
7442         oe => VCC,
7443         padio => ww_d_toggle_counter(11));
7444
7445 \d_toggle_counter_out_12_\ : stratix_io
7446 -- pragma translate_off
7447 GENERIC MAP (
7448         ddio_mode => "none",
7449         input_async_reset => "none",
7450         input_power_up => "low",
7451         input_register_mode => "none",
7452         input_sync_reset => "none",
7453         oe_async_reset => "none",
7454         oe_power_up => "low",
7455         oe_register_mode => "none",
7456         oe_sync_reset => "none",
7457         operation_mode => "output",
7458         output_async_reset => "none",
7459         output_power_up => "low",
7460         output_register_mode => "none",
7461         output_sync_reset => "none")
7462 -- pragma translate_on
7463 PORT MAP (
7464         datain => \vga_control_unit|toggle_counter_sig_12\,
7465         devclrn => ww_devclrn,
7466         devpor => ww_devpor,
7467         devoe => ww_devoe,
7468         oe => VCC,
7469         padio => ww_d_toggle_counter(12));
7470
7471 \d_toggle_counter_out_13_\ : stratix_io
7472 -- pragma translate_off
7473 GENERIC MAP (
7474         ddio_mode => "none",
7475         input_async_reset => "none",
7476         input_power_up => "low",
7477         input_register_mode => "none",
7478         input_sync_reset => "none",
7479         oe_async_reset => "none",
7480         oe_power_up => "low",
7481         oe_register_mode => "none",
7482         oe_sync_reset => "none",
7483         operation_mode => "output",
7484         output_async_reset => "none",
7485         output_power_up => "low",
7486         output_register_mode => "none",
7487         output_sync_reset => "none")
7488 -- pragma translate_on
7489 PORT MAP (
7490         datain => \vga_control_unit|toggle_counter_sig_13\,
7491         devclrn => ww_devclrn,
7492         devpor => ww_devpor,
7493         devoe => ww_devoe,
7494         oe => VCC,
7495         padio => ww_d_toggle_counter(13));
7496
7497 \d_toggle_counter_out_14_\ : stratix_io
7498 -- pragma translate_off
7499 GENERIC MAP (
7500         ddio_mode => "none",
7501         input_async_reset => "none",
7502         input_power_up => "low",
7503         input_register_mode => "none",
7504         input_sync_reset => "none",
7505         oe_async_reset => "none",
7506         oe_power_up => "low",
7507         oe_register_mode => "none",
7508         oe_sync_reset => "none",
7509         operation_mode => "output",
7510         output_async_reset => "none",
7511         output_power_up => "low",
7512         output_register_mode => "none",
7513         output_sync_reset => "none")
7514 -- pragma translate_on
7515 PORT MAP (
7516         datain => \vga_control_unit|toggle_counter_sig_14\,
7517         devclrn => ww_devclrn,
7518         devpor => ww_devpor,
7519         devoe => ww_devoe,
7520         oe => VCC,
7521         padio => ww_d_toggle_counter(14));
7522
7523 \d_toggle_counter_out_15_\ : stratix_io
7524 -- pragma translate_off
7525 GENERIC MAP (
7526         ddio_mode => "none",
7527         input_async_reset => "none",
7528         input_power_up => "low",
7529         input_register_mode => "none",
7530         input_sync_reset => "none",
7531         oe_async_reset => "none",
7532         oe_power_up => "low",
7533         oe_register_mode => "none",
7534         oe_sync_reset => "none",
7535         operation_mode => "output",
7536         output_async_reset => "none",
7537         output_power_up => "low",
7538         output_register_mode => "none",
7539         output_sync_reset => "none")
7540 -- pragma translate_on
7541 PORT MAP (
7542         datain => \vga_control_unit|toggle_counter_sig_15\,
7543         devclrn => ww_devclrn,
7544         devpor => ww_devpor,
7545         devoe => ww_devoe,
7546         oe => VCC,
7547         padio => ww_d_toggle_counter(15));
7548
7549 \d_toggle_counter_out_16_\ : stratix_io
7550 -- pragma translate_off
7551 GENERIC MAP (
7552         ddio_mode => "none",
7553         input_async_reset => "none",
7554         input_power_up => "low",
7555         input_register_mode => "none",
7556         input_sync_reset => "none",
7557         oe_async_reset => "none",
7558         oe_power_up => "low",
7559         oe_register_mode => "none",
7560         oe_sync_reset => "none",
7561         operation_mode => "output",
7562         output_async_reset => "none",
7563         output_power_up => "low",
7564         output_register_mode => "none",
7565         output_sync_reset => "none")
7566 -- pragma translate_on
7567 PORT MAP (
7568         datain => \vga_control_unit|toggle_counter_sig_16\,
7569         devclrn => ww_devclrn,
7570         devpor => ww_devpor,
7571         devoe => ww_devoe,
7572         oe => VCC,
7573         padio => ww_d_toggle_counter(16));
7574
7575 \d_toggle_counter_out_17_\ : stratix_io
7576 -- pragma translate_off
7577 GENERIC MAP (
7578         ddio_mode => "none",
7579         input_async_reset => "none",
7580         input_power_up => "low",
7581         input_register_mode => "none",
7582         input_sync_reset => "none",
7583         oe_async_reset => "none",
7584         oe_power_up => "low",
7585         oe_register_mode => "none",
7586         oe_sync_reset => "none",
7587         operation_mode => "output",
7588         output_async_reset => "none",
7589         output_power_up => "low",
7590         output_register_mode => "none",
7591         output_sync_reset => "none")
7592 -- pragma translate_on
7593 PORT MAP (
7594         datain => \vga_control_unit|toggle_counter_sig_17\,
7595         devclrn => ww_devclrn,
7596         devpor => ww_devpor,
7597         devoe => ww_devoe,
7598         oe => VCC,
7599         padio => ww_d_toggle_counter(17));
7600
7601 \d_toggle_counter_out_18_\ : stratix_io
7602 -- pragma translate_off
7603 GENERIC MAP (
7604         ddio_mode => "none",
7605         input_async_reset => "none",
7606         input_power_up => "low",
7607         input_register_mode => "none",
7608         input_sync_reset => "none",
7609         oe_async_reset => "none",
7610         oe_power_up => "low",
7611         oe_register_mode => "none",
7612         oe_sync_reset => "none",
7613         operation_mode => "output",
7614         output_async_reset => "none",
7615         output_power_up => "low",
7616         output_register_mode => "none",
7617         output_sync_reset => "none")
7618 -- pragma translate_on
7619 PORT MAP (
7620         datain => \vga_control_unit|toggle_counter_sig_18\,
7621         devclrn => ww_devclrn,
7622         devpor => ww_devpor,
7623         devoe => ww_devoe,
7624         oe => VCC,
7625         padio => ww_d_toggle_counter(18));
7626
7627 \d_toggle_counter_out_19_\ : stratix_io
7628 -- pragma translate_off
7629 GENERIC MAP (
7630         ddio_mode => "none",
7631         input_async_reset => "none",
7632         input_power_up => "low",
7633         input_register_mode => "none",
7634         input_sync_reset => "none",
7635         oe_async_reset => "none",
7636         oe_power_up => "low",
7637         oe_register_mode => "none",
7638         oe_sync_reset => "none",
7639         operation_mode => "output",
7640         output_async_reset => "none",
7641         output_power_up => "low",
7642         output_register_mode => "none",
7643         output_sync_reset => "none")
7644 -- pragma translate_on
7645 PORT MAP (
7646         datain => \vga_control_unit|toggle_counter_sig_19\,
7647         devclrn => ww_devclrn,
7648         devpor => ww_devpor,
7649         devoe => ww_devoe,
7650         oe => VCC,
7651         padio => ww_d_toggle_counter(19));
7652
7653 \d_toggle_counter_out_20_\ : stratix_io
7654 -- pragma translate_off
7655 GENERIC MAP (
7656         ddio_mode => "none",
7657         input_async_reset => "none",
7658         input_power_up => "low",
7659         input_register_mode => "none",
7660         input_sync_reset => "none",
7661         oe_async_reset => "none",
7662         oe_power_up => "low",
7663         oe_register_mode => "none",
7664         oe_sync_reset => "none",
7665         operation_mode => "output",
7666         output_async_reset => "none",
7667         output_power_up => "low",
7668         output_register_mode => "none",
7669         output_sync_reset => "none")
7670 -- pragma translate_on
7671 PORT MAP (
7672         datain => \vga_control_unit|toggle_counter_sig_20\,
7673         devclrn => ww_devclrn,
7674         devpor => ww_devpor,
7675         devoe => ww_devoe,
7676         oe => VCC,
7677         padio => ww_d_toggle_counter(20));
7678
7679 \d_toggle_counter_out_21_\ : stratix_io
7680 -- pragma translate_off
7681 GENERIC MAP (
7682         ddio_mode => "none",
7683         input_async_reset => "none",
7684         input_power_up => "low",
7685         input_register_mode => "none",
7686         input_sync_reset => "none",
7687         oe_async_reset => "none",
7688         oe_power_up => "low",
7689         oe_register_mode => "none",
7690         oe_sync_reset => "none",
7691         operation_mode => "output",
7692         output_async_reset => "none",
7693         output_power_up => "low",
7694         output_register_mode => "none",
7695         output_sync_reset => "none")
7696 -- pragma translate_on
7697 PORT MAP (
7698         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7699         devclrn => ww_devclrn,
7700         devpor => ww_devpor,
7701         devoe => ww_devoe,
7702         oe => VCC,
7703         padio => ww_d_toggle_counter(21));
7704
7705 \d_toggle_counter_out_22_\ : stratix_io
7706 -- pragma translate_off
7707 GENERIC MAP (
7708         ddio_mode => "none",
7709         input_async_reset => "none",
7710         input_power_up => "low",
7711         input_register_mode => "none",
7712         input_sync_reset => "none",
7713         oe_async_reset => "none",
7714         oe_power_up => "low",
7715         oe_register_mode => "none",
7716         oe_sync_reset => "none",
7717         operation_mode => "output",
7718         output_async_reset => "none",
7719         output_power_up => "low",
7720         output_register_mode => "none",
7721         output_sync_reset => "none")
7722 -- pragma translate_on
7723 PORT MAP (
7724         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7725         devclrn => ww_devclrn,
7726         devpor => ww_devpor,
7727         devoe => ww_devoe,
7728         oe => VCC,
7729         padio => ww_d_toggle_counter(22));
7730
7731 \d_toggle_counter_out_23_\ : stratix_io
7732 -- pragma translate_off
7733 GENERIC MAP (
7734         ddio_mode => "none",
7735         input_async_reset => "none",
7736         input_power_up => "low",
7737         input_register_mode => "none",
7738         input_sync_reset => "none",
7739         oe_async_reset => "none",
7740         oe_power_up => "low",
7741         oe_register_mode => "none",
7742         oe_sync_reset => "none",
7743         operation_mode => "output",
7744         output_async_reset => "none",
7745         output_power_up => "low",
7746         output_register_mode => "none",
7747         output_sync_reset => "none")
7748 -- pragma translate_on
7749 PORT MAP (
7750         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7751         devclrn => ww_devclrn,
7752         devpor => ww_devpor,
7753         devoe => ww_devoe,
7754         oe => VCC,
7755         padio => ww_d_toggle_counter(23));
7756
7757 \d_toggle_counter_out_24_\ : stratix_io
7758 -- pragma translate_off
7759 GENERIC MAP (
7760         ddio_mode => "none",
7761         input_async_reset => "none",
7762         input_power_up => "low",
7763         input_register_mode => "none",
7764         input_sync_reset => "none",
7765         oe_async_reset => "none",
7766         oe_power_up => "low",
7767         oe_register_mode => "none",
7768         oe_sync_reset => "none",
7769         operation_mode => "output",
7770         output_async_reset => "none",
7771         output_power_up => "low",
7772         output_register_mode => "none",
7773         output_sync_reset => "none")
7774 -- pragma translate_on
7775 PORT MAP (
7776         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7777         devclrn => ww_devclrn,
7778         devpor => ww_devpor,
7779         devoe => ww_devoe,
7780         oe => VCC,
7781         padio => ww_d_toggle_counter(24));
7782 END structure;
7783
7784