bsp2/Designflow/ppr/sim/db/vga.hif

   1 Version 9.0 Build 132 02/25/2009 SJ Full Version
   2 45
   3 3235
   4 OFF
   5 OFF
   6 OFF
   7 ON
   8 ON
   9 ON
  10 FV_OFF
  11 Level2
  12 0
  13 0
  14 VRSM_ON
  15 VHSM_ON
  16 synplcty.lmf
  17 -- Start Library Paths --
  18 -- End Library Paths --
  19 -- Start VHDL Libraries --
  20 -- End VHDL Libraries --
  21 # entity
  22 vga
  23 # storage
  24 db|vga.(0).cnf
  25 db|vga.(0).cnf
  26 # case_sensitive
  27 # source_file
  28 ..|..|syn|rev_1|vga.vqm
  29 a69bdf2838bc2ddfa265318d6caf919c
  30 28
  31 # hierarchies {
  32 |
  33 }
  34 # lmf
  35 |opt|quartus|quartus|lmf|synplcty.lmf
  36 3057712873b497a38b70a3917f30cc38
  37 # macro_sequence
  38
  39 # end
  40 # entity
  41 vga_driver
  42 # storage
  43 db|vga.(1).cnf
  44 db|vga.(1).cnf
  45 # case_sensitive
  46 # source_file
  47 ..|..|syn|rev_1|vga.vqm
  48 a69bdf2838bc2ddfa265318d6caf919c
  49 28
  50 # hierarchies {
  51 vga_driver:vga_driver_unit
  52 }
  53 # lmf
  54 |opt|quartus|quartus|lmf|synplcty.lmf
  55 3057712873b497a38b70a3917f30cc38
  56 # macro_sequence
  57
  58 # end
  59 # entity
  60 vga_control
  61 # storage
  62 db|vga.(2).cnf
  63 db|vga.(2).cnf
  64 # case_sensitive
  65 # source_file
  66 ..|..|syn|rev_1|vga.vqm
  67 a69bdf2838bc2ddfa265318d6caf919c
  68 28
  69 # hierarchies {
  70 vga_control:vga_control_unit
  71 }
  72 # lmf
  73 |opt|quartus|quartus|lmf|synplcty.lmf
  74 3057712873b497a38b70a3917f30cc38
  75 # macro_sequence
  76
  77 # end
  78 # complete
  79 \r