2 clk_pin => clk_pin_in.PADIO
3 reset_pin => reset_pin_in.PADIO
4 r0_pin <= r0_pin_out.PADIO
5 r1_pin <= r1_pin_out.PADIO
6 r2_pin <= r2_pin_out.PADIO
7 g0_pin <= g0_pin_out.PADIO
8 g1_pin <= g1_pin_out.PADIO
9 g2_pin <= g2_pin_out.PADIO
10 b0_pin <= b0_pin_out.PADIO
11 b1_pin <= b1_pin_out.PADIO
12 hsync_pin <= hsync_pin_out.PADIO
13 vsync_pin <= vsync_pin_out.PADIO
14 seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
15 seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
16 seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
17 seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
18 seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
19 seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
20 seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
21 seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
22 seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
23 seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
24 seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
25 seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
26 seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
27 seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
28 d_hsync <= d_hsync_out.PADIO
29 d_vsync <= d_vsync_out.PADIO
30 d_column_counter[0] <= d_column_counter_out_0_.PADIO
31 d_column_counter[1] <= d_column_counter_out_1_.PADIO
32 d_column_counter[2] <= d_column_counter_out_2_.PADIO
33 d_column_counter[3] <= d_column_counter_out_3_.PADIO
34 d_column_counter[4] <= d_column_counter_out_4_.PADIO
35 d_column_counter[5] <= d_column_counter_out_5_.PADIO
36 d_column_counter[6] <= d_column_counter_out_6_.PADIO
37 d_column_counter[7] <= d_column_counter_out_7_.PADIO
38 d_column_counter[8] <= d_column_counter_out_8_.PADIO
39 d_column_counter[9] <= d_column_counter_out_9_.PADIO
40 d_line_counter[0] <= d_line_counter_out_0_.PADIO
41 d_line_counter[1] <= d_line_counter_out_1_.PADIO
42 d_line_counter[2] <= d_line_counter_out_2_.PADIO
43 d_line_counter[3] <= d_line_counter_out_3_.PADIO
44 d_line_counter[4] <= d_line_counter_out_4_.PADIO
45 d_line_counter[5] <= d_line_counter_out_5_.PADIO
46 d_line_counter[6] <= d_line_counter_out_6_.PADIO
47 d_line_counter[7] <= d_line_counter_out_7_.PADIO
48 d_line_counter[8] <= d_line_counter_out_8_.PADIO
49 d_set_column_counter <= d_set_column_counter_out.PADIO
50 d_set_line_counter <= d_set_line_counter_out.PADIO
51 d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
52 d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
53 d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
54 d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
55 d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
56 d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
57 d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
58 d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
59 d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
60 d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
61 d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
62 d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
63 d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
64 d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
65 d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
66 d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
67 d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
68 d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
69 d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
70 d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
71 d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
72 d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
73 d_h_enable <= d_h_enable_out.PADIO
74 d_v_enable <= d_v_enable_out.PADIO
78 d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
79 d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
80 d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
81 d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
82 d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
83 d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
84 d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
85 d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
86 d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
87 d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
88 d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
89 d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
90 d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
91 d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
92 d_state_clk <= d_state_clk_out.PADIO
93 d_toggle <= d_toggle_out.PADIO
94 d_toggle_counter[0] <= d_toggle_counter_out_0_.PADIO
95 d_toggle_counter[1] <= d_toggle_counter_out_1_.PADIO
96 d_toggle_counter[2] <= d_toggle_counter_out_2_.PADIO
97 d_toggle_counter[3] <= d_toggle_counter_out_3_.PADIO
98 d_toggle_counter[4] <= d_toggle_counter_out_4_.PADIO
99 d_toggle_counter[5] <= d_toggle_counter_out_5_.PADIO
100 d_toggle_counter[6] <= d_toggle_counter_out_6_.PADIO
101 d_toggle_counter[7] <= d_toggle_counter_out_7_.PADIO
102 d_toggle_counter[8] <= d_toggle_counter_out_8_.PADIO
103 d_toggle_counter[9] <= d_toggle_counter_out_9_.PADIO
104 d_toggle_counter[10] <= d_toggle_counter_out_10_.PADIO
105 d_toggle_counter[11] <= d_toggle_counter_out_11_.PADIO
106 d_toggle_counter[12] <= d_toggle_counter_out_12_.PADIO
107 d_toggle_counter[13] <= d_toggle_counter_out_13_.PADIO
108 d_toggle_counter[14] <= d_toggle_counter_out_14_.PADIO
109 d_toggle_counter[15] <= d_toggle_counter_out_15_.PADIO
110 d_toggle_counter[16] <= d_toggle_counter_out_16_.PADIO
111 d_toggle_counter[17] <= d_toggle_counter_out_17_.PADIO
112 d_toggle_counter[18] <= d_toggle_counter_out_18_.PADIO
113 d_toggle_counter[19] <= d_toggle_counter_out_19_.PADIO
114 d_toggle_counter[20] <= d_toggle_counter_out_20_.PADIO
115 d_toggle_counter[21] <= d_toggle_counter_out_21_.PADIO
116 d_toggle_counter[22] <= d_toggle_counter_out_22_.PADIO
117 d_toggle_counter[23] <= d_toggle_counter_out_23_.PADIO
118 d_toggle_counter[24] <= d_toggle_counter_out_24_.PADIO
121 |vga|vga_driver:vga_driver_unit
122 line_counter_sig_0 <= line_counter_sig_0_.REGOUT
123 line_counter_sig_1 <= line_counter_sig_1_.REGOUT
124 line_counter_sig_2 <= line_counter_sig_2_.REGOUT
125 line_counter_sig_3 <= line_counter_sig_3_.REGOUT
126 line_counter_sig_4 <= line_counter_sig_4_.REGOUT
127 line_counter_sig_5 <= line_counter_sig_5_.REGOUT
128 line_counter_sig_6 <= line_counter_sig_6_.REGOUT
129 line_counter_sig_7 <= line_counter_sig_7_.REGOUT
130 line_counter_sig_8 <= line_counter_sig_8_.REGOUT
131 dly_counter_1 => vsync_state_6_.DATAC
132 dly_counter_1 => h_sync_Z.DATAC
133 dly_counter_1 => v_sync_Z.DATAC
134 dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
135 dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
136 dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
137 dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
138 dly_counter_0 => vsync_state_6_.DATAB
139 dly_counter_0 => h_sync_Z.DATAB
140 dly_counter_0 => v_sync_Z.DATAB
141 dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
142 dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
143 dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
144 dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
145 vsync_state_2 <= vsync_state_2_.REGOUT
146 vsync_state_5 <= vsync_state_5_.REGOUT
147 vsync_state_3 <= vsync_state_3_.REGOUT
148 vsync_state_6 <= vsync_state_6_.REGOUT
149 vsync_state_4 <= vsync_state_4_.REGOUT
150 vsync_state_1 <= vsync_state_1_.REGOUT
151 vsync_state_0 <= vsync_state_0_.REGOUT
152 hsync_state_2 <= hsync_state_2_.REGOUT
153 hsync_state_4 <= hsync_state_4_.REGOUT
154 hsync_state_0 <= hsync_state_0_.REGOUT
155 hsync_state_5 <= hsync_state_5_.REGOUT
156 hsync_state_1 <= hsync_state_1_.REGOUT
157 hsync_state_3 <= hsync_state_3_.REGOUT
158 hsync_state_6 <= hsync_state_6_.REGOUT
159 column_counter_sig_0 <= column_counter_sig_0_.REGOUT
160 column_counter_sig_1 <= column_counter_sig_1_.REGOUT
161 column_counter_sig_2 <= column_counter_sig_2_.REGOUT
162 column_counter_sig_3 <= column_counter_sig_3_.REGOUT
163 column_counter_sig_4 <= column_counter_sig_4_.REGOUT
164 column_counter_sig_5 <= column_counter_sig_5_.REGOUT
165 column_counter_sig_6 <= column_counter_sig_6_.REGOUT
166 column_counter_sig_7 <= column_counter_sig_7_.REGOUT
167 column_counter_sig_8 <= column_counter_sig_8_.REGOUT
168 column_counter_sig_9 <= column_counter_sig_9_.REGOUT
169 vsync_counter_9 <= vsync_counter_9_.REGOUT
170 vsync_counter_8 <= vsync_counter_8_.REGOUT
171 vsync_counter_7 <= vsync_counter_7_.REGOUT
172 vsync_counter_6 <= vsync_counter_6_.REGOUT
173 vsync_counter_5 <= vsync_counter_5_.REGOUT
174 vsync_counter_4 <= vsync_counter_4_.REGOUT
175 vsync_counter_3 <= vsync_counter_3_.REGOUT
176 vsync_counter_2 <= vsync_counter_2_.REGOUT
177 vsync_counter_1 <= vsync_counter_1_.REGOUT
178 vsync_counter_0 <= vsync_counter_0_.REGOUT
179 hsync_counter_9 <= hsync_counter_9_.REGOUT
180 hsync_counter_8 <= hsync_counter_8_.REGOUT
181 hsync_counter_7 <= hsync_counter_7_.REGOUT
182 hsync_counter_6 <= hsync_counter_6_.REGOUT
183 hsync_counter_5 <= hsync_counter_5_.REGOUT
184 hsync_counter_4 <= hsync_counter_4_.REGOUT
185 hsync_counter_3 <= hsync_counter_3_.REGOUT
186 hsync_counter_2 <= hsync_counter_2_.REGOUT
187 hsync_counter_1 <= hsync_counter_1_.REGOUT
188 hsync_counter_0 <= hsync_counter_0_.REGOUT
189 d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
190 v_sync <= v_sync_Z.REGOUT
191 h_sync <= h_sync_Z.REGOUT
192 h_enable_sig <= h_enable_sig_Z.REGOUT
193 v_enable_sig <= v_enable_sig_Z.REGOUT
194 reset_pin_c => vsync_state_6_.DATAA
195 reset_pin_c => h_sync_Z.DATAA
196 reset_pin_c => v_sync_Z.DATAA
197 reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
198 reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
199 reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
200 reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
201 un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
202 d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
203 clk_pin_c => hsync_counter_0_.CLK
204 clk_pin_c => hsync_counter_1_.CLK
205 clk_pin_c => hsync_counter_2_.CLK
206 clk_pin_c => hsync_counter_3_.CLK
207 clk_pin_c => hsync_counter_4_.CLK
208 clk_pin_c => hsync_counter_5_.CLK
209 clk_pin_c => hsync_counter_6_.CLK
210 clk_pin_c => hsync_counter_7_.CLK
211 clk_pin_c => hsync_counter_8_.CLK
212 clk_pin_c => hsync_counter_9_.CLK
213 clk_pin_c => vsync_counter_0_.CLK
214 clk_pin_c => vsync_counter_1_.CLK
215 clk_pin_c => vsync_counter_2_.CLK
216 clk_pin_c => vsync_counter_3_.CLK
217 clk_pin_c => vsync_counter_4_.CLK
218 clk_pin_c => vsync_counter_5_.CLK
219 clk_pin_c => vsync_counter_6_.CLK
220 clk_pin_c => vsync_counter_7_.CLK
221 clk_pin_c => vsync_counter_8_.CLK
222 clk_pin_c => vsync_counter_9_.CLK
223 clk_pin_c => column_counter_sig_9_.CLK
224 clk_pin_c => column_counter_sig_8_.CLK
225 clk_pin_c => column_counter_sig_7_.CLK
226 clk_pin_c => column_counter_sig_6_.CLK
227 clk_pin_c => column_counter_sig_5_.CLK
228 clk_pin_c => column_counter_sig_4_.CLK
229 clk_pin_c => column_counter_sig_3_.CLK
230 clk_pin_c => column_counter_sig_2_.CLK
231 clk_pin_c => column_counter_sig_1_.CLK
232 clk_pin_c => column_counter_sig_0_.CLK
233 clk_pin_c => hsync_state_6_.CLK
234 clk_pin_c => vsync_state_0_.CLK
235 clk_pin_c => vsync_state_1_.CLK
236 clk_pin_c => vsync_state_6_.CLK
237 clk_pin_c => line_counter_sig_8_.CLK
238 clk_pin_c => line_counter_sig_7_.CLK
239 clk_pin_c => line_counter_sig_6_.CLK
240 clk_pin_c => line_counter_sig_5_.CLK
241 clk_pin_c => line_counter_sig_4_.CLK
242 clk_pin_c => line_counter_sig_3_.CLK
243 clk_pin_c => line_counter_sig_2_.CLK
244 clk_pin_c => line_counter_sig_1_.CLK
245 clk_pin_c => line_counter_sig_0_.CLK
246 clk_pin_c => v_enable_sig_Z.CLK
247 clk_pin_c => h_enable_sig_Z.CLK
248 clk_pin_c => h_sync_Z.CLK
249 clk_pin_c => v_sync_Z.CLK
250 clk_pin_c => vsync_state_5_.CLK
251 clk_pin_c => vsync_state_4_.CLK
252 clk_pin_c => vsync_state_3_.CLK
253 clk_pin_c => vsync_state_2_.CLK
254 clk_pin_c => hsync_state_5_.CLK
255 clk_pin_c => hsync_state_4_.CLK
256 clk_pin_c => hsync_state_3_.CLK
257 clk_pin_c => hsync_state_2_.CLK
258 clk_pin_c => hsync_state_1_.CLK
259 clk_pin_c => hsync_state_0_.CLK
262 |vga|vga_control:vga_control_unit
263 line_counter_sig_0 => DRAW_SQUARE_next_un17_v_enablelto3.DATAC
264 line_counter_sig_2 => DRAW_SQUARE_next_un17_v_enablelto3.DATAB
265 line_counter_sig_2 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAB
266 line_counter_sig_1 => DRAW_SQUARE_next_un17_v_enablelto3.DATAA
267 line_counter_sig_3 => DRAW_SQUARE_next_un13_v_enablelto6.DATAC
268 line_counter_sig_3 => DRAW_SQUARE_next_un17_v_enablelto3.DATAD
269 line_counter_sig_6 => b_next_0_sqmuxa_7_4_a_cZ.DATAC
270 line_counter_sig_6 => DRAW_SQUARE_next_un13_v_enablelto6.DATAB
271 line_counter_sig_5 => b_next_0_sqmuxa_7_4_a_cZ.DATAB
272 line_counter_sig_5 => DRAW_SQUARE_next_un13_v_enablelto6.DATAA
273 line_counter_sig_4 => b_next_0_sqmuxa_7_4_a_cZ.DATAA
274 line_counter_sig_4 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAA
275 line_counter_sig_7 => b_next_0_sqmuxa_7_4_cZ.DATAB
276 line_counter_sig_8 => b_next_0_sqmuxa_7_4_cZ.DATAA
277 line_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAD
278 column_counter_sig_0 => DRAW_SQUARE_next_un5_v_enablelt2.DATAC
279 column_counter_sig_1 => DRAW_SQUARE_next_un5_v_enablelt2.DATAA
280 column_counter_sig_2 => DRAW_SQUARE_next_un9_v_enablelto4.DATAC
281 column_counter_sig_2 => DRAW_SQUARE_next_un5_v_enablelt2.DATAB
282 column_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAA
283 column_counter_sig_3 => DRAW_SQUARE_next_un5_v_enablelto5.DATAC
284 column_counter_sig_3 => DRAW_SQUARE_next_un9_v_enablelto4.DATAA
285 column_counter_sig_5 => DRAW_SQUARE_next_un5_v_enablelto5.DATAB
286 column_counter_sig_5 => DRAW_SQUARE_next_un9_v_enablelto6.DATAA
287 column_counter_sig_4 => DRAW_SQUARE_next_un5_v_enablelto5.DATAA
288 column_counter_sig_4 => DRAW_SQUARE_next_un9_v_enablelto4.DATAB
289 column_counter_sig_9 => b_next_0_sqmuxa_7_3_cZ.DATAB
290 column_counter_sig_9 => b_next_0_sqmuxa_7_2_cZ.DATAC
291 column_counter_sig_7 => b_next_0_sqmuxa_7_5_cZ.DATAB
292 column_counter_sig_7 => b_next_0_sqmuxa_7_3_cZ.DATAA
293 column_counter_sig_6 => b_next_0_sqmuxa_7_5_cZ.DATAA
294 column_counter_sig_6 => DRAW_SQUARE_next_un9_v_enablelto6.DATAB
295 toggle_counter_sig_0 <= toggle_counter_sig_0_.REGOUT
296 toggle_counter_sig_1 <= toggle_counter_sig_1_.REGOUT
297 toggle_counter_sig_2 <= toggle_counter_sig_2_.REGOUT
298 toggle_counter_sig_3 <= toggle_counter_sig_3_.REGOUT
299 toggle_counter_sig_4 <= toggle_counter_sig_4_.REGOUT
300 toggle_counter_sig_5 <= toggle_counter_sig_5_.REGOUT
301 toggle_counter_sig_6 <= toggle_counter_sig_6_.REGOUT
302 toggle_counter_sig_7 <= toggle_counter_sig_7_.REGOUT
303 toggle_counter_sig_8 <= toggle_counter_sig_8_.REGOUT
304 toggle_counter_sig_9 <= toggle_counter_sig_9_.REGOUT
305 toggle_counter_sig_10 <= toggle_counter_sig_10_.REGOUT
306 toggle_counter_sig_11 <= toggle_counter_sig_11_.REGOUT
307 toggle_counter_sig_12 <= toggle_counter_sig_12_.REGOUT
308 toggle_counter_sig_13 <= toggle_counter_sig_13_.REGOUT
309 toggle_counter_sig_14 <= toggle_counter_sig_14_.REGOUT
310 toggle_counter_sig_15 <= toggle_counter_sig_15_.REGOUT
311 toggle_counter_sig_16 <= toggle_counter_sig_16_.REGOUT
312 toggle_counter_sig_17 <= toggle_counter_sig_17_.REGOUT
313 toggle_counter_sig_18 <= toggle_counter_sig_18_.REGOUT
314 toggle_counter_sig_19 <= toggle_counter_sig_19_.REGOUT
315 toggle_counter_sig_20 <= toggle_counter_sig_20_.REGOUT
316 toggle_counter_sig_21 <= toggle_counter_sig_21_.REGOUT
317 toggle_counter_sig_22 <= toggle_counter_sig_22_.REGOUT
318 toggle_counter_sig_23 <= toggle_counter_sig_23_.REGOUT
319 toggle_counter_sig_24 <= toggle_counter_sig_24_.REGOUT
320 h_enable_sig => b_next_0_sqmuxa_7_2_cZ.DATAB
323 v_enable_sig => r_Z.DATAB
324 v_enable_sig => b_Z.DATAB
326 toggle_sig <= toggle_sig_Z.REGOUT
327 un6_dly_counter_0_x => toggle_counter_sig_24_.ACLR
328 un6_dly_counter_0_x => toggle_counter_sig_23_.ACLR
329 un6_dly_counter_0_x => toggle_counter_sig_22_.ACLR
330 un6_dly_counter_0_x => toggle_counter_sig_21_.ACLR
331 un6_dly_counter_0_x => toggle_counter_sig_20_.ACLR
332 un6_dly_counter_0_x => toggle_counter_sig_19_.ACLR
333 un6_dly_counter_0_x => toggle_counter_sig_18_.ACLR
334 un6_dly_counter_0_x => toggle_counter_sig_17_.ACLR
335 un6_dly_counter_0_x => toggle_counter_sig_16_.ACLR
336 un6_dly_counter_0_x => toggle_counter_sig_15_.ACLR
337 un6_dly_counter_0_x => toggle_counter_sig_14_.ACLR
338 un6_dly_counter_0_x => toggle_counter_sig_13_.ACLR
339 un6_dly_counter_0_x => toggle_counter_sig_12_.ACLR
340 un6_dly_counter_0_x => toggle_counter_sig_11_.ACLR
341 un6_dly_counter_0_x => toggle_counter_sig_10_.ACLR
342 un6_dly_counter_0_x => toggle_counter_sig_9_.ACLR
343 un6_dly_counter_0_x => toggle_counter_sig_8_.ACLR
344 un6_dly_counter_0_x => toggle_counter_sig_7_.ACLR
345 un6_dly_counter_0_x => toggle_counter_sig_6_.ACLR
346 un6_dly_counter_0_x => toggle_counter_sig_5_.ACLR
347 un6_dly_counter_0_x => toggle_counter_sig_4_.ACLR
348 un6_dly_counter_0_x => toggle_counter_sig_3_.ACLR
349 un6_dly_counter_0_x => toggle_counter_sig_2_.ACLR
350 un6_dly_counter_0_x => toggle_counter_sig_1_.ACLR
351 un6_dly_counter_0_x => toggle_counter_sig_0_.ACLR
352 un6_dly_counter_0_x => toggle_sig_Z.ACLR
353 un6_dly_counter_0_x => r_Z.ACLR
354 un6_dly_counter_0_x => b_Z.ACLR
355 un6_dly_counter_0_x => g_Z.ACLR
356 clk_pin_c => toggle_counter_sig_24_.CLK
357 clk_pin_c => toggle_counter_sig_23_.CLK
358 clk_pin_c => toggle_counter_sig_22_.CLK
359 clk_pin_c => toggle_counter_sig_21_.CLK
360 clk_pin_c => toggle_counter_sig_20_.CLK
361 clk_pin_c => toggle_counter_sig_19_.CLK
362 clk_pin_c => toggle_counter_sig_18_.CLK
363 clk_pin_c => toggle_counter_sig_17_.CLK
364 clk_pin_c => toggle_counter_sig_16_.CLK
365 clk_pin_c => toggle_counter_sig_15_.CLK
366 clk_pin_c => toggle_counter_sig_14_.CLK
367 clk_pin_c => toggle_counter_sig_13_.CLK
368 clk_pin_c => toggle_counter_sig_12_.CLK
369 clk_pin_c => toggle_counter_sig_11_.CLK
370 clk_pin_c => toggle_counter_sig_10_.CLK
371 clk_pin_c => toggle_counter_sig_9_.CLK
372 clk_pin_c => toggle_counter_sig_8_.CLK
373 clk_pin_c => toggle_counter_sig_7_.CLK
374 clk_pin_c => toggle_counter_sig_6_.CLK
375 clk_pin_c => toggle_counter_sig_5_.CLK
376 clk_pin_c => toggle_counter_sig_4_.CLK
377 clk_pin_c => toggle_counter_sig_3_.CLK
378 clk_pin_c => toggle_counter_sig_2_.CLK
379 clk_pin_c => toggle_counter_sig_1_.CLK
380 clk_pin_c => toggle_counter_sig_0_.CLK
381 clk_pin_c => toggle_sig_Z.CLK
projects / dide_16.git / blob