1 Analysis & Synthesis report for vga_pll
2 Wed Oct 28 14:54:40 2009
3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
10 2. Analysis & Synthesis Summary
11 3. Analysis & Synthesis Settings
12 4. Analysis & Synthesis Source Files Read
13 5. Analysis & Synthesis Resource Usage Summary
14 6. Analysis & Synthesis Resource Utilization by Entity
15 7. Registers Removed During Synthesis
16 8. General Register Statistics
17 9. Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component
18 10. altpll Parameter Settings by Entity Instance
19 11. Analysis & Synthesis Messages
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42 +------------------------------------------------------------------------+
43 ; Analysis & Synthesis Summary ;
44 +-----------------------------+------------------------------------------+
45 ; Analysis & Synthesis Status ; Successful - Wed Oct 28 14:54:40 2009 ;
46 ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
47 ; Revision Name ; vga_pll ;
48 ; Top-level Entity Name ; vga_pll ;
50 ; Total logic elements ; 175 ;
52 ; Total virtual pins ; 0 ;
53 ; Total memory bits ; 0 ;
54 ; DSP block 9-bit elements ; 0 ;
57 +-----------------------------+------------------------------------------+
60 +----------------------------------------------------------------------------------------------------------+
61 ; Analysis & Synthesis Settings ;
62 +----------------------------------------------------------------+--------------------+--------------------+
63 ; Option ; Setting ; Default Value ;
64 +----------------------------------------------------------------+--------------------+--------------------+
65 ; Device ; EP1S25F672C6 ; ;
66 ; Top-level entity name ; vga_pll ; vga_pll ;
67 ; Family name ; Stratix ; Stratix ;
68 ; Type of Retiming Performed During Resynthesis ; Full ; ;
69 ; Resynthesis Optimization Effort ; Normal ; ;
70 ; Physical Synthesis Level for Resynthesis ; Normal ; ;
71 ; Use Generated Physical Constraints File ; On ; ;
72 ; Use smart compilation ; Off ; Off ;
73 ; Restructure Multiplexers ; Auto ; Auto ;
74 ; Create Debugging Nodes for IP Cores ; Off ; Off ;
75 ; Preserve fewer node names ; On ; On ;
76 ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
77 ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
78 ; VHDL Version ; VHDL93 ; VHDL93 ;
79 ; State Machine Processing ; Auto ; Auto ;
80 ; Safe State Machine ; Off ; Off ;
81 ; Extract Verilog State Machines ; On ; On ;
82 ; Extract VHDL State Machines ; On ; On ;
83 ; Ignore Verilog initial constructs ; Off ; Off ;
84 ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
85 ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
86 ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
87 ; Parallel Synthesis ; Off ; Off ;
88 ; DSP Block Balancing ; Auto ; Auto ;
89 ; NOT Gate Push-Back ; On ; On ;
90 ; Power-Up Don't Care ; On ; On ;
91 ; Remove Redundant Logic Cells ; Off ; Off ;
92 ; Remove Duplicate Registers ; On ; On ;
93 ; Ignore CARRY Buffers ; Off ; Off ;
94 ; Ignore CASCADE Buffers ; Off ; Off ;
95 ; Ignore GLOBAL Buffers ; Off ; Off ;
96 ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
97 ; Ignore LCELL Buffers ; Off ; Off ;
98 ; Ignore SOFT Buffers ; On ; On ;
99 ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
100 ; Optimization Technique ; Balanced ; Balanced ;
101 ; Carry Chain Length ; 70 ; 70 ;
102 ; Auto Carry Chains ; On ; On ;
103 ; Auto Open-Drain Pins ; On ; On ;
104 ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
105 ; Auto ROM Replacement ; On ; On ;
106 ; Auto RAM Replacement ; On ; On ;
107 ; Auto DSP Block Replacement ; On ; On ;
108 ; Auto Shift Register Replacement ; Auto ; Auto ;
109 ; Auto Clock Enable Replacement ; On ; On ;
110 ; Strict RAM Replacement ; Off ; Off ;
111 ; Allow Synchronous Control Signals ; On ; On ;
112 ; Force Use of Synchronous Clear Signals ; Off ; Off ;
113 ; Auto RAM Block Balancing ; On ; On ;
114 ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
115 ; Auto Resource Sharing ; Off ; Off ;
116 ; Allow Any RAM Size For Recognition ; Off ; Off ;
117 ; Allow Any ROM Size For Recognition ; Off ; Off ;
118 ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
119 ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
120 ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
121 ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
122 ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
123 ; Synchronization Register Chain Length ; 2 ; 2 ;
124 ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
125 ; HDL message level ; Level2 ; Level2 ;
126 ; Suppress Register Optimization Related Messages ; Off ; Off ;
127 ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
128 ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
129 ; Clock MUX Protection ; On ; On ;
130 ; Block Design Naming ; Auto ; Auto ;
131 ; Synthesis Effort ; Auto ; Auto ;
132 ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
133 ; Analysis & Synthesis Message Level ; Medium ; Medium ;
134 +----------------------------------------------------------------+--------------------+--------------------+
137 +----------------------------------------------------------------------------------------------------------------------------------------------------------+
138 ; Analysis & Synthesis Source Files Read ;
139 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
140 ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
141 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
142 ; ../../src/vga_pll.bdf ; yes ; User Block Diagram/Schematic File ; /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf ;
143 ; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm ;
144 ; ../../src/vpll.vhd ; yes ; User Wizard-Generated File ; /homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd ;
145 ; altpll.tdf ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/altpll.tdf ;
146 ; aglobal90.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc ;
147 ; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc ;
148 ; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc ;
149 ; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc ;
150 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
153 +----------------------------------------------------------------------------------------+
154 ; Analysis & Synthesis Resource Usage Summary ;
155 +---------------------------------------------+------------------------------------------+
157 +---------------------------------------------+------------------------------------------+
158 ; Total logic elements ; 175 ;
159 ; -- Combinational with no register ; 92 ;
160 ; -- Register only ; 3 ;
161 ; -- Combinational with a register ; 80 ;
163 ; Logic element usage by number of LUT inputs ; ;
164 ; -- 4 input functions ; 60 ;
165 ; -- 3 input functions ; 52 ;
166 ; -- 2 input functions ; 58 ;
167 ; -- 1 input functions ; 2 ;
168 ; -- 0 input functions ; 0 ;
170 ; Logic elements by mode ; ;
171 ; -- normal mode ; 122 ;
172 ; -- arithmetic mode ; 53 ;
174 ; -- register cascade mode ; 0 ;
175 ; -- synchronous clear/load mode ; 69 ;
176 ; -- asynchronous clear/load mode ; 24 ;
178 ; Total registers ; 83 ;
179 ; Total logic cells in carry chains ; 61 ;
182 ; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ;
183 ; Maximum fan-out ; 84 ;
184 ; Total fan-out ; 845 ;
185 ; Average fan-out ; 2.88 ;
186 +---------------------------------------------+------------------------------------------+
189 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
190 ; Analysis & Synthesis Resource Utilization by Entity ;
191 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
192 ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
193 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
194 ; |vga_pll ; 175 (0) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; 92 (0) ; 3 (0) ; 80 (0) ; 61 (0) ; 0 (0) ; |vga_pll ; work ;
195 ; |vga:inst| ; 175 (2) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 ; 0 ; 92 (0) ; 3 (0) ; 80 (2) ; 61 (0) ; 0 (0) ; |vga_pll|vga:inst ; work ;
196 ; |vga_control:vga_control_unit| ; 43 (43) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 24 (24) ; 21 (21) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ;
197 ; |vga_driver:vga_driver_unit| ; 130 (130) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 (73) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ;
198 ; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ;
199 ; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ;
200 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
201 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
204 +------------------------------------------------------------------------------------------------------+
205 ; Registers Removed During Synthesis ;
206 +-------------------------------------------------------------+----------------------------------------+
207 ; Register name ; Reason for Removal ;
208 +-------------------------------------------------------------+----------------------------------------+
209 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_24 ; Stuck at GND due to stuck port reg_out ;
210 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_23 ; Stuck at GND due to stuck port reg_out ;
211 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_22 ; Stuck at GND due to stuck port reg_out ;
212 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_21 ; Stuck at GND due to stuck port reg_out ;
213 ; vga:inst|vga_control:vga_control_unit|g ; Stuck at GND due to stuck port reg_out ;
214 ; Total Number of Removed Registers = 5 ; ;
215 +-------------------------------------------------------------+----------------------------------------+
218 +------------------------------------------------------+
219 ; General Register Statistics ;
220 +----------------------------------------------+-------+
221 ; Statistic ; Value ;
222 +----------------------------------------------+-------+
223 ; Total registers ; 83 ;
224 ; Number of registers using Synchronous Clear ; 69 ;
225 ; Number of registers using Synchronous Load ; 20 ;
226 ; Number of registers using Asynchronous Clear ; 24 ;
227 ; Number of registers using Asynchronous Load ; 0 ;
228 ; Number of registers using Clock Enable ; 12 ;
229 ; Number of registers using Preset ; 0 ;
230 +----------------------------------------------+-------+
233 +---------------------------------------------------------------------------------+
234 ; Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component ;
235 +-------------------------------+-------------------+-----------------------------+
236 ; Parameter Name ; Value ; Type ;
237 +-------------------------------+-------------------+-----------------------------+
238 ; OPERATION_MODE ; NORMAL ; Untyped ;
239 ; PLL_TYPE ; AUTO ; Untyped ;
240 ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
241 ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
242 ; SCAN_CHAIN ; LONG ; Untyped ;
243 ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
244 ; INCLK0_INPUT_FREQUENCY ; 30003 ; Signed Integer ;
245 ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
246 ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
247 ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
248 ; LOCK_HIGH ; 1 ; Untyped ;
249 ; LOCK_LOW ; 1 ; Untyped ;
250 ; VALID_LOCK_MULTIPLIER ; 1 ; Signed Integer ;
251 ; INVALID_LOCK_MULTIPLIER ; 5 ; Signed Integer ;
252 ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
253 ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
254 ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
255 ; SKIP_VCO ; OFF ; Untyped ;
256 ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
257 ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
258 ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
259 ; BANDWIDTH ; 0 ; Untyped ;
260 ; BANDWIDTH_TYPE ; AUTO ; Untyped ;
261 ; SPREAD_FREQUENCY ; 0 ; Signed Integer ;
262 ; DOWN_SPREAD ; 0 ; Untyped ;
263 ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
264 ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
265 ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
266 ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
267 ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
268 ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
269 ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
270 ; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
271 ; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
272 ; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
273 ; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
274 ; CLK0_MULTIPLY_BY ; 5435 ; Signed Integer ;
275 ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
276 ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
277 ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
278 ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
279 ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
280 ; CLK4_DIVIDE_BY ; 1 ; Untyped ;
281 ; CLK3_DIVIDE_BY ; 1 ; Untyped ;
282 ; CLK2_DIVIDE_BY ; 1 ; Untyped ;
283 ; CLK1_DIVIDE_BY ; 1 ; Untyped ;
284 ; CLK0_DIVIDE_BY ; 6666 ; Signed Integer ;
285 ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
286 ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
287 ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
288 ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
289 ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
290 ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
291 ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
292 ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
293 ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
294 ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
295 ; CLK5_TIME_DELAY ; 0 ; Untyped ;
296 ; CLK4_TIME_DELAY ; 0 ; Untyped ;
297 ; CLK3_TIME_DELAY ; 0 ; Untyped ;
298 ; CLK2_TIME_DELAY ; 0 ; Untyped ;
299 ; CLK1_TIME_DELAY ; 0 ; Untyped ;
300 ; CLK0_TIME_DELAY ; 0 ; Untyped ;
301 ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
302 ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
303 ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
304 ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
305 ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
306 ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
307 ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
308 ; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
309 ; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
310 ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
311 ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
312 ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
313 ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
314 ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
315 ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
316 ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
317 ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
318 ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
319 ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
320 ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
321 ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
322 ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
323 ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
324 ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
325 ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
326 ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
327 ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
328 ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
329 ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
330 ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
331 ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
332 ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
333 ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
334 ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
335 ; DPA_MULTIPLY_BY ; 0 ; Untyped ;
336 ; DPA_DIVIDE_BY ; 1 ; Untyped ;
337 ; DPA_DIVIDER ; 0 ; Untyped ;
338 ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
339 ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
340 ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
341 ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
342 ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
343 ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
344 ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
345 ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
346 ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
347 ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
348 ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
349 ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
350 ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
351 ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
352 ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
353 ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
354 ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
355 ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
356 ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
357 ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
358 ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
359 ; VCO_DIVIDE_BY ; 0 ; Untyped ;
360 ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
361 ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
362 ; VCO_MIN ; 0 ; Untyped ;
363 ; VCO_MAX ; 0 ; Untyped ;
364 ; VCO_CENTER ; 0 ; Untyped ;
365 ; PFD_MIN ; 0 ; Untyped ;
366 ; PFD_MAX ; 0 ; Untyped ;
367 ; M_INITIAL ; 0 ; Untyped ;
373 ; C0_HIGH ; 0 ; Untyped ;
374 ; C1_HIGH ; 0 ; Untyped ;
375 ; C2_HIGH ; 0 ; Untyped ;
376 ; C3_HIGH ; 0 ; Untyped ;
377 ; C4_HIGH ; 0 ; Untyped ;
378 ; C5_HIGH ; 0 ; Untyped ;
379 ; C6_HIGH ; 0 ; Untyped ;
380 ; C7_HIGH ; 0 ; Untyped ;
381 ; C8_HIGH ; 0 ; Untyped ;
382 ; C9_HIGH ; 0 ; Untyped ;
383 ; C0_LOW ; 0 ; Untyped ;
384 ; C1_LOW ; 0 ; Untyped ;
385 ; C2_LOW ; 0 ; Untyped ;
386 ; C3_LOW ; 0 ; Untyped ;
387 ; C4_LOW ; 0 ; Untyped ;
388 ; C5_LOW ; 0 ; Untyped ;
389 ; C6_LOW ; 0 ; Untyped ;
390 ; C7_LOW ; 0 ; Untyped ;
391 ; C8_LOW ; 0 ; Untyped ;
392 ; C9_LOW ; 0 ; Untyped ;
393 ; C0_INITIAL ; 0 ; Untyped ;
394 ; C1_INITIAL ; 0 ; Untyped ;
395 ; C2_INITIAL ; 0 ; Untyped ;
396 ; C3_INITIAL ; 0 ; Untyped ;
397 ; C4_INITIAL ; 0 ; Untyped ;
398 ; C5_INITIAL ; 0 ; Untyped ;
399 ; C6_INITIAL ; 0 ; Untyped ;
400 ; C7_INITIAL ; 0 ; Untyped ;
401 ; C8_INITIAL ; 0 ; Untyped ;
402 ; C9_INITIAL ; 0 ; Untyped ;
403 ; C0_MODE ; BYPASS ; Untyped ;
404 ; C1_MODE ; BYPASS ; Untyped ;
405 ; C2_MODE ; BYPASS ; Untyped ;
406 ; C3_MODE ; BYPASS ; Untyped ;
407 ; C4_MODE ; BYPASS ; Untyped ;
408 ; C5_MODE ; BYPASS ; Untyped ;
409 ; C6_MODE ; BYPASS ; Untyped ;
410 ; C7_MODE ; BYPASS ; Untyped ;
411 ; C8_MODE ; BYPASS ; Untyped ;
412 ; C9_MODE ; BYPASS ; Untyped ;
413 ; C0_PH ; 0 ; Untyped ;
414 ; C1_PH ; 0 ; Untyped ;
415 ; C2_PH ; 0 ; Untyped ;
416 ; C3_PH ; 0 ; Untyped ;
417 ; C4_PH ; 0 ; Untyped ;
418 ; C5_PH ; 0 ; Untyped ;
419 ; C6_PH ; 0 ; Untyped ;
420 ; C7_PH ; 0 ; Untyped ;
421 ; C8_PH ; 0 ; Untyped ;
422 ; C9_PH ; 0 ; Untyped ;
423 ; L0_HIGH ; 1 ; Untyped ;
424 ; L1_HIGH ; 1 ; Untyped ;
425 ; G0_HIGH ; 1 ; Untyped ;
426 ; G1_HIGH ; 1 ; Untyped ;
427 ; G2_HIGH ; 1 ; Untyped ;
428 ; G3_HIGH ; 1 ; Untyped ;
429 ; E0_HIGH ; 1 ; Untyped ;
430 ; E1_HIGH ; 1 ; Untyped ;
431 ; E2_HIGH ; 1 ; Untyped ;
432 ; E3_HIGH ; 1 ; Untyped ;
433 ; L0_LOW ; 1 ; Untyped ;
434 ; L1_LOW ; 1 ; Untyped ;
435 ; G0_LOW ; 1 ; Untyped ;
436 ; G1_LOW ; 1 ; Untyped ;
437 ; G2_LOW ; 1 ; Untyped ;
438 ; G3_LOW ; 1 ; Untyped ;
439 ; E0_LOW ; 1 ; Untyped ;
440 ; E1_LOW ; 1 ; Untyped ;
441 ; E2_LOW ; 1 ; Untyped ;
442 ; E3_LOW ; 1 ; Untyped ;
443 ; L0_INITIAL ; 1 ; Untyped ;
444 ; L1_INITIAL ; 1 ; Untyped ;
445 ; G0_INITIAL ; 1 ; Untyped ;
446 ; G1_INITIAL ; 1 ; Untyped ;
447 ; G2_INITIAL ; 1 ; Untyped ;
448 ; G3_INITIAL ; 1 ; Untyped ;
449 ; E0_INITIAL ; 1 ; Untyped ;
450 ; E1_INITIAL ; 1 ; Untyped ;
451 ; E2_INITIAL ; 1 ; Untyped ;
452 ; E3_INITIAL ; 1 ; Untyped ;
453 ; L0_MODE ; BYPASS ; Untyped ;
454 ; L1_MODE ; BYPASS ; Untyped ;
455 ; G0_MODE ; BYPASS ; Untyped ;
456 ; G1_MODE ; BYPASS ; Untyped ;
457 ; G2_MODE ; BYPASS ; Untyped ;
458 ; G3_MODE ; BYPASS ; Untyped ;
459 ; E0_MODE ; BYPASS ; Untyped ;
460 ; E1_MODE ; BYPASS ; Untyped ;
461 ; E2_MODE ; BYPASS ; Untyped ;
462 ; E3_MODE ; BYPASS ; Untyped ;
463 ; L0_PH ; 0 ; Untyped ;
464 ; L1_PH ; 0 ; Untyped ;
465 ; G0_PH ; 0 ; Untyped ;
466 ; G1_PH ; 0 ; Untyped ;
467 ; G2_PH ; 0 ; Untyped ;
468 ; G3_PH ; 0 ; Untyped ;
469 ; E0_PH ; 0 ; Untyped ;
470 ; E1_PH ; 0 ; Untyped ;
471 ; E2_PH ; 0 ; Untyped ;
472 ; E3_PH ; 0 ; Untyped ;
473 ; M_PH ; 0 ; Untyped ;
474 ; C1_USE_CASC_IN ; OFF ; Untyped ;
475 ; C2_USE_CASC_IN ; OFF ; Untyped ;
476 ; C3_USE_CASC_IN ; OFF ; Untyped ;
477 ; C4_USE_CASC_IN ; OFF ; Untyped ;
478 ; C5_USE_CASC_IN ; OFF ; Untyped ;
479 ; C6_USE_CASC_IN ; OFF ; Untyped ;
480 ; C7_USE_CASC_IN ; OFF ; Untyped ;
481 ; C8_USE_CASC_IN ; OFF ; Untyped ;
482 ; C9_USE_CASC_IN ; OFF ; Untyped ;
483 ; CLK0_COUNTER ; G0 ; Untyped ;
484 ; CLK1_COUNTER ; G0 ; Untyped ;
485 ; CLK2_COUNTER ; G0 ; Untyped ;
486 ; CLK3_COUNTER ; G0 ; Untyped ;
487 ; CLK4_COUNTER ; G0 ; Untyped ;
488 ; CLK5_COUNTER ; G0 ; Untyped ;
489 ; CLK6_COUNTER ; E0 ; Untyped ;
490 ; CLK7_COUNTER ; E1 ; Untyped ;
491 ; CLK8_COUNTER ; E2 ; Untyped ;
492 ; CLK9_COUNTER ; E3 ; Untyped ;
493 ; L0_TIME_DELAY ; 0 ; Untyped ;
494 ; L1_TIME_DELAY ; 0 ; Untyped ;
495 ; G0_TIME_DELAY ; 0 ; Untyped ;
496 ; G1_TIME_DELAY ; 0 ; Untyped ;
497 ; G2_TIME_DELAY ; 0 ; Untyped ;
498 ; G3_TIME_DELAY ; 0 ; Untyped ;
499 ; E0_TIME_DELAY ; 0 ; Untyped ;
500 ; E1_TIME_DELAY ; 0 ; Untyped ;
501 ; E2_TIME_DELAY ; 0 ; Untyped ;
502 ; E3_TIME_DELAY ; 0 ; Untyped ;
503 ; M_TIME_DELAY ; 0 ; Untyped ;
504 ; N_TIME_DELAY ; 0 ; Untyped ;
505 ; EXTCLK3_COUNTER ; E3 ; Untyped ;
506 ; EXTCLK2_COUNTER ; E2 ; Untyped ;
507 ; EXTCLK1_COUNTER ; E1 ; Untyped ;
508 ; EXTCLK0_COUNTER ; E0 ; Untyped ;
509 ; ENABLE0_COUNTER ; L0 ; Untyped ;
510 ; ENABLE1_COUNTER ; L0 ; Untyped ;
511 ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
512 ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
513 ; LOOP_FILTER_C ; 5 ; Untyped ;
514 ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
515 ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
516 ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
517 ; VCO_POST_SCALE ; 0 ; Untyped ;
518 ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
519 ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
520 ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
521 ; INTENDED_DEVICE_FAMILY ; Stratix ; Untyped ;
522 ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
523 ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
524 ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
525 ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
526 ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
527 ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
528 ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
529 ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
530 ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
531 ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
532 ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
533 ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
534 ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
535 ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
536 ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
537 ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
538 ; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
539 ; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
540 ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
541 ; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
542 ; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
543 ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
544 ; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
545 ; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
546 ; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
547 ; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
548 ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
549 ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
550 ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
551 ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
552 ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
553 ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
554 ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
555 ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
556 ; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
557 ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
558 ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
559 ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
560 ; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
561 ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
562 ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
563 ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
564 ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
565 ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
566 ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
567 ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
568 ; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;
569 ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
570 ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
571 ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
572 ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
573 ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
574 ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
575 ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
576 ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
577 ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
578 ; M_TEST_SOURCE ; 5 ; Untyped ;
579 ; C0_TEST_SOURCE ; 5 ; Untyped ;
580 ; C1_TEST_SOURCE ; 5 ; Untyped ;
581 ; C2_TEST_SOURCE ; 5 ; Untyped ;
582 ; C3_TEST_SOURCE ; 5 ; Untyped ;
583 ; C4_TEST_SOURCE ; 5 ; Untyped ;
584 ; C5_TEST_SOURCE ; 5 ; Untyped ;
585 ; C6_TEST_SOURCE ; 5 ; Untyped ;
586 ; C7_TEST_SOURCE ; 5 ; Untyped ;
587 ; C8_TEST_SOURCE ; 5 ; Untyped ;
588 ; C9_TEST_SOURCE ; 5 ; Untyped ;
589 ; CBXI_PARAMETER ; NOTHING ; Untyped ;
590 ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
591 ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
592 ; WIDTH_CLOCK ; 6 ; Untyped ;
593 ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
594 ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
595 ; DEVICE_FAMILY ; Stratix ; Untyped ;
596 ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
597 ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
598 ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
599 ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
600 ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
601 ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
602 +-------------------------------+-------------------+-----------------------------+
603 Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
606 +--------------------------------------------------------------------+
607 ; altpll Parameter Settings by Entity Instance ;
608 +-------------------------------+------------------------------------+
610 +-------------------------------+------------------------------------+
611 ; Number of entity instances ; 1 ;
612 ; Entity Instance ; vpll:inst1|altpll:altpll_component ;
613 ; -- OPERATION_MODE ; NORMAL ;
614 ; -- PLL_TYPE ; AUTO ;
615 ; -- PRIMARY_CLOCK ; INCLK0 ;
616 ; -- INCLK0_INPUT_FREQUENCY ; 30003 ;
617 ; -- INCLK1_INPUT_FREQUENCY ; 0 ;
618 ; -- VCO_MULTIPLY_BY ; 0 ;
619 ; -- VCO_DIVIDE_BY ; 0 ;
620 +-------------------------------+------------------------------------+
623 +-------------------------------+
624 ; Analysis & Synthesis Messages ;
625 +-------------------------------+
626 Info: *******************************************************************
627 Info: Running Quartus II Analysis & Synthesis
628 Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
629 Info: Processing started: Wed Oct 28 14:54:33 2009
630 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
631 Info: Revision "vga_pll" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0.
632 Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf
633 Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf
634 Info: Found entity 1: vga_pll
635 Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
636 Info: Found entity 1: vga_driver
637 Info: Found entity 2: vga_control
638 Info: Found entity 3: vga
639 Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd
640 Info: Found design unit 1: vpll-SYN
641 Info: Found entity 1: vpll
642 Info: Elaborating entity "vga_pll" for the top level hierarchy
643 Info: Elaborating entity "vga" for hierarchy "vga:inst"
644 Info: Elaborating entity "vga_driver" for hierarchy "vga:inst|vga_driver:vga_driver_unit"
645 Info: Elaborating entity "vga_control" for hierarchy "vga:inst|vga_control:vga_control_unit"
646 Info: Elaborating entity "vpll" for hierarchy "vpll:inst1"
647 Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object "locked" assigned a value but never read
648 Info: Elaborating entity "altpll" for hierarchy "vpll:inst1|altpll:altpll_component"
649 Info: Elaborated megafunction instantiation "vpll:inst1|altpll:altpll_component"
650 Info: Instantiated megafunction "vpll:inst1|altpll:altpll_component" with the following parameter:
651 Info: Parameter "bandwidth_type" = "AUTO"
652 Info: Parameter "clk0_duty_cycle" = "50"
653 Info: Parameter "lpm_type" = "altpll"
654 Info: Parameter "clk0_multiply_by" = "5435"
655 Info: Parameter "invalid_lock_multiplier" = "5"
656 Info: Parameter "inclk0_input_frequency" = "30003"
657 Info: Parameter "gate_lock_signal" = "NO"
658 Info: Parameter "clk0_divide_by" = "6666"
659 Info: Parameter "pll_type" = "AUTO"
660 Info: Parameter "valid_lock_multiplier" = "1"
661 Info: Parameter "clk0_time_delay" = "0"
662 Info: Parameter "spread_frequency" = "0"
663 Info: Parameter "intended_device_family" = "Stratix"
664 Info: Parameter "operation_mode" = "NORMAL"
665 Info: Parameter "compensate_clock" = "CLK0"
666 Info: Parameter "clk0_phase_shift" = "0"
667 Info: WYSIWYG I/O primitives converted to equivalent logic
668 Info: WYSIWYG I/O primitive "vga:inst|clk_pin_in" converted to equivalent logic
669 Info: Implemented 293 device resources after synthesis - the final resource count might be different
670 Info: Implemented 2 input pins
671 Info: Implemented 115 output pins
672 Info: Implemented 175 logic cells
673 Info: Implemented 1 ClockLock PLLs
674 Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
675 Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
676 Info: Peak virtual memory: 204 megabytes
677 Info: Processing ended: Wed Oct 28 14:54:40 2009
678 Info: Elapsed time: 00:00:07
679 Info: Total CPU time (on all processors): 00:00:04
projects / dide_16.git / blob