1 { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
2 { "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:55:36 2009 " "Info: Processing started: Wed Oct 28 14:55:36 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
3 { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
4 { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
5 { "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1}
6 { "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1}
7 { "Info" "ITDB_FULL_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 register vga:inst\|vga_control:vga_control_unit\|r 28.83 ns " "Info: Slack time is 28.83 ns for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4\" and destination register \"vga:inst\|vga_control:vga_control_unit\|r\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "125.83 MHz 7.947 ns " "Info: Fmax is 125.83 MHz (period= 7.947 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.570 ns + Largest register register " "Info: + Largest register to register requirement is 36.570 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "36.777 ns + " "Info: + Setup relationship between source and destination is 36.777 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.747 ns " "Info: + Latch edge is 35.747 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.021 ns + Largest " "Info: + Largest clock skew is -0.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.043 ns + Shortest register " "Info: + Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|vga_control:vga_control_unit\|r 2 REG LC_X72_Y6_N1 4 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.064 ns - Longest register " "Info: - Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.504 ns) + CELL(0.560 ns) 2.064 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 2 REG LC_X22_Y42_N7 9 " "Info: 2: + IC(1.504 ns) + CELL(0.560 ns) = 2.064 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.13 % ) " "Info: Total cell delay = 0.560 ns ( 27.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.504 ns ( 72.87 % ) " "Info: Total interconnect delay = 1.504 ns ( 72.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.740 ns - Longest register register " "Info: - Longest register to register delay is 7.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 1 REG LC_X22_Y42_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.332 ns) 1.344 ns vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto4_0 2 COMB LC_X18_Y42_N6 1 " "Info: 2: + IC(1.012 ns) + CELL(0.332 ns) = 1.344 ns; Loc. = LC_X18_Y42_N6; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto4_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.344 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3301 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.332 ns) 2.012 ns vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto6 3 COMB LC_X18_Y42_N4 1 " "Info: 3: + IC(0.336 ns) + CELL(0.332 ns) = 2.012 ns; Loc. = LC_X18_Y42_N4; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.668 ns" { vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3293 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.332 ns) 4.112 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4 4 COMB LC_X28_Y35_N2 2 " "Info: 4: + IC(1.768 ns) + CELL(0.332 ns) = 4.112 ns; Loc. = LC_X28_Y35_N2; Fanout = 2; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.100 ns" { vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3286 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.139 ns) + CELL(0.489 ns) 7.740 ns vga:inst\|vga_control:vga_control_unit\|r 5 REG LC_X72_Y6_N1 4 " "Info: 5: + IC(3.139 ns) + CELL(0.489 ns) = 7.740 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.628 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.485 ns ( 19.19 % ) " "Info: Total cell delay = 1.485 ns ( 19.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.255 ns ( 80.81 % ) " "Info: Total interconnect delay = 6.255 ns ( 80.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 {} vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.012ns 0.336ns 1.768ns 3.139ns } { 0.000ns 0.332ns 0.332ns 0.332ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 {} vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.012ns 0.336ns 1.768ns 3.139ns } { 0.000ns 0.332ns 0.332ns 0.332ns 0.489ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
8 { "Info" "ITAN_NO_REG2REG_EXIST" "board_clk " "Info: No valid register-to-register data paths exist for clock \"board_clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
9 { "Info" "ITDB_FULL_MIN_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 register vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 730 ps " "Info: Minimum slack time is 730 ps for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0\" and destination register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.654 ns + Shortest register register " "Info: + Shortest register to register delay is 0.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 1 REG LC_X42_Y42_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.235 ns) 0.654 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X42_Y42_N2 4 " "Info: 2: + IC(0.419 ns) + CELL(0.235 ns) = 0.654 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.93 % ) " "Info: Total cell delay = 0.235 ns ( 35.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.419 ns ( 64.07 % ) " "Info: Total interconnect delay = 0.419 ns ( 64.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.419ns } { 0.000ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.030 ns " "Info: + Latch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.097 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X42_Y42_N2 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.097 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 2 REG LC_X42_Y42_N9 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.419ns } { 0.000ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
10 { "Info" "ITDB_TSU_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 reset board_clk 10.866 ns register " "Info: tsu for register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0\" (data pin = \"reset\", clock pin = \"board_clk\") is 10.866 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.923 ns + Longest pin register " "Info: + Longest pin to register delay is 11.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.624 ns) + CELL(0.213 ns) 6.978 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.837 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.397 ns) + CELL(0.213 ns) 9.588 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X52_Y41_N9 6 " "Info: 3: + IC(2.397 ns) + CELL(0.213 ns) = 9.588 ns; Loc. = LC_X52_Y41_N9; Fanout = 6; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.610 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.609 ns) + CELL(0.726 ns) 11.923 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 4 REG LC_X42_Y42_N9 4 " "Info: 4: + IC(1.609 ns) + CELL(0.726 ns) = 11.923 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.335 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.293 ns ( 19.23 % ) " "Info: Total cell delay = 2.293 ns ( 19.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.630 ns ( 80.77 % ) " "Info: Total interconnect delay = 9.630 ns ( 80.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.923 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.923 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 5.624ns 2.397ns 1.609ns } { 0.000ns 1.141ns 0.213ns 0.213ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns - " "Info: - Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.097 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 2 REG LC_X42_Y42_N9 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.923 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.923 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 5.624ns 2.397ns 1.609ns } { 0.000ns 1.141ns 0.213ns 0.213ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
11 { "Info" "ITDB_FULL_TCO_RESULT" "board_clk seven_seg_pin\[7\] vga:inst\|dly_counter\[0\] 11.498 ns register " "Info: tco from clock \"board_clk\" to destination pin \"seven_seg_pin\[7\]\" through register \"vga:inst\|dly_counter\[0\]\" is 11.498 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.043 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.309 ns + Longest register pin " "Info: + Longest register to pin delay is 10.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|dly_counter\[0\] 1 REG LC_X30_Y39_N4 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(0.087 ns) 1.251 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(1.164 ns) + CELL(0.087 ns) = 1.251 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.251 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.867 ns) + CELL(4.191 ns) 10.309 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 10.309 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.058 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 240 928 1148 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.278 ns ( 41.50 % ) " "Info: Total cell delay = 4.278 ns ( 41.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.031 ns ( 58.50 % ) " "Info: Total interconnect delay = 6.031 ns ( 58.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.309 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.309 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 1.164ns 4.867ns } { 0.000ns 0.087ns 4.191ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.309 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.309 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 1.164ns 4.867ns } { 0.000ns 0.087ns 4.191ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
12 { "Info" "ITDB_FULL_TPD_RESULT" "reset seven_seg_pin\[7\] 16.036 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seven_seg_pin\[7\]\" is 16.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.624 ns) + CELL(0.213 ns) 6.978 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.837 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.867 ns) + CELL(4.191 ns) 16.036 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 16.036 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.058 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 240 928 1148 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.545 ns ( 34.58 % ) " "Info: Total cell delay = 5.545 ns ( 34.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.491 ns ( 65.42 % ) " "Info: Total interconnect delay = 10.491 ns ( 65.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "16.036 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "16.036 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.000ns 5.624ns 4.867ns } { 0.000ns 1.141ns 0.213ns 4.191ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
13 { "Info" "ITDB_TH_RESULT" "vga:inst\|dly_counter\[0\] reset board_clk -5.569 ns register " "Info: th for register \"vga:inst\|dly_counter\[0\]\" (data pin = \"reset\", clock pin = \"board_clk\") is -5.569 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.043 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.682 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.177 ns) + CELL(0.364 ns) 6.682 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(5.177 ns) + CELL(0.364 ns) = 6.682 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.541 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 22.52 % ) " "Info: Total cell delay = 1.505 ns ( 22.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.177 ns ( 77.48 % ) " "Info: Total interconnect delay = 5.177 ns ( 77.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.682 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.682 ns" { reset {} reset~out0 {} vga:inst|dly_counter[0] {} } { 0.000ns 0.000ns 5.177ns } { 0.000ns 1.141ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.682 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.682 ns" { reset {} reset~out0 {} vga:inst|dly_counter[0] {} } { 0.000ns 0.000ns 5.177ns } { 0.000ns 1.141ns 0.364ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
14 { "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0 -1}
15 { "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:55:37 2009 " "Info: Processing ended: Wed Oct 28 14:55:37 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blob