bsp2/Designflow/ppr/download/db/vga_pll.hif

   1 Version 9.0 Build 132 02/25/2009 SJ Full Version
   2 45
   3 3235
   4 OFF
   5 OFF
   6 OFF
   7 ON
   8 ON
   9 OFF
  10 FV_OFF
  11 Level2
  12 0
  13 0
  14 VRSM_ON
  15 VHSM_ON
  16 synplcty.lmf
  17 -- Start Library Paths --
  18 -- End Library Paths --
  19 -- Start VHDL Libraries --
  20 -- End VHDL Libraries --
  21 # entity
  22 vga_pll
  23 # storage
  24 db|vga_pll.(0).cnf
  25 db|vga_pll.(0).cnf
  26 # case_insensitive
  27 # source_file
  28 ..|..|src|vga_pll.bdf
  29 99c3b73be69bba6a49dedfda59395ee
  30 26
  31 # internal_option {
  32 BLOCK_DESIGN_NAMING
  33 AUTO
  34 }
  35 # hierarchies {
  36 |
  37 }
  38 # lmf
  39 |opt|quartus|quartus|lmf|synplcty.lmf
  40 3057712873b497a38b70a3917f30cc38
  41 # macro_sequence
  42
  43 # end
  44 # entity
  45 vga
  46 # storage
  47 db|vga_pll.(1).cnf
  48 db|vga_pll.(1).cnf
  49 # case_sensitive
  50 # source_file
  51 ..|..|syn|rev_1|vga.vqm
  52 a69bdf2838bc2ddfa265318d6caf919c
  53 28
  54 # hierarchies {
  55 vga:inst
  56 }
  57 # lmf
  58 |opt|quartus|quartus|lmf|synplcty.lmf
  59 3057712873b497a38b70a3917f30cc38
  60 # macro_sequence
  61
  62 # end
  63 # entity
  64 vga_driver
  65 # storage
  66 db|vga_pll.(2).cnf
  67 db|vga_pll.(2).cnf
  68 # case_sensitive
  69 # source_file
  70 ..|..|syn|rev_1|vga.vqm
  71 a69bdf2838bc2ddfa265318d6caf919c
  72 28
  73 # hierarchies {
  74 vga:inst|vga_driver:vga_driver_unit
  75 }
  76 # lmf
  77 |opt|quartus|quartus|lmf|synplcty.lmf
  78 3057712873b497a38b70a3917f30cc38
  79 # macro_sequence
  80
  81 # end
  82 # entity
  83 vga_control
  84 # storage
  85 db|vga_pll.(3).cnf
  86 db|vga_pll.(3).cnf
  87 # case_sensitive
  88 # source_file
  89 ..|..|syn|rev_1|vga.vqm
  90 a69bdf2838bc2ddfa265318d6caf919c
  91 28
  92 # hierarchies {
  93 vga:inst|vga_control:vga_control_unit
  94 }
  95 # lmf
  96 |opt|quartus|quartus|lmf|synplcty.lmf
  97 3057712873b497a38b70a3917f30cc38
  98 # macro_sequence
  99
 100 # end
 101 # entity
 102 vpll
 103 # storage
 104 db|vga_pll.(4).cnf
 105 db|vga_pll.(4).cnf
 106 # logic_option {
 107 AUTO_RAM_RECOGNITION
 108 ON
 109 }
 110 # case_insensitive
 111 # source_file
 112 ..|..|src|vpll.vhd
 113 ccc2bcb05887d5721243fd22481948be
 114 5
 115 # internal_option {
 116 HDL_INITIAL_FANOUT_LIMIT
 117 OFF
 118 AUTO_RESOURCE_SHARING
 119 OFF
 120 AUTO_RAM_RECOGNITION
 121 ON
 122 AUTO_ROM_RECOGNITION
 123 ON
 124 }
 125 # hierarchies {
 126 vpll:inst1
 127 }
 128 # lmf
 129 |opt|quartus|quartus|lmf|maxplus2.lmf
 130 9a59d39b0706640b4b2718e8a1ff1f
 131 # macro_sequence
 132
 133 # end
 134 # entity
 135 altpll
 136 # storage
 137 db|vga_pll.(5).cnf
 138 db|vga_pll.(5).cnf
 139 # case_insensitive
 140 # source_file
 141 |opt|quartus|quartus|libraries|megafunctions|altpll.tdf
 142 d980162588d7aa8b78874932c782e18
 143 7
 144 # user_parameter {
 145 OPERATION_MODE
 146 NORMAL
 147 PARAMETER_UNKNOWN
 148 USR
 149 PLL_TYPE
 150 AUTO
 151 PARAMETER_UNKNOWN
 152 USR
 153 QUALIFY_CONF_DONE
 154 OFF
 155 PARAMETER_UNKNOWN
 156 DEF
 157 COMPENSATE_CLOCK
 158 CLK0
 159 PARAMETER_UNKNOWN
 160 USR
 161 SCAN_CHAIN
 162 LONG
 163 PARAMETER_UNKNOWN
 164 DEF
 165 PRIMARY_CLOCK
 166 INCLK0
 167 PARAMETER_UNKNOWN
 168 DEF
 169 INCLK0_INPUT_FREQUENCY
 170 30003
 171 PARAMETER_SIGNED_DEC
 172 USR
 173 INCLK1_INPUT_FREQUENCY
 174 0
 175 PARAMETER_UNKNOWN
 176 DEF
 177 GATE_LOCK_SIGNAL
 178 NO
 179 PARAMETER_UNKNOWN
 180 USR
 181 GATE_LOCK_COUNTER
 182 0
 183 PARAMETER_UNKNOWN
 184 DEF
 185 LOCK_HIGH
 186 1
 187 PARAMETER_UNKNOWN
 188 DEF
 189 LOCK_LOW
 190 1
 191 PARAMETER_UNKNOWN
 192 DEF
 193 VALID_LOCK_MULTIPLIER
 194 1
 195 PARAMETER_SIGNED_DEC
 196 USR
 197 INVALID_LOCK_MULTIPLIER
 198 5
 199 PARAMETER_SIGNED_DEC
 200 USR
 201 SWITCH_OVER_ON_LOSSCLK
 202 OFF
 203 PARAMETER_UNKNOWN
 204 DEF
 205 SWITCH_OVER_ON_GATED_LOCK
 206 OFF
 207 PARAMETER_UNKNOWN
 208 DEF
 209 ENABLE_SWITCH_OVER_COUNTER
 210 OFF
 211 PARAMETER_UNKNOWN
 212 DEF
 213 SKIP_VCO
 214 OFF
 215 PARAMETER_UNKNOWN
 216 DEF
 217 SWITCH_OVER_COUNTER
 218 0
 219 PARAMETER_UNKNOWN
 220 DEF
 221 SWITCH_OVER_TYPE
 222 AUTO
 223 PARAMETER_UNKNOWN
 224 DEF
 225 FEEDBACK_SOURCE
 226 EXTCLK0
 227 PARAMETER_UNKNOWN
 228 DEF
 229 BANDWIDTH
 230 0
 231 PARAMETER_UNKNOWN
 232 DEF
 233 BANDWIDTH_TYPE
 234 AUTO
 235 PARAMETER_UNKNOWN
 236 USR
 237 SPREAD_FREQUENCY
 238 0
 239 PARAMETER_SIGNED_DEC
 240 USR
 241 DOWN_SPREAD
 242 0
 243 PARAMETER_UNKNOWN
 244 DEF
 245 SELF_RESET_ON_GATED_LOSS_LOCK
 246 OFF
 247 PARAMETER_UNKNOWN
 248 DEF
 249 SELF_RESET_ON_LOSS_LOCK
 250 OFF
 251 PARAMETER_UNKNOWN
 252 DEF
 253 CLK9_MULTIPLY_BY
 254 0
 255 PARAMETER_UNKNOWN
 256 DEF
 257 CLK8_MULTIPLY_BY
 258 0
 259 PARAMETER_UNKNOWN
 260 DEF
 261 CLK7_MULTIPLY_BY
 262 0
 263 PARAMETER_UNKNOWN
 264 DEF
 265 CLK6_MULTIPLY_BY
 266 0
 267 PARAMETER_UNKNOWN
 268 DEF
 269 CLK5_MULTIPLY_BY
 270 1
 271 PARAMETER_UNKNOWN
 272 DEF
 273 CLK4_MULTIPLY_BY
 274 1
 275 PARAMETER_UNKNOWN
 276 DEF
 277 CLK3_MULTIPLY_BY
 278 1
 279 PARAMETER_UNKNOWN
 280 DEF
 281 CLK2_MULTIPLY_BY
 282 1
 283 PARAMETER_UNKNOWN
 284 DEF
 285 CLK1_MULTIPLY_BY
 286 1
 287 PARAMETER_UNKNOWN
 288 DEF
 289 CLK0_MULTIPLY_BY
 290 5435
 291 PARAMETER_SIGNED_DEC
 292 USR
 293 CLK9_DIVIDE_BY
 294 0
 295 PARAMETER_UNKNOWN
 296 DEF
 297 CLK8_DIVIDE_BY
 298 0
 299 PARAMETER_UNKNOWN
 300 DEF
 301 CLK7_DIVIDE_BY
 302 0
 303 PARAMETER_UNKNOWN
 304 DEF
 305 CLK6_DIVIDE_BY
 306 0
 307 PARAMETER_UNKNOWN
 308 DEF
 309 CLK5_DIVIDE_BY
 310 1
 311 PARAMETER_UNKNOWN
 312 DEF
 313 CLK4_DIVIDE_BY
 314 1
 315 PARAMETER_UNKNOWN
 316 DEF
 317 CLK3_DIVIDE_BY
 318 1
 319 PARAMETER_UNKNOWN
 320 DEF
 321 CLK2_DIVIDE_BY
 322 1
 323 PARAMETER_UNKNOWN
 324 DEF
 325 CLK1_DIVIDE_BY
 326 1
 327 PARAMETER_UNKNOWN
 328 DEF
 329 CLK0_DIVIDE_BY
 330 6666
 331 PARAMETER_SIGNED_DEC
 332 USR
 333 CLK9_PHASE_SHIFT
 334 0
 335 PARAMETER_UNKNOWN
 336 DEF
 337 CLK8_PHASE_SHIFT
 338 0
 339 PARAMETER_UNKNOWN
 340 DEF
 341 CLK7_PHASE_SHIFT
 342 0
 343 PARAMETER_UNKNOWN
 344 DEF
 345 CLK6_PHASE_SHIFT
 346 0
 347 PARAMETER_UNKNOWN
 348 DEF
 349 CLK5_PHASE_SHIFT
 350 0
 351 PARAMETER_UNKNOWN
 352 DEF
 353 CLK4_PHASE_SHIFT
 354 0
 355 PARAMETER_UNKNOWN
 356 DEF
 357 CLK3_PHASE_SHIFT
 358 0
 359 PARAMETER_UNKNOWN
 360 DEF
 361 CLK2_PHASE_SHIFT
 362 0
 363 PARAMETER_UNKNOWN
 364 DEF
 365 CLK1_PHASE_SHIFT
 366 0
 367 PARAMETER_UNKNOWN
 368 DEF
 369 CLK0_PHASE_SHIFT
 370 0
 371 PARAMETER_UNKNOWN
 372 USR
 373 CLK5_TIME_DELAY
 374 0
 375 PARAMETER_UNKNOWN
 376 DEF
 377 CLK4_TIME_DELAY
 378 0
 379 PARAMETER_UNKNOWN
 380 DEF
 381 CLK3_TIME_DELAY
 382 0
 383 PARAMETER_UNKNOWN
 384 DEF
 385 CLK2_TIME_DELAY
 386 0
 387 PARAMETER_UNKNOWN
 388 DEF
 389 CLK1_TIME_DELAY
 390 0
 391 PARAMETER_UNKNOWN
 392 DEF
 393 CLK0_TIME_DELAY
 394 0
 395 PARAMETER_UNKNOWN
 396 USR
 397 CLK9_DUTY_CYCLE
 398 50
 399 PARAMETER_UNKNOWN
 400 DEF
 401 CLK8_DUTY_CYCLE
 402 50
 403 PARAMETER_UNKNOWN
 404 DEF
 405 CLK7_DUTY_CYCLE
 406 50
 407 PARAMETER_UNKNOWN
 408 DEF
 409 CLK6_DUTY_CYCLE
 410 50
 411 PARAMETER_UNKNOWN
 412 DEF
 413 CLK5_DUTY_CYCLE
 414 50
 415 PARAMETER_UNKNOWN
 416 DEF
 417 CLK4_DUTY_CYCLE
 418 50
 419 PARAMETER_UNKNOWN
 420 DEF
 421 CLK3_DUTY_CYCLE
 422 50
 423 PARAMETER_UNKNOWN
 424 DEF
 425 CLK2_DUTY_CYCLE
 426 50
 427 PARAMETER_UNKNOWN
 428 DEF
 429 CLK1_DUTY_CYCLE
 430 50
 431 PARAMETER_UNKNOWN
 432 DEF
 433 CLK0_DUTY_CYCLE
 434 50
 435 PARAMETER_SIGNED_DEC
 436 USR
 437 CLK9_USE_EVEN_COUNTER_MODE
 438 OFF
 439 PARAMETER_UNKNOWN
 440 DEF
 441 CLK8_USE_EVEN_COUNTER_MODE
 442 OFF
 443 PARAMETER_UNKNOWN
 444 DEF
 445 CLK7_USE_EVEN_COUNTER_MODE
 446 OFF
 447 PARAMETER_UNKNOWN
 448 DEF
 449 CLK6_USE_EVEN_COUNTER_MODE
 450 OFF
 451 PARAMETER_UNKNOWN
 452 DEF
 453 CLK5_USE_EVEN_COUNTER_MODE
 454 OFF
 455 PARAMETER_UNKNOWN
 456 DEF
 457 CLK4_USE_EVEN_COUNTER_MODE
 458 OFF
 459 PARAMETER_UNKNOWN
 460 DEF
 461 CLK3_USE_EVEN_COUNTER_MODE
 462 OFF
 463 PARAMETER_UNKNOWN
 464 DEF
 465 CLK2_USE_EVEN_COUNTER_MODE
 466 OFF
 467 PARAMETER_UNKNOWN
 468 DEF
 469 CLK1_USE_EVEN_COUNTER_MODE
 470 OFF
 471 PARAMETER_UNKNOWN
 472 DEF
 473 CLK0_USE_EVEN_COUNTER_MODE
 474 OFF
 475 PARAMETER_UNKNOWN
 476 DEF
 477 CLK9_USE_EVEN_COUNTER_VALUE
 478 OFF
 479 PARAMETER_UNKNOWN
 480 DEF
 481 CLK8_USE_EVEN_COUNTER_VALUE
 482 OFF
 483 PARAMETER_UNKNOWN
 484 DEF
 485 CLK7_USE_EVEN_COUNTER_VALUE
 486 OFF
 487 PARAMETER_UNKNOWN
 488 DEF
 489 CLK6_USE_EVEN_COUNTER_VALUE
 490 OFF
 491 PARAMETER_UNKNOWN
 492 DEF
 493 CLK5_USE_EVEN_COUNTER_VALUE
 494 OFF
 495 PARAMETER_UNKNOWN
 496 DEF
 497 CLK4_USE_EVEN_COUNTER_VALUE
 498 OFF
 499 PARAMETER_UNKNOWN
 500 DEF
 501 CLK3_USE_EVEN_COUNTER_VALUE
 502 OFF
 503 PARAMETER_UNKNOWN
 504 DEF
 505 CLK2_USE_EVEN_COUNTER_VALUE
 506 OFF
 507 PARAMETER_UNKNOWN
 508 DEF
 509 CLK1_USE_EVEN_COUNTER_VALUE
 510 OFF
 511 PARAMETER_UNKNOWN
 512 DEF
 513 CLK0_USE_EVEN_COUNTER_VALUE
 514 OFF
 515 PARAMETER_UNKNOWN
 516 DEF
 517 LOCK_WINDOW_UI
 518  0.05
 519 PARAMETER_UNKNOWN
 520 DEF
 521 LOCK_WINDOW_UI_BITS
 522 UNUSED
 523 PARAMETER_UNKNOWN
 524 DEF
 525 VCO_RANGE_DETECTOR_LOW_BITS
 526 UNUSED
 527 PARAMETER_UNKNOWN
 528 DEF
 529 VCO_RANGE_DETECTOR_HIGH_BITS
 530 UNUSED
 531 PARAMETER_UNKNOWN
 532 DEF
 533 DPA_MULTIPLY_BY
 534 0
 535 PARAMETER_UNKNOWN
 536 DEF
 537 DPA_DIVIDE_BY
 538 1
 539 PARAMETER_UNKNOWN
 540 DEF
 541 DPA_DIVIDER
 542 0
 543 PARAMETER_UNKNOWN
 544 DEF
 545 EXTCLK3_MULTIPLY_BY
 546 1
 547 PARAMETER_UNKNOWN
 548 DEF
 549 EXTCLK2_MULTIPLY_BY
 550 1
 551 PARAMETER_UNKNOWN
 552 DEF
 553 EXTCLK1_MULTIPLY_BY
 554 1
 555 PARAMETER_UNKNOWN
 556 DEF
 557 EXTCLK0_MULTIPLY_BY
 558 1
 559 PARAMETER_UNKNOWN
 560 DEF
 561 EXTCLK3_DIVIDE_BY
 562 1
 563 PARAMETER_UNKNOWN
 564 DEF
 565 EXTCLK2_DIVIDE_BY
 566 1
 567 PARAMETER_UNKNOWN
 568 DEF
 569 EXTCLK1_DIVIDE_BY
 570 1
 571 PARAMETER_UNKNOWN
 572 DEF
 573 EXTCLK0_DIVIDE_BY
 574 1
 575 PARAMETER_UNKNOWN
 576 DEF
 577 EXTCLK3_PHASE_SHIFT
 578 0
 579 PARAMETER_UNKNOWN
 580 DEF
 581 EXTCLK2_PHASE_SHIFT
 582 0
 583 PARAMETER_UNKNOWN
 584 DEF
 585 EXTCLK1_PHASE_SHIFT
 586 0
 587 PARAMETER_UNKNOWN
 588 DEF
 589 EXTCLK0_PHASE_SHIFT
 590 0
 591 PARAMETER_UNKNOWN
 592 DEF
 593 EXTCLK3_TIME_DELAY
 594 0
 595 PARAMETER_UNKNOWN
 596 DEF
 597 EXTCLK2_TIME_DELAY
 598 0
 599 PARAMETER_UNKNOWN
 600 DEF
 601 EXTCLK1_TIME_DELAY
 602 0
 603 PARAMETER_UNKNOWN
 604 DEF
 605 EXTCLK0_TIME_DELAY
 606 0
 607 PARAMETER_UNKNOWN
 608 DEF
 609 EXTCLK3_DUTY_CYCLE
 610 50
 611 PARAMETER_UNKNOWN
 612 DEF
 613 EXTCLK2_DUTY_CYCLE
 614 50
 615 PARAMETER_UNKNOWN
 616 DEF
 617 EXTCLK1_DUTY_CYCLE
 618 50
 619 PARAMETER_UNKNOWN
 620 DEF
 621 EXTCLK0_DUTY_CYCLE
 622 50
 623 PARAMETER_UNKNOWN
 624 DEF
 625 VCO_MULTIPLY_BY
 626 0
 627 PARAMETER_UNKNOWN
 628 DEF
 629 VCO_DIVIDE_BY
 630 0
 631 PARAMETER_UNKNOWN
 632 DEF
 633 SCLKOUT0_PHASE_SHIFT
 634 0
 635 PARAMETER_UNKNOWN
 636 DEF
 637 SCLKOUT1_PHASE_SHIFT
 638 0
 639 PARAMETER_UNKNOWN
 640 DEF
 641 VCO_MIN
 642 0
 643 PARAMETER_UNKNOWN
 644 DEF
 645 VCO_MAX
 646 0
 647 PARAMETER_UNKNOWN
 648 DEF
 649 VCO_CENTER
 650 0
 651 PARAMETER_UNKNOWN
 652 DEF
 653 PFD_MIN
 654 0
 655 PARAMETER_UNKNOWN
 656 DEF
 657 PFD_MAX
 658 0
 659 PARAMETER_UNKNOWN
 660 DEF
 661 M_INITIAL
 662 0
 663 PARAMETER_UNKNOWN
 664 DEF
 665 M
 666 0
 667 PARAMETER_UNKNOWN
 668 DEF
 669 N
 670 1
 671 PARAMETER_UNKNOWN
 672 DEF
 673 M2
 674 1
 675 PARAMETER_UNKNOWN
 676 DEF
 677 N2
 678 1
 679 PARAMETER_UNKNOWN
 680 DEF
 681 SS
 682 1
 683 PARAMETER_UNKNOWN
 684 DEF
 685 C0_HIGH
 686 0
 687 PARAMETER_UNKNOWN
 688 DEF
 689 C1_HIGH
 690 0
 691 PARAMETER_UNKNOWN
 692 DEF
 693 C2_HIGH
 694 0
 695 PARAMETER_UNKNOWN
 696 DEF
 697 C3_HIGH
 698 0
 699 PARAMETER_UNKNOWN
 700 DEF
 701 C4_HIGH
 702 0
 703 PARAMETER_UNKNOWN
 704 DEF
 705 C5_HIGH
 706 0
 707 PARAMETER_UNKNOWN
 708 DEF
 709 C6_HIGH
 710 0
 711 PARAMETER_UNKNOWN
 712 DEF
 713 C7_HIGH
 714 0
 715 PARAMETER_UNKNOWN
 716 DEF
 717 C8_HIGH
 718 0
 719 PARAMETER_UNKNOWN
 720 DEF
 721 C9_HIGH
 722 0
 723 PARAMETER_UNKNOWN
 724 DEF
 725 C0_LOW
 726 0
 727 PARAMETER_UNKNOWN
 728 DEF
 729 C1_LOW
 730 0
 731 PARAMETER_UNKNOWN
 732 DEF
 733 C2_LOW
 734 0
 735 PARAMETER_UNKNOWN
 736 DEF
 737 C3_LOW
 738 0
 739 PARAMETER_UNKNOWN
 740 DEF
 741 C4_LOW
 742 0
 743 PARAMETER_UNKNOWN
 744 DEF
 745 C5_LOW
 746 0
 747 PARAMETER_UNKNOWN
 748 DEF
 749 C6_LOW
 750 0
 751 PARAMETER_UNKNOWN
 752 DEF
 753 C7_LOW
 754 0
 755 PARAMETER_UNKNOWN
 756 DEF
 757 C8_LOW
 758 0
 759 PARAMETER_UNKNOWN
 760 DEF
 761 C9_LOW
 762 0
 763 PARAMETER_UNKNOWN
 764 DEF
 765 C0_INITIAL
 766 0
 767 PARAMETER_UNKNOWN
 768 DEF
 769 C1_INITIAL
 770 0
 771 PARAMETER_UNKNOWN
 772 DEF
 773 C2_INITIAL
 774 0
 775 PARAMETER_UNKNOWN
 776 DEF
 777 C3_INITIAL
 778 0
 779 PARAMETER_UNKNOWN
 780 DEF
 781 C4_INITIAL
 782 0
 783 PARAMETER_UNKNOWN
 784 DEF
 785 C5_INITIAL
 786 0
 787 PARAMETER_UNKNOWN
 788 DEF
 789 C6_INITIAL
 790 0
 791 PARAMETER_UNKNOWN
 792 DEF
 793 C7_INITIAL
 794 0
 795 PARAMETER_UNKNOWN
 796 DEF
 797 C8_INITIAL
 798 0
 799 PARAMETER_UNKNOWN
 800 DEF
 801 C9_INITIAL
 802 0
 803 PARAMETER_UNKNOWN
 804 DEF
 805 C0_MODE
 806 BYPASS
 807 PARAMETER_UNKNOWN
 808 DEF
 809 C1_MODE
 810 BYPASS
 811 PARAMETER_UNKNOWN
 812 DEF
 813 C2_MODE
 814 BYPASS
 815 PARAMETER_UNKNOWN
 816 DEF
 817 C3_MODE
 818 BYPASS
 819 PARAMETER_UNKNOWN
 820 DEF
 821 C4_MODE
 822 BYPASS
 823 PARAMETER_UNKNOWN
 824 DEF
 825 C5_MODE
 826 BYPASS
 827 PARAMETER_UNKNOWN
 828 DEF
 829 C6_MODE
 830 BYPASS
 831 PARAMETER_UNKNOWN
 832 DEF
 833 C7_MODE
 834 BYPASS
 835 PARAMETER_UNKNOWN
 836 DEF
 837 C8_MODE
 838 BYPASS
 839 PARAMETER_UNKNOWN
 840 DEF
 841 C9_MODE
 842 BYPASS
 843 PARAMETER_UNKNOWN
 844 DEF
 845 C0_PH
 846 0
 847 PARAMETER_UNKNOWN
 848 DEF
 849 C1_PH
 850 0
 851 PARAMETER_UNKNOWN
 852 DEF
 853 C2_PH
 854 0
 855 PARAMETER_UNKNOWN
 856 DEF
 857 C3_PH
 858 0
 859 PARAMETER_UNKNOWN
 860 DEF
 861 C4_PH
 862 0
 863 PARAMETER_UNKNOWN
 864 DEF
 865 C5_PH
 866 0
 867 PARAMETER_UNKNOWN
 868 DEF
 869 C6_PH
 870 0
 871 PARAMETER_UNKNOWN
 872 DEF
 873 C7_PH
 874 0
 875 PARAMETER_UNKNOWN
 876 DEF
 877 C8_PH
 878 0
 879 PARAMETER_UNKNOWN
 880 DEF
 881 C9_PH
 882 0
 883 PARAMETER_UNKNOWN
 884 DEF
 885 L0_HIGH
 886 1
 887 PARAMETER_UNKNOWN
 888 DEF
 889 L1_HIGH
 890 1
 891 PARAMETER_UNKNOWN
 892 DEF
 893 G0_HIGH
 894 1
 895 PARAMETER_UNKNOWN
 896 DEF
 897 G1_HIGH
 898 1
 899 PARAMETER_UNKNOWN
 900 DEF
 901 G2_HIGH
 902 1
 903 PARAMETER_UNKNOWN
 904 DEF
 905 G3_HIGH
 906 1
 907 PARAMETER_UNKNOWN
 908 DEF
 909 E0_HIGH
 910 1
 911 PARAMETER_UNKNOWN
 912 DEF
 913 E1_HIGH
 914 1
 915 PARAMETER_UNKNOWN
 916 DEF
 917 E2_HIGH
 918 1
 919 PARAMETER_UNKNOWN
 920 DEF
 921 E3_HIGH
 922 1
 923 PARAMETER_UNKNOWN
 924 DEF
 925 L0_LOW
 926 1
 927 PARAMETER_UNKNOWN
 928 DEF
 929 L1_LOW
 930 1
 931 PARAMETER_UNKNOWN
 932 DEF
 933 G0_LOW
 934 1
 935 PARAMETER_UNKNOWN
 936 DEF
 937 G1_LOW
 938 1
 939 PARAMETER_UNKNOWN
 940 DEF
 941 G2_LOW
 942 1
 943 PARAMETER_UNKNOWN
 944 DEF
 945 G3_LOW
 946 1
 947 PARAMETER_UNKNOWN
 948 DEF
 949 E0_LOW
 950 1
 951 PARAMETER_UNKNOWN
 952 DEF
 953 E1_LOW
 954 1
 955 PARAMETER_UNKNOWN
 956 DEF
 957 E2_LOW
 958 1
 959 PARAMETER_UNKNOWN
 960 DEF
 961 E3_LOW
 962 1
 963 PARAMETER_UNKNOWN
 964 DEF
 965 L0_INITIAL
 966 1
 967 PARAMETER_UNKNOWN
 968 DEF
 969 L1_INITIAL
 970 1
 971 PARAMETER_UNKNOWN
 972 DEF
 973 G0_INITIAL
 974 1
 975 PARAMETER_UNKNOWN
 976 DEF
 977 G1_INITIAL
 978 1
 979 PARAMETER_UNKNOWN
 980 DEF
 981 G2_INITIAL
 982 1
 983 PARAMETER_UNKNOWN
 984 DEF
 985 G3_INITIAL
 986 1
 987 PARAMETER_UNKNOWN
 988 DEF
 989 E0_INITIAL
 990 1
 991 PARAMETER_UNKNOWN
 992 DEF
 993 E1_INITIAL
 994 1
 995 PARAMETER_UNKNOWN
 996 DEF
 997 E2_INITIAL
 998 1
 999 PARAMETER_UNKNOWN
1000 DEF
1001 E3_INITIAL
1002 1
1003 PARAMETER_UNKNOWN
1004 DEF
1005 L0_MODE
1006 BYPASS
1007 PARAMETER_UNKNOWN
1008 DEF
1009 L1_MODE
1010 BYPASS
1011 PARAMETER_UNKNOWN
1012 DEF
1013 G0_MODE
1014 BYPASS
1015 PARAMETER_UNKNOWN
1016 DEF
1017 G1_MODE
1018 BYPASS
1019 PARAMETER_UNKNOWN
1020 DEF
1021 G2_MODE
1022 BYPASS
1023 PARAMETER_UNKNOWN
1024 DEF
1025 G3_MODE
1026 BYPASS
1027 PARAMETER_UNKNOWN
1028 DEF
1029 E0_MODE
1030 BYPASS
1031 PARAMETER_UNKNOWN
1032 DEF
1033 E1_MODE
1034 BYPASS
1035 PARAMETER_UNKNOWN
1036 DEF
1037 E2_MODE
1038 BYPASS
1039 PARAMETER_UNKNOWN
1040 DEF
1041 E3_MODE
1042 BYPASS
1043 PARAMETER_UNKNOWN
1044 DEF
1045 L0_PH
1046 0
1047 PARAMETER_UNKNOWN
1048 DEF
1049 L1_PH
1050 0
1051 PARAMETER_UNKNOWN
1052 DEF
1053 G0_PH
1054 0
1055 PARAMETER_UNKNOWN
1056 DEF
1057 G1_PH
1058 0
1059 PARAMETER_UNKNOWN
1060 DEF
1061 G2_PH
1062 0
1063 PARAMETER_UNKNOWN
1064 DEF
1065 G3_PH
1066 0
1067 PARAMETER_UNKNOWN
1068 DEF
1069 E0_PH
1070 0
1071 PARAMETER_UNKNOWN
1072 DEF
1073 E1_PH
1074 0
1075 PARAMETER_UNKNOWN
1076 DEF
1077 E2_PH
1078 0
1079 PARAMETER_UNKNOWN
1080 DEF
1081 E3_PH
1082 0
1083 PARAMETER_UNKNOWN
1084 DEF
1085 M_PH
1086 0
1087 PARAMETER_UNKNOWN
1088 DEF
1089 C1_USE_CASC_IN
1090 OFF
1091 PARAMETER_UNKNOWN
1092 DEF
1093 C2_USE_CASC_IN
1094 OFF
1095 PARAMETER_UNKNOWN
1096 DEF
1097 C3_USE_CASC_IN
1098 OFF
1099 PARAMETER_UNKNOWN
1100 DEF
1101 C4_USE_CASC_IN
1102 OFF
1103 PARAMETER_UNKNOWN
1104 DEF
1105 C5_USE_CASC_IN
1106 OFF
1107 PARAMETER_UNKNOWN
1108 DEF
1109 C6_USE_CASC_IN
1110 OFF
1111 PARAMETER_UNKNOWN
1112 DEF
1113 C7_USE_CASC_IN
1114 OFF
1115 PARAMETER_UNKNOWN
1116 DEF
1117 C8_USE_CASC_IN
1118 OFF
1119 PARAMETER_UNKNOWN
1120 DEF
1121 C9_USE_CASC_IN
1122 OFF
1123 PARAMETER_UNKNOWN
1124 DEF
1125 CLK0_COUNTER
1126 G0
1127 PARAMETER_UNKNOWN
1128 DEF
1129 CLK1_COUNTER
1130 G0
1131 PARAMETER_UNKNOWN
1132 DEF
1133 CLK2_COUNTER
1134 G0
1135 PARAMETER_UNKNOWN
1136 DEF
1137 CLK3_COUNTER
1138 G0
1139 PARAMETER_UNKNOWN
1140 DEF
1141 CLK4_COUNTER
1142 G0
1143 PARAMETER_UNKNOWN
1144 DEF
1145 CLK5_COUNTER
1146 G0
1147 PARAMETER_UNKNOWN
1148 DEF
1149 CLK6_COUNTER
1150 E0
1151 PARAMETER_UNKNOWN
1152 DEF
1153 CLK7_COUNTER
1154 E1
1155 PARAMETER_UNKNOWN
1156 DEF
1157 CLK8_COUNTER
1158 E2
1159 PARAMETER_UNKNOWN
1160 DEF
1161 CLK9_COUNTER
1162 E3
1163 PARAMETER_UNKNOWN
1164 DEF
1165 L0_TIME_DELAY
1166 0
1167 PARAMETER_UNKNOWN
1168 DEF
1169 L1_TIME_DELAY
1170 0
1171 PARAMETER_UNKNOWN
1172 DEF
1173 G0_TIME_DELAY
1174 0
1175 PARAMETER_UNKNOWN
1176 DEF
1177 G1_TIME_DELAY
1178 0
1179 PARAMETER_UNKNOWN
1180 DEF
1181 G2_TIME_DELAY
1182 0
1183 PARAMETER_UNKNOWN
1184 DEF
1185 G3_TIME_DELAY
1186 0
1187 PARAMETER_UNKNOWN
1188 DEF
1189 E0_TIME_DELAY
1190 0
1191 PARAMETER_UNKNOWN
1192 DEF
1193 E1_TIME_DELAY
1194 0
1195 PARAMETER_UNKNOWN
1196 DEF
1197 E2_TIME_DELAY
1198 0
1199 PARAMETER_UNKNOWN
1200 DEF
1201 E3_TIME_DELAY
1202 0
1203 PARAMETER_UNKNOWN
1204 DEF
1205 M_TIME_DELAY
1206 0
1207 PARAMETER_UNKNOWN
1208 DEF
1209 N_TIME_DELAY
1210 0
1211 PARAMETER_UNKNOWN
1212 DEF
1213 EXTCLK3_COUNTER
1214 E3
1215 PARAMETER_UNKNOWN
1216 DEF
1217 EXTCLK2_COUNTER
1218 E2
1219 PARAMETER_UNKNOWN
1220 DEF
1221 EXTCLK1_COUNTER
1222 E1
1223 PARAMETER_UNKNOWN
1224 DEF
1225 EXTCLK0_COUNTER
1226 E0
1227 PARAMETER_UNKNOWN
1228 DEF
1229 ENABLE0_COUNTER
1230 L0
1231 PARAMETER_UNKNOWN
1232 DEF
1233 ENABLE1_COUNTER
1234 L0
1235 PARAMETER_UNKNOWN
1236 DEF
1237 CHARGE_PUMP_CURRENT
1238 2
1239 PARAMETER_UNKNOWN
1240 DEF
1241 LOOP_FILTER_R
1242  1.000000
1243 PARAMETER_UNKNOWN
1244 DEF
1245 LOOP_FILTER_C
1246 5
1247 PARAMETER_UNKNOWN
1248 DEF
1249 CHARGE_PUMP_CURRENT_BITS
1250 9999
1251 PARAMETER_UNKNOWN
1252 DEF
1253 LOOP_FILTER_R_BITS
1254 9999
1255 PARAMETER_UNKNOWN
1256 DEF
1257 LOOP_FILTER_C_BITS
1258 9999
1259 PARAMETER_UNKNOWN
1260 DEF
1261 VCO_POST_SCALE
1262 0
1263 PARAMETER_UNKNOWN
1264 DEF
1265 CLK2_OUTPUT_FREQUENCY
1266 0
1267 PARAMETER_UNKNOWN
1268 DEF
1269 CLK1_OUTPUT_FREQUENCY
1270 0
1271 PARAMETER_UNKNOWN
1272 DEF
1273 CLK0_OUTPUT_FREQUENCY
1274 0
1275 PARAMETER_UNKNOWN
1276 DEF
1277 INTENDED_DEVICE_FAMILY
1278 Stratix
1279 PARAMETER_UNKNOWN
1280 USR
1281 PORT_CLKENA0
1282 PORT_CONNECTIVITY
1283 PARAMETER_UNKNOWN
1284 DEF
1285 PORT_CLKENA1
1286 PORT_CONNECTIVITY
1287 PARAMETER_UNKNOWN
1288 DEF
1289 PORT_CLKENA2
1290 PORT_CONNECTIVITY
1291 PARAMETER_UNKNOWN
1292 DEF
1293 PORT_CLKENA3
1294 PORT_CONNECTIVITY
1295 PARAMETER_UNKNOWN
1296 DEF
1297 PORT_CLKENA4
1298 PORT_CONNECTIVITY
1299 PARAMETER_UNKNOWN
1300 DEF
1301 PORT_CLKENA5
1302 PORT_CONNECTIVITY
1303 PARAMETER_UNKNOWN
1304 DEF
1305 PORT_EXTCLKENA0
1306 PORT_CONNECTIVITY
1307 PARAMETER_UNKNOWN
1308 DEF
1309 PORT_EXTCLKENA1
1310 PORT_CONNECTIVITY
1311 PARAMETER_UNKNOWN
1312 DEF
1313 PORT_EXTCLKENA2
1314 PORT_CONNECTIVITY
1315 PARAMETER_UNKNOWN
1316 DEF
1317 PORT_EXTCLKENA3
1318 PORT_CONNECTIVITY
1319 PARAMETER_UNKNOWN
1320 DEF
1321 PORT_EXTCLK0
1322 PORT_CONNECTIVITY
1323 PARAMETER_UNKNOWN
1324 DEF
1325 PORT_EXTCLK1
1326 PORT_CONNECTIVITY
1327 PARAMETER_UNKNOWN
1328 DEF
1329 PORT_EXTCLK2
1330 PORT_CONNECTIVITY
1331 PARAMETER_UNKNOWN
1332 DEF
1333 PORT_EXTCLK3
1334 PORT_CONNECTIVITY
1335 PARAMETER_UNKNOWN
1336 DEF
1337 PORT_CLKBAD0
1338 PORT_CONNECTIVITY
1339 PARAMETER_UNKNOWN
1340 DEF
1341 PORT_CLKBAD1
1342 PORT_CONNECTIVITY
1343 PARAMETER_UNKNOWN
1344 DEF
1345 PORT_CLK0
1346 PORT_CONNECTIVITY
1347 PARAMETER_UNKNOWN
1348 DEF
1349 PORT_CLK1
1350 PORT_CONNECTIVITY
1351 PARAMETER_UNKNOWN
1352 DEF
1353 PORT_CLK2
1354 PORT_CONNECTIVITY
1355 PARAMETER_UNKNOWN
1356 DEF
1357 PORT_CLK3
1358 PORT_CONNECTIVITY
1359 PARAMETER_UNKNOWN
1360 DEF
1361 PORT_CLK4
1362 PORT_CONNECTIVITY
1363 PARAMETER_UNKNOWN
1364 DEF
1365 PORT_CLK5
1366 PORT_CONNECTIVITY
1367 PARAMETER_UNKNOWN
1368 DEF
1369 PORT_CLK6
1370 PORT_UNUSED
1371 PARAMETER_UNKNOWN
1372 DEF
1373 PORT_CLK7
1374 PORT_UNUSED
1375 PARAMETER_UNKNOWN
1376 DEF
1377 PORT_CLK8
1378 PORT_UNUSED
1379 PARAMETER_UNKNOWN
1380 DEF
1381 PORT_CLK9
1382 PORT_UNUSED
1383 PARAMETER_UNKNOWN
1384 DEF
1385 PORT_SCANDATA
1386 PORT_CONNECTIVITY
1387 PARAMETER_UNKNOWN
1388 DEF
1389 PORT_SCANDATAOUT
1390 PORT_CONNECTIVITY
1391 PARAMETER_UNKNOWN
1392 DEF
1393 PORT_SCANDONE
1394 PORT_CONNECTIVITY
1395 PARAMETER_UNKNOWN
1396 DEF
1397 PORT_SCLKOUT1
1398 PORT_CONNECTIVITY
1399 PARAMETER_UNKNOWN
1400 DEF
1401 PORT_SCLKOUT0
1402 PORT_CONNECTIVITY
1403 PARAMETER_UNKNOWN
1404 DEF
1405 PORT_ACTIVECLOCK
1406 PORT_CONNECTIVITY
1407 PARAMETER_UNKNOWN
1408 DEF
1409 PORT_CLKLOSS
1410 PORT_CONNECTIVITY
1411 PARAMETER_UNKNOWN
1412 DEF
1413 PORT_INCLK1
1414 PORT_CONNECTIVITY
1415 PARAMETER_UNKNOWN
1416 DEF
1417 PORT_INCLK0
1418 PORT_CONNECTIVITY
1419 PARAMETER_UNKNOWN
1420 DEF
1421 PORT_FBIN
1422 PORT_CONNECTIVITY
1423 PARAMETER_UNKNOWN
1424 DEF
1425 PORT_PLLENA
1426 PORT_CONNECTIVITY
1427 PARAMETER_UNKNOWN
1428 DEF
1429 PORT_CLKSWITCH
1430 PORT_CONNECTIVITY
1431 PARAMETER_UNKNOWN
1432 DEF
1433 PORT_ARESET
1434 PORT_CONNECTIVITY
1435 PARAMETER_UNKNOWN
1436 DEF
1437 PORT_PFDENA
1438 PORT_CONNECTIVITY
1439 PARAMETER_UNKNOWN
1440 DEF
1441 PORT_SCANCLK
1442 PORT_CONNECTIVITY
1443 PARAMETER_UNKNOWN
1444 DEF
1445 PORT_SCANACLR
1446 PORT_CONNECTIVITY
1447 PARAMETER_UNKNOWN
1448 DEF
1449 PORT_SCANREAD
1450 PORT_CONNECTIVITY
1451 PARAMETER_UNKNOWN
1452 DEF
1453 PORT_SCANWRITE
1454 PORT_CONNECTIVITY
1455 PARAMETER_UNKNOWN
1456 DEF
1457 PORT_ENABLE0
1458 PORT_CONNECTIVITY
1459 PARAMETER_UNKNOWN
1460 DEF
1461 PORT_ENABLE1
1462 PORT_CONNECTIVITY
1463 PARAMETER_UNKNOWN
1464 DEF
1465 PORT_LOCKED
1466 PORT_CONNECTIVITY
1467 PARAMETER_UNKNOWN
1468 DEF
1469 PORT_CONFIGUPDATE
1470 PORT_CONNECTIVITY
1471 PARAMETER_UNKNOWN
1472 DEF
1473 PORT_FBOUT
1474 PORT_CONNECTIVITY
1475 PARAMETER_UNKNOWN
1476 DEF
1477 PORT_PHASEDONE
1478 PORT_CONNECTIVITY
1479 PARAMETER_UNKNOWN
1480 DEF
1481 PORT_PHASESTEP
1482 PORT_CONNECTIVITY
1483 PARAMETER_UNKNOWN
1484 DEF
1485 PORT_PHASEUPDOWN
1486 PORT_CONNECTIVITY
1487 PARAMETER_UNKNOWN
1488 DEF
1489 PORT_SCANCLKENA
1490 PORT_CONNECTIVITY
1491 PARAMETER_UNKNOWN
1492 DEF
1493 PORT_PHASECOUNTERSELECT
1494 PORT_CONNECTIVITY
1495 PARAMETER_UNKNOWN
1496 DEF
1497 PORT_VCOOVERRANGE
1498 PORT_CONNECTIVITY
1499 PARAMETER_UNKNOWN
1500 DEF
1501 PORT_VCOUNDERRANGE
1502 PORT_CONNECTIVITY
1503 PARAMETER_UNKNOWN
1504 DEF
1505 M_TEST_SOURCE
1506 5
1507 PARAMETER_UNKNOWN
1508 DEF
1509 C0_TEST_SOURCE
1510 5
1511 PARAMETER_UNKNOWN
1512 DEF
1513 C1_TEST_SOURCE
1514 5
1515 PARAMETER_UNKNOWN
1516 DEF
1517 C2_TEST_SOURCE
1518 5
1519 PARAMETER_UNKNOWN
1520 DEF
1521 C3_TEST_SOURCE
1522 5
1523 PARAMETER_UNKNOWN
1524 DEF
1525 C4_TEST_SOURCE
1526 5
1527 PARAMETER_UNKNOWN
1528 DEF
1529 C5_TEST_SOURCE
1530 5
1531 PARAMETER_UNKNOWN
1532 DEF
1533 C6_TEST_SOURCE
1534 5
1535 PARAMETER_UNKNOWN
1536 DEF
1537 C7_TEST_SOURCE
1538 5
1539 PARAMETER_UNKNOWN
1540 DEF
1541 C8_TEST_SOURCE
1542 5
1543 PARAMETER_UNKNOWN
1544 DEF
1545 C9_TEST_SOURCE
1546 5
1547 PARAMETER_UNKNOWN
1548 DEF
1549 CBXI_PARAMETER
1550 NOTHING
1551 PARAMETER_UNKNOWN
1552 DEF
1553 VCO_FREQUENCY_CONTROL
1554 AUTO
1555 PARAMETER_UNKNOWN
1556 DEF
1557 VCO_PHASE_SHIFT_STEP
1558 0
1559 PARAMETER_UNKNOWN
1560 DEF
1561 WIDTH_CLOCK
1562 6
1563 PARAMETER_UNKNOWN
1564 DEF
1565 WIDTH_PHASECOUNTERSELECT
1566 4
1567 PARAMETER_UNKNOWN
1568 DEF
1569 USING_FBMIMICBIDIR_PORT
1570 OFF
1571 PARAMETER_UNKNOWN
1572 DEF
1573 DEVICE_FAMILY
1574 Stratix
1575 PARAMETER_UNKNOWN
1576 USR
1577 SCAN_CHAIN_MIF_FILE
1578 UNUSED
1579 PARAMETER_UNKNOWN
1580 DEF
1581 SIM_GATE_LOCK_DEVICE_BEHAVIOR
1582 OFF
1583 PARAMETER_UNKNOWN
1584 DEF
1585 AUTO_CARRY_CHAINS
1586 ON
1587 AUTO_CARRY
1588 USR
1589 IGNORE_CARRY_BUFFERS
1590 OFF
1591 IGNORE_CARRY
1592 USR
1593 AUTO_CASCADE_CHAINS
1594 ON
1595 AUTO_CASCADE
1596 USR
1597 IGNORE_CASCADE_BUFFERS
1598 OFF
1599 IGNORE_CASCADE
1600 USR
1601 }
1602 # used_port {
1603 inclk0
1604 -1
1605 3
1606 clk0
1607 -1
1608 3
1609 inclk1
1610 -1
1611 1
1612 extclkena3
1613 -1
1614 1
1615 extclkena2
1616 -1
1617 1
1618 extclkena1
1619 -1
1620 1
1621 extclkena0
1622 -1
1623 1
1624 clkena5
1625 -1
1626 1
1627 clkena4
1628 -1
1629 1
1630 clkena3
1631 -1
1632 1
1633 clkena2
1634 -1
1635 1
1636 clkena1
1637 -1
1638 1
1639 areset
1640 -1
1641 1
1642 pllena
1643 -1
1644 2
1645 clkena0
1646 -1
1647 2
1648 }
1649 # include_file {
1650 |opt|quartus|quartus|libraries|megafunctions|cycloneii_pll.inc
1651 39a0d9d1237d1db39c848c3f9faffc
1652 |opt|quartus|quartus|libraries|megafunctions|stratix_pll.inc
1653 5f8211898149ceae8264a0ea5036254f
1654 |opt|quartus|quartus|libraries|megafunctions|aglobal90.inc
1655 99832fdf63412df51d7531202d74e75
1656 |opt|quartus|quartus|libraries|megafunctions|stratixii_pll.inc
1657 6d1985e16ab5f59a1fd6b0ae20978a4e
1658 }
1659 # hierarchies {
1660 vpll:inst1|altpll:altpll_component
1661 }
1662 # lmf
1663 |opt|quartus|quartus|lmf|synplcty.lmf
1664 3057712873b497a38b70a3917f30cc38
1665 # macro_sequence
1666
1667 # end
1668 # complete
1669 \r