From dc0bdbab2df7ff8c89b0e1325a60ce994ee6bf43 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 14 Feb 2012 10:50:11 -0700 Subject: [PATCH] Torpedo mainboard changes to fix warnings. Fixes the warnings generated in the torpedo mainboard build. Most of these changes are similar to fixes already implemented in the persimmon mainboard. Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5 Signed-off-by: Martin L Roth Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/634 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/amd/torpedo/Oem.h | 5 +-- src/mainboard/amd/torpedo/acpi_tables.c | 12 ++++--- src/mainboard/amd/torpedo/fadt.c | 40 +++++++++++++----------- src/mainboard/amd/torpedo/gpio.c | 5 ++- src/mainboard/amd/torpedo/irq_tables.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 20 ++++++------ src/mainboard/amd/torpedo/mptable.c | 20 ++++++------ src/mainboard/amd/torpedo/platform_cfg.h | 3 ++ src/mainboard/amd/torpedo/romstage.c | 1 + 9 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index a7109dc38..037ce94ef 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,8 +16,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define BIOS_SIZE 0x04 //04 - 1MB +#ifndef BIOS_SIZE + #define BIOS_SIZE 0x04 //04 - 1MB +#endif #define LEGACY_FREE 0x00 #if CONFIG_ONBOARD_USB30 == 0 #define XHCI_SUPPORT 0x01 diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 4710b57c2..3ba789d69 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -25,9 +25,9 @@ #include #include #include -#include - #include "agesawrapper.h" +#include +#include #define DUMP_ACPI_TABLES 0 extern u32 apicid_sb900; @@ -110,7 +110,9 @@ unsigned long write_acpi_tables(unsigned long start) unsigned long current; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; +#if 0 // Don't need HPET table. acpi_hpet_t *hpet; +#endif acpi_madt_t *madt; acpi_srat_t *srat; acpi_slit_t *slit; @@ -164,7 +166,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { - memcpy(current, srat, srat->header.length); + memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *) current; //acpi_create_srat(srat); current += srat->header.length; @@ -176,7 +178,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { - memcpy(current, slit, slit->header.length); + memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *) current; //acpi_create_slit(slit); current += slit->header.length; @@ -188,7 +190,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; } diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 5701dabc2..a4cb1b91e 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -28,7 +28,7 @@ #include #include #include -//#include "../../../southbridge/amd/sb900/sb900.h" +#include "SbPlatform.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ @@ -44,6 +44,7 @@ #define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { + u16 val = 0; acpi_header_t *header = &(fadt->header); pm_base &= 0xFFFF; @@ -71,29 +72,30 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ + val = ACPI_PM2_CNT_BLK; + WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); - pm_iowrite(0x6E, ACPI_PM2_CNT_BLK & 0xFF); - pm_iowrite(0x6F, ACPI_PM2_CNT_BLK >> 8); + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn */ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 2633fb578..3e49cb138 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -23,9 +23,9 @@ */ #include "Filecode.h" -#include "Hudson-2.h" -#include "AmdSbLib.h" +#include "SbPlatform.h" #include "gpio.h" +#include "vendorcode/amd/cimx/sb900/AmdSbLib.h" #define FILECODE UNASSIGNED_FILE_FILECODE @@ -62,7 +62,6 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - void gpioEarlyInit (void); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index f61f1e896..595e09b25 100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c @@ -23,7 +23,7 @@ #include #include #include -//#include +#include diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 288798fdb..215215393 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -31,6 +31,9 @@ #define ONE_MB 0x100000 //#define SMBUS_IO_BASE 0x6000 +void set_pcie_reset(void); +void set_pcie_dereset(void); + /** * TODO * SB CIMx callback @@ -54,7 +57,7 @@ uint64_t uma_memory_base, uma_memory_size; *************************************************/ static void torpedo_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Torpedo Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -79,14 +82,13 @@ static void torpedo_enable(device_t dev) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo; - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if (sys_mem >= 2048 * ONE_MB) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ + } else if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", @@ -114,6 +116,6 @@ int add_mainboard_resources(struct lb_memory *mem) return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TORPEDO Mainboard") + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = torpedo_enable, }; diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 2e171a137..97db2b9a9 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include "SbPlatform.h" //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS @@ -113,15 +115,11 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ - device_t dev; u32 dword; u8 byte; - dword = 0; - dword = pm_ioread(0x34) & 0xF0; - dword |= (pm_ioread(0x35) & 0xFF) << 8; - dword |= (pm_ioread(0x36) & 0xFF) << 16; - dword |= (pm_ioread(0x37) & 0xFF) << 24; + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); @@ -166,8 +164,12 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -214,9 +216,9 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15); - PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14); + PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12); + PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13); + PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 532d83f0a..d97d0344d 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -1237,4 +1237,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); */ u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); +// definition for function in gpio.c +void gpioEarlyInit (void); + #endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 2e1d8fcb8..74365e672 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -37,6 +37,7 @@ #include "SbEarly.h" #include "SbPlatform.h" #include +#include "platform_cfg.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -- 2.25.1