From 976fa8800e04817b6e18ee47a1d2cd3dd73be446 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Fri, 6 Apr 2012 14:27:33 +0200 Subject: [PATCH] m5a99x-evo: grml, strange romstage ld warning... dunno why :/ /home/lewurm/cb/repo/util/crossgcc/xgcc/lib/gcc/i386-elf/4.6.2/../../../../i386-elf/bin/ld: Do not use global variables in romstage collect2: ld returned 1 exit status make: *** [build/coreboot.romstage] Error 1 --- src/mainboard/asus/m5a99x-evo/Kconfig | 2 +- src/mainboard/asus/m5a99x-evo/Makefile.inc | 3 +- src/mainboard/asus/m5a99x-evo/platform_cfg.h | 1195 ++++++++++++++++++ src/mainboard/asus/m5a99x-evo/romstage.c | 10 +- src/southbridge/amd/cimx/sb900/SbPlatform.h | 3 +- src/vendorcode/amd/cimx/sb900/Dispatcher.c | 2 +- 6 files changed, 1205 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/m5a99x-evo/Kconfig b/src/mainboard/asus/m5a99x-evo/Kconfig index b36ab1452..729ae53a0 100644 --- a/src/mainboard/asus/m5a99x-evo/Kconfig +++ b/src/mainboard/asus/m5a99x-evo/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select QRANK_DIMM_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_CIMX_SB900 select SUPERIO_ITE_IT8721F select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/asus/m5a99x-evo/Makefile.inc b/src/mainboard/asus/m5a99x-evo/Makefile.inc index b55a0c74d..f24679cf2 100644 --- a/src/mainboard/asus/m5a99x-evo/Makefile.inc +++ b/src/mainboard/asus/m5a99x-evo/Makefile.inc @@ -2,9 +2,8 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 + AGESA_ROOT ?= src/vendorcode/amd/agesa/f10 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c AGESA_INC := -I$(AGESA_ROOT)/ \ -I$(AGESA_ROOT)/Include \ diff --git a/src/mainboard/asus/m5a99x-evo/platform_cfg.h b/src/mainboard/asus/m5a99x-evo/platform_cfg.h index 003fdb0b3..1d856bffd 100644 --- a/src/mainboard/asus/m5a99x-evo/platform_cfg.h +++ b/src/mainboard/asus/m5a99x-evo/platform_cfg.h @@ -90,11 +90,13 @@ */ #define PCI_CLOCK_CTRL 0x1F +#if 0 /** * @def SATA_CONTROLLER * @breif INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED +#endif /** * @def SATA_MODE @@ -159,6 +161,7 @@ */ #define AZALIA_CONTROLLER AZALIA_AUTO +#if 0 /** * @def AZALIA_PIN_CONFIG * @brief @@ -166,6 +169,7 @@ * 1 - enable */ #define AZALIA_PIN_CONFIG 1 +#endif /** * @def AZALIA_SDIN_PIN @@ -230,4 +234,1195 @@ */ #define SIO_HWM_BASE_ADDRESS 0x290 + +/** + * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE + * @li 1 - Legacy free enable + * @li 0 - Legacy free disable + */ +#ifndef SBCIMx_LEGACY_FREE + #define SBCIMx_LEGACY_FREE 0 +#endif + +/** + * @section SpiSpeed + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef SBCIMX_SPI_SPEED + #define SBCIMX_SPI_SPEED 0 +#endif + +/** + * @section SpiFastSpeed + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef SBCIMX_SPI_FASTSPEED + #define SBCIMX_SPI_FASTSPEED 0 +#endif + +/** + * @section SpiMode + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef SBCIMX_SPI_MODE + #define SBCIMX_SPI_MODE 0 +#endif + +/** + * @section SpiBurstWrite + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef SBCIMX_SPI_BURST_WRITE + #define SBCIMX_SPI_BURST_WRITE 0 +#endif + +/** + * @section INCHIP_EC_KBD INCHIP_EC_KBD + * @li 0 - Use SIO PS/2 function. + * @li 1 - Use EC PS/2 function. + */ +#ifndef INCHIP_EC_KBD + #define INCHIP_EC_KBD 0 +#endif + +/** + * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10 + * @li 0 - EC controller NOT support Channel10 + * @li 1 - EC controller support Channel10. + */ +#ifndef INCHIP_EC_CHANNEL10 + #define INCHIP_EC_CHANNEL10 1 +#endif + +/** + * @section Smbus0BaseAddress + */ +// #ifndef SMBUS0_BASE_ADDRESS +// #define SMBUS0_BASE_ADDRESS 0xB00 +// #endif + +/** + * @section Smbus1BaseAddress + */ +// #ifndef SMBUS1_BASE_ADDRESS +// #define SMBUS1_BASE_ADDRESS 0xB21 +// #endif + +/** + * @section SioPmeBaseAddress + */ +// #ifndef SIO_PME_BASE_ADDRESS +// #define SIO_PME_BASE_ADDRESS 0xE00 +// #endif + +/** + * @section WatchDogTimerBase + */ +// #ifndef WATCHDOG_TIMER_BASE_ADDRESS +// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 +// #endif + +/** + * @section GecShadowRomBase + */ +#ifndef GEC_ROM_SHADOW_ADDRESS + #define GEC_ROM_SHADOW_ADDRESS 0xFED61000 +#endif + +/** + * @section SpiRomBaseAddress + */ +// #ifndef SPI_BASE_ADDRESS +// #define SPI_BASE_ADDRESS 0xFEC10000 +// #endif + +/** + * @section AcpiPm1EvtBlkAddr + */ +// #ifndef PM1_EVT_BLK_ADDRESS +// #define PM1_EVT_BLK_ADDRESS 0x400 +// #endif + +/** + * @section AcpiPm1CntBlkAddr + */ +// #ifndef PM1_CNT_BLK_ADDRESS +// #define PM1_CNT_BLK_ADDRESS 0x404 +// #endif + +/** + * @section AcpiPmTmrBlkAddr + */ +// #ifndef PM1_TMR_BLK_ADDRESS +// #define PM1_TMR_BLK_ADDRESS 0x408 +// #endif + +/** + * @section CpuControlBlkAddr + */ +// #ifndef CPU_CNT_BLK_ADDRESS +// #define CPU_CNT_BLK_ADDRESS 0x410 +// #endif + +/** + * @section AcpiGpe0BlkAddr + */ +// #ifndef GPE0_BLK_ADDRESS +// #define GPE0_BLK_ADDRESS 0x420 +// #endif + +/** + * @section SmiCmdPortAddr + */ +// #ifndef SMI_CMD_PORT +// #define SMI_CMD_PORT 0xB0 +// #endif + +/** + * @section AcpiPmaCntBlkAddr + */ +// #ifndef ACPI_PMA_CNT_BLK_ADDRESS +// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +// #endif + +/** + * @section SataController + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef INCHIP_SATA_CONTROLLER + #define INCHIP_SATA_CONTROLLER 1 +#endif + +/** + * @section SataIdeCombMdPriSecOpt + * @li 0 - Primary + * @li 1 - Secondary + * Sata Controller set as primary or + * secondary while Combined Mode is enabled + */ +#ifndef SATA_COMBINE_MODE_CHANNEL + #define SATA_COMBINE_MODE_CHANNEL 0 +#endif + +/** + * @section SataSetMaxGen2 + * @li 0 - Disable + * @li 1 - Enable + * SataController Set to Max Gen2 mode + */ +#ifndef SATA_MAX_GEN2_MODE + #define SATA_MAX_GEN2_MODE 0 +#endif + +/** + * @section SataIdeCombinedMode + * @li 0 - Disable + * @li 1 - Enable + * Sata IDE Controller set to Combined Mode + */ +#ifndef SATA_COMBINE_MODE + #define SATA_COMBINE_MODE 0 +#endif + +#define SATA_CLK_RESERVED 9 + +/** + * @section NbSbGen2 + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef NB_SB_GEN2 + #define NB_SB_GEN2 1 +#endif + +/** + * @section SataInternal100Spread + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef INCHIP_SATA_INTERNAL_100_SPREAD + #define INCHIP_SATA_INTERNAL_100_SPREAD 0 +#endif + +/** + * @section Cg2Pll + * @li 0 - Disable + * @li 1 - Enable + */ +#ifndef INCHIP_CG2_PLL + #define INCHIP_CG2_PLL 0 +#endif + + + + +/** + * @section SpreadSpectrum + * @li 0 - Disable + * @li 1 - Enable + * Spread Spectrum function + */ +#define INCHIP_SPREAD_SPECTRUM 1 + +/** + * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG + * + * - Usb Ohci1 Contoller is define at BIT0 + * 0:Disable 1:Enable + * (Bus 0 Dev 18 Func0) + * - Usb Ehci1 Contoller is define at BIT1 + * 0:Disable 1:Enable + * (Bus 0 Dev 18 Func2) + * - Usb Ohci2 Contoller is define at BIT2 + * 0:Disable 1:Enable + * (Bus 0 Dev 19 Func0) + * - Usb Ehci2 Contoller is define at BIT3 + * 0:Disable 1:Enable + * (Bus 0 Dev 19 Func2) + * - Usb Ohci3 Contoller is define at BIT4 + * 0:Disable 1:Enable + * (Bus 0 Dev 22 Func0) + * - Usb Ehci3 Contoller is define at BIT5 + * 0:Disable 1:Enable + * (Bus 0 Dev 22 Func2) + * - Usb Ohci4 Contoller is define at BIT6 + * 0:Disable 1:Enable + * (Bus 0 Dev 20 Func5) + */ +#define INCHIP_USB_CINFIG 0x7F +#define INCHIP_USB_OHCI1_CINFIG 0x01 +#define INCHIP_USB_OHCI2_CINFIG 0x01 +#if CONFIG_ONBOARD_USB30 == 1 +#define INCHIP_USB_OHCI3_CINFIG 0x00 +#else +#define INCHIP_USB_OHCI3_CINFIG 0x01 +#endif +#define INCHIP_USB_OHCI4_CINFIG 0x01 +#define INCHIP_USB_EHCI1_CINFIG 0x01 +#define INCHIP_USB_EHCI2_CINFIG 0x01 +#define INCHIP_USB_EHCI3_CINFIG 0x01 + +/** + * @section INCHIP_SATA_MODE INCHIP_SATA_MODE + * @li 000 - Native IDE mode + * @li 001 - RAID mode + * @li 010 - AHCI mode + * @li 011 - Legacy IDE mode + * @li 100 - IDE->AHCI mode + * @li 101 - AHCI mode as 7804 ID (AMD driver) + * @li 110 - IDE->AHCI mode as 7804 ID (AMD driver) + */ +#define INCHIP_SATA_MODE 0 + +/** + * @section INCHIP_IDE_MODE INCHIP_IDE_MODE + * @li 0 - Legacy IDE mode + * @li 1 - Native IDE mode + * ** DO NOT ALLOW SATA & IDE use same mode ** + */ +#define INCHIP_IDE_MODE 1 + +#define SATA_PORT_MULT_CAP_RESERVED 1 + +/** + * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER + * @li 0 - Auto : Detect Azalia controller automatically. + * @li 1 - Diable : Disable Azalia controller. + * @li 2 - Enable : Enable Azalia controller. + */ +#define INCHIP_AZALIA_CONTROLLER 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG + * @li 0 - disable + * @li 1 - enable + */ +#define INCHIP_AZALIA_PIN_CONFIG 1 + +/** + * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG + * + * SDIN0 is define at BIT0 & BIT1 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + * SDIN2 is define at BIT4 & BIT5 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + * SDIN3 is define at BIT6 & BIT7 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + */ +#define AZALIA_PIN_CONFIG 0x2A + +/** + * @section AzaliaSnoop + * @li 0 - disable + * @li 1 - enable * + */ +#define INCHIP_AZALIA_SNOOP 0x01 + +/** + * @section NCHIP_GEC_CONTROLLER + * @li 0 - Enable * + * @li 1 - Disable + */ +#define INCHIP_GEC_CONTROLLER 0x00 + +/** + * @section SB_HPET_TIMER SB_HPET_TIMER + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_HPET_TIMER 1 + +/** + * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_GPP_CONTROLLER 1 + +/** + * @section GPP_LINK_CONFIG GPP_LINK_CONFIG + * @li 0000 - Port ABCD -> 4:0:0:0 + * @li 0001 - N/A + * @li 0010 - Port ABCD -> 2:2:0:0 + * @li 0011 - Port ABCD -> 2:1:1:0 + * @li 0100 - Port ABCD -> 1:1:1:1 + */ +#define GPP_LINK_CONFIG 4 + +/** + * @section SB_GPP_PORT0 SB_GPP_PORT0 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_GPP_PORT0 1 + +/** + * @section SB_GPP_PORT1 SB_GPP_PORT1 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_GPP_PORT1 1 + +/** + * @section SB_GPP_PORT2 SB_GPP_PORT2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_GPP_PORT2 1 + +/** + * @section SB_GPP_PORT3 SB_GPP_PORT3 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SB_GPP_PORT3 1 + +/** + * @section SB_IR_CONTROLLER + * @li 00 - disable + * @li 01 - Rx and Tx0 + * @li 10 - Rx and Tx1 + * @li 11 - Rx and both Tx0,Tx1 + */ +#define SB_IR_CONTROLLER 3 + +/** + * @section INCHIP_USB_PHY_POWER_DOWN + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_USB_PHY_POWER_DOWN 0 + +/** + * @section INCHIP_NATIVE_PCIE_SUPPOORT + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_NATIVE_PCIE_SUPPOORT 1 + +/** + * @section INCHIP_NB_SB_GEN2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_NB_SB_GEN2 1 + +/** + * @section INCHIP_GPP_GEN2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_GEN2 1 + +/** + * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1 + +/** + * @section INCHIP_GEC_PHY_STATUS + * @li 0 - Gb PHY Mode * + * @li 1 - 100/10 PHY Mode + */ +#define INCHIP_GEC_PHY_STATUS 0 + +/** + * @section INCHIP_GEC_POWER_POLICY + * @li 0 - S3/S5 + * @li 1 - S5 + * @li 2 - S3 + * @li 3 - Never power down * + */ +#define INCHIP_GEC_POWER_POLICY 3 + +/** + * @section INCHIP_GEC_DEBUGBUS + * @li 0 - Disable * + * @li 1 - Enable + */ +#define INCHIP_GEC_DEBUGBUS 0 + +/** + * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE + * @li 0 - Disable * + * @li 1 - Enable + * SataController Set to Max Gen2 mode + */ +#define SATA_MAX_GEN2_MODE 0 + +/** + * @section INCHIP_SATA_AGGR_LINK_PM_CAP + * @li 0 - Disable + * @li 1 - Enable * + * SataController Set to aggressive link PM capability + */ +#define INCHIP_SATA_AGGR_LINK_PM_CAP 0 + +/** + * @section INCHIP_SATA_PORT_MULT_CAP + * @li 0 - Disable + * @li 1 - Enable * + * SataController Set to Port Multiple capability + */ +#define INCHIP_SATA_PORT_MULT_CAP 1 + +/** + * @section INCHIP_SATA_PSC_CAP + * @li 0 - Disable + * @li 1 - Enable * +*/ +#define INCHIP_SATA_PSC_CAP 0 + +/** + * @section INCHIP_SATA_SSC_CAP + * @li 0 - Disable + * @li 1 - Enable * + */ +#define INCHIP_SATA_SSC_CAP 0 + +/** + * @section INCHIP_SATA_CLK_AUTO_OFF + * @li 0 - Disable + * @li 1 - Enable * + */ +#define INCHIP_SATA_CLK_AUTO_OFF 1 + +/** + * @section INCHIP_SATA_FIS_BASE_SW + * @li 0 - Disable + * @li 1 - Enable * + */ +#define INCHIP_SATA_FIS_BASE_SW 1 + +/** + * @section INCHIP_SATA_CCC_SUPPORT + * @li 0 - Disable + * @li 1 - Enable * + */ +#define INCHIP_SATA_CCC_SUPPORT 1 + +/** + * @section INCHIP_SATA_MSI_CAP + * @li 0 - Disable + * @li 1 - Enable * + */ +#define INCHIP_SATA_MSI_CAP 1 + +/** + * @section CIMXSB_SATA_TARGET_8DEVICE_CAP + * @li 0 - Disable * + * @li 1 - Enable + */ +#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0 + +/** + * @section SATA_DISABLE_GENERIC_MODE + * @li 0 - Disable * + * @li 1 - Enable + */ +#define SATA_DISABLE_GENERIC_MODE_CAP 0 + +/** + * @section SATA_AHCI_ENCLOSURE_CAP + * @li 0 - Disable * + * @li 1 - Enable + */ +#define SATA_AHCI_ENCLOSURE_CAP 0 + +/** + * @section SataForceRaid (RISD5 mode) + * @li 0 - Disable * + * @li 1 - Enable + */ +#define INCHIP_SATA_FORCE_RAID5 0 + +/** + * @section SATA_GPIO_0_CAP + * @li 0 - Disable * + * @li 1 - Enable + */ +#define SATA_GPIO_0_CAP 0 + +/** + * @section SATA_GPIO_1_CAP + * @li 0 - Disable * + * @li 1 - Enable + */ +#define SATA_GPIO_1_CAP 0 + +/** + * @section SataPhyPllShutDown + * @li 0 - Disable + * @li 1 - Enable * + */ +#define SATA_PHY_PLL_SHUTDOWN 1 + +/** + * @section ImcEnableOverWrite + * @li 0 - Disable + * @li 1 - Enable + */ +#define IMC_ENABLE_OVER_WRITE 0 + +/** + * @section UsbMsi + * @li 0 - Disable + * @li 1 - Enable + */ +#define USB_MSI 0 + +/** + * @section HdAudioMsi + * @li 0 - Disable + * @li 1 - Enable + */ +#define HDAUDIO_MSI 0 + +/** + * @section LpcMsi + * @li 0 - Disable + * @li 1 - Enable + */ +#define LPC_MSI 0 + +/** + * @section PcibMsi + * @li 0 - Disable + * @li 1 - Enable + */ +#define PCIB_MSI 0 + +/** + * @section AbMsi + * @li 0 - Disable + * @li 1 - Enable + */ +#define AB_MSI 0 + +/** + * @section GecShadowRomBase + * @li 0 - Disable + * @li 1 - Enable * + */ +#define GEC_SHADOWROM_BASE 0xFED61000 + +/** + * @section SataController + * @li 0 - Disable + * @li 1 - Enable * + */ +#define SATA_CONTROLLER 1 + +/** + * @section SataIdeCombMdPriSecOpt + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_IDE_COMBMD_PRISEC_OPT 0 + +/** + * @section SataIdeCombinedMode + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_IDECOMBINED_MODE 0 + +/** + * @section sdConfig + * @li 0 - Disable + * @li 1 - Enable * + */ +#define SB_SD_CONFIG 1 + +/** + * @section sdSpeed + * @li 0 - Disable + * @li 1 - Enable * + */ +#define SB_SD_SPEED 1 + +/** + * @section sdBitwidth + * @li 0 - Disable + * @li 1 - Enable * + */ +#define SB_SD_BITWIDTH 1 + +/** + * @section SataDisUnusedIdePChannel + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_DISUNUSED_IDE_P_CHANNEL 0 + +/** + * @section SataDisUnusedIdeSChannel + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_DISUNUSED_IDE_S_CHANNEL 0 + +/** + * @section IdeDisUnusedIdePChannel + * @li 0 - Disable + * @li 1 - Enable + */ +#define IDE_DISUNUSED_IDE_P_CHANNEL 0 + +/** + * @section IdeDisUnusedIdeSChannel + * @li 0 - Disable + * @li 1 - Enable + */ +#define IDE_DISUNUSED_IDE_S_CHANNEL 0 + +/** + * @section IdeDisUnusedIdeSChannel + * @li 0 - Disable + * @li 1 - Enable + */ + +/** + * @section SataEspPort0 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT0 0 + +/** + * @section SataEspPort1 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT1 0 + +/** + * @section SataEspPort2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT2 0 + +/** + * @section SataEspPort3 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT3 0 + +/** + * @section SataEspPort4 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT4 0 + +/** + * @section SataEspPort5 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT5 0 + +/** + * @section SataEspPort6 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT6 0 + +/** + * @section SataEspPort7 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_ESP_PORT7 0 + +/** + * @section SataPortPower0 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT0 0 + +/** + * @section SataPortPower1 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT1 0 + +/** + * @section SataPortPower2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT2 0 + +/** + * @section SataPortPower3 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT3 0 + +/** + * @section SataPortPower4 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT4 0 + +/** + * @section SataPortPower5 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT5 0 + +/** + * @section SataPortPower6 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT6 0 + +/** + * @section SataPortPower7 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORT_POWER_PORT7 0 + +/** + * @section SataPortMd0 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT0 3 + +/** + * @section SataPortMd1 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT1 3 + +/** + * @section SataPortMd2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT2 3 + +/** + * @section SataPortMd3 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT3 3 + +/** + * @section SataPortMd4 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT4 0 + +/** + * @section SataPortMd5 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT5 0 + +/** + * @section SataPortMd6 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT6 0 + +/** + * @section SataPortMd7 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_PORTMODE_PORT7 0 + +/** + * @section SataHotRemovelEnh0 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT0 0 + +/** + * @section SataHotRemovelEnh1 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT1 0 + +/** + * @section SataHotRemovelEnh2 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT2 0 + +/** + * @section SataHotRemovelEnh3 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT3 0 + +/** + * @section SataHotRemovelEnh4 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT4 0 + +/** + * @section SataHotRemovelEnh5 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT5 0 + +/** + * @section SataHotRemovelEnh6 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT6 0 + +/** + * @section SataHotRemovelEnh7 + * @li 0 - Disable + * @li 1 - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT7 0 + +/** + * @section XhciSwitch + * @li 0 - Disable + * @li 1 - Enable + */ +#if CONFIG_ONBOARD_USB30 == 1 + #define SB_XHCI_SWITCH 0 +#else +#define SB_XHCI_SWITCH 1 +#endif + +/** + * @section FrontPanelDetected + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_FRONT_PANEL_DETECTED 0 + +/** + * @section AnyHT200MhzLink + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_ANY_HT_200MHZ_LINK 0 + +/** + * @section PcibClkStopOverride + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0 + +/** + * @section GppLinkConfig + * @li 0000 - Port ABCD -> 4:0:0:0 + * @li 0001 - N/A + * @li 0010 - Port ABCD -> 2:2:0:0 + * @li 0011 - Port ABCD -> 2:1:1:0 + * @li 0100 - Port ABCD -> 1:1:1:1 + */ +#define INCHIP_GPP_LINK_CONFIG 4 + +/** + * @section GppUnhidePorts + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_UNHIDE_PORTS 0 + +/** + * @section GppPortAspm + * @li 01 - Disabled + * @li 01 - L0s + * @li 10 - L1 + * @li 11 - L0s + L1 + */ +#define INCHIP_GPP_PORT_ASPM 3 + +/** + * @section GppLaneReversal + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_LANEREVERSAL 0 + +/** + * @section AlinkPhyPllPowerDown + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1 + +/** + * @section GppPhyPllPowerDown + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1 + +/** + * @section GppDynamicPowerSaving + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1 + +/** + * @section PcieAER + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_PCIE_AER 0 + +/** + * @section PcieRAS + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_PCIE_RAS 0 + +/** + * @section GppHardwareDowngrade + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_HARDWARE_DOWNGRADE 0 + +/** + * @section GppToggleReset + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_TOGGLE_RESET 0 + +/** + * @section SbPcieOrderRule + * @li 00 - Disable + * @li 01 - Rule 1 + * @li 10 - Rule 2 + */ +#define INCHIP_SB_PCIE_ORDER_RULE 2 + +/** + * @section AcDcMsg + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_ACDC_MSG 0 + +/** + * @section TimerTickTrack + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_TIMER_TICK_TRACK 1 + +/** + * @section ClockInterruptTag + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_CLOCK_INTERRUPT_TAG 1 + +/** + * @section OhciTrafficHanding + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_OHCI_TRAFFIC_HANDING 0 + +/** + * @section EhciTrafficHanding + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_EHCI_TRAFFIC_HANDING 0 + +/** + * @section FusionMsgCMultiCore + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_FUSION_MSGC_MULTICORE 0 + +/** + * @section FusionMsgCStage + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_FUSION_MSGC_STAGE 0 + +/** + * @section ALinkClkGateOff + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_ALINK_CLK_GATE_OFF 0 + +/** + * @section BLinkClkGateOff + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_BLINK_CLK_GATE_OFF 0 + +/** + * @section SlowSpeedABlinkClock + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0 + +/** + * @section AbClockGating + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_AB_CLOCK_GATING 1 + +/** + * @section GppClockGating + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_GPP_CLOCK_GATING 1 + +/** + * @section L1TimerOverwrite + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_L1_TIMER_OVERWRITE 0 + +/** + * @section UmiDynamicSpeedChange + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0 + +/** + * @section SbAlinkGppTxDriverStrength + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0 + +/** + * @section StressResetMode + * @li 0 - Disable + * @li 1 - Enable + */ +#define INCHIP_STRESS_RESET_MODE 0 + +#ifndef SB_PCI_CLOCK_RESERVED + #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F +#endif + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb900_cimx_config(AMDSBCFG *sb_cfg); +void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); + + + #endif diff --git a/src/mainboard/asus/m5a99x-evo/romstage.c b/src/mainboard/asus/m5a99x-evo/romstage.c index 9d8e08ac6..8091f8e59 100644 --- a/src/mainboard/asus/m5a99x-evo/romstage.c +++ b/src/mainboard/asus/m5a99x-evo/romstage.c @@ -47,9 +47,9 @@ #include #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include -#include /* SB OEM constants */ -#include +#include +#include /* SB OEM constants */ +#include #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) @@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init - sb_Poweron_Init(); + sb_poweron_init(); } post_code(0x30); @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); enable_rs780_dev8(); - sb800_clk_output_48Mhz(); + // sb800_clk_output_48Mhz(); it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 3fb45dea6..547009dca 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -59,7 +59,8 @@ typedef union _PCI_ADDR { #include #include "AmdSbLib.h" -#include "Amd.h" +// #include "Amd.h" +#include #include "Hudson-2.h" #include "SbType.h" #include "AcpiLib.h" diff --git a/src/vendorcode/amd/cimx/sb900/Dispatcher.c b/src/vendorcode/amd/cimx/sb900/Dispatcher.c index 152ffc215..9c1d0dd96 100755 --- a/src/vendorcode/amd/cimx/sb900/Dispatcher.c +++ b/src/vendorcode/amd/cimx/sb900/Dispatcher.c @@ -190,7 +190,7 @@ LocateImage ( #ifdef x64 12346789 #else - Result = VerifyImage (Signature, (VOID*) (__int64)ImagePtr); + Result = VerifyImage (Signature, (VOID *) ImagePtr); #endif if ( Result != NULL ) { return Result; -- 2.25.1