From 49ae971333408f2a37b9fd6752f6cc9b8fb7f5b4 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 3 May 2011 07:55:30 +0000 Subject: [PATCH] i82801gx: enable SPI prefetching Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801gx/Kconfig | 5 +++ src/southbridge/intel/i82801gx/bootblock.c | 40 ++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 src/southbridge/intel/i82801gx/bootblock.c diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index f63c12faa..a6bd2026d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -38,5 +38,10 @@ config USBDEBUG_DEFAULT_PORT int default 1 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801gx/bootblock.c" + depends on SOUTHBRIDGE_INTEL_I82801GX + endif diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c new file mode 100644 index 000000000..39b0bd419 --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); +} + -- 2.25.1