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Add support for Intel Sandybridge CPU
[coreboot.git] / src / cpu / intel / model_65x /
2012-01-10 Sven SchnelleMTRR: get physical address size from CPUID tree | commitdiff
2011-08-04 Keith Huicpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. tree | commitdiff
2010-10-18 Stefan Reinauerupdate intel microcode files. tree | commitdiff
2010-10-16 Keith HuiMove support for Deschutes Slot 1 CPUs (model_65x)... tree | commitdiff
my coreboot WIP stuff (asus m5a99x-evo board)