Make MTRR min hole alignment 64MB

This affects the algorithm when determining when to
transform a range into a larger range with a hole.

It is needed when for when I switch on an 8MB TSEG
and cause the memory maps to go crazy.

Also add header defines for the SMRR.

Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02bbb1c9d41ea78433b998c16647c109b9f2..ed7d93bd068b30621a17261ff390df0ec321c3f3 100644 (file)
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
                return reg;
        }
 
-       if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+       if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+           range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
                /*
-                * If this range is not divisible by 16MB then instead
+                * If this range is not divisible then instead
                 * make a larger range and carve out an uncached hole.
                 */
                hole_startk = range_startk + range_sizek;
-               hole_sizek = 0x4000 - (range_sizek % 0x4000);
+               hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
                range_sizek += hole_sizek;
        }
 

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7a3f2dfa387dc607ba3874f5266807363d..8b5cc281bcf0aced6b64c100daafd6432f52208a 100644 (file)
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn          (1 << 11)
 #define MTRRdefTypeFixEn       (1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)