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(parent: dfb3c13) | patch
Artec Group dbe61 mainboard support.
authorMarc Jones <marc.jones@amd.com>
Wed, 20 Jun 2007 23:45:44 +0000 (23:45 +0000)
committerMarc Jones <marc.jones@amd.com>
Wed, 20 Jun 2007 23:45:44 +0000 (23:45 +0000)
commita0aaa752dd69a4454ddc94df1196607c14ea7756
tree9344051b5c8cc105bb0a1792086bad8743395efftree | snapshot
parentdfb3c130d5cdd3a01531c23c3d15e7a1010bf221commit | diff
Artec Group dbe61 mainboard support.
Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/mainboard/artecgroup/dbe61/Config.lb diff | blob | history
src/mainboard/artecgroup/dbe61/Options.lb diff | blob | history
src/mainboard/artecgroup/dbe61/auto.c [deleted file] blob | history
src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/irq_tables.c diff | blob | history
src/mainboard/artecgroup/dbe61/mainboard.c diff | blob | history
src/mainboard/artecgroup/dbe61/spd_table.h [new file with mode: 0644] blob
targets/artecgroup/dbe61/Config.lb diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)