X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Fusb_ehci.c;fp=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Fusb_ehci.c;h=c2995354564ecc1d40ae6e6ea3dc05a30c5d375a;hp=0000000000000000000000000000000000000000;hb=8e073829ec69ee89b3e91f4c040c96988084a526;hpb=cb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3

diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
new file mode 100644
index 000000000..c29953545
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void usb_ehci_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Disable Wake on Disconnect in RMH */
+	reg32 = RCBA32(0x35b0);
+	reg32 |= 0x22;
+	RCBA32(0x35b0) = reg32;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	//reg32 |= PCI_COMMAND_SERR;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+
+	access_cntl = pci_read_config8(dev, 0x80);
+
+	/* Enable writes to protected registers. */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+
+	/* Restore protection. */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static void usb_ehci_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 usb_debug;
+
+	usb_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(usb_debug);
+	if (!res) return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+}
+
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= &usb_ehci_set_subsystem,
+};
+
+static struct device_operations usb_ehci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= usb_ehci_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_ehci_init,
+	.scan_bus		= 0,
+	.ops_pci		= &lops_pci,
+};
+
+static const struct pci_driver pch_usb_ehci1 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c26,
+};
+static const struct pci_driver pch_usb_ehci2 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c2d,
+};
+static const struct pci_driver pch_usb_ehci3 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1e26,
+};
+static const struct pci_driver pch_usb_ehci4 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1e2d,
+};