X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Ffinalize.c;fp=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Ffinalize.c;h=ed1ebf7a9ad2972a2b81a43197940002e6b259e1;hp=0000000000000000000000000000000000000000;hb=8e073829ec69ee89b3e91f4c040c96988084a526;hpb=cb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3

diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
new file mode 100644
index 000000000..ed1ebf7a9
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+#include "pch.h"
+
+void intel_pch_finalize_smm(void)
+{
+	/* Set SPI opcode menu */
+	RCBA16(0x3894) = SPI_OPPREFIX;
+	RCBA16(0x3896) = SPI_OPTYPE;
+	RCBA32(0x3898) = SPI_OPMENU_LOWER;
+	RCBA32(0x389c) = SPI_OPMENU_UPPER;
+
+	/* Lock SPIBAR */
+	RCBA32_OR(0x3804, (1 << 15));
+
+	/* TCLOCKDN: TC Lockdown */
+	RCBA32_OR(0x0050, (1 << 31));
+
+	/* BIOS Interface Lockdown */
+	RCBA32_OR(0x3410, (1 << 0));
+
+	/* Function Disable SUS Well Lockdown */
+	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
+
+	/* Global SMI Lock */
+	pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+
+	/* GEN_PMCON Lock */
+	pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+
+	/* R/WO registers */
+	RCBA32(0x21a4) = RCBA32(0x21a4);
+	pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
+		    pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+}