X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Fbootblock.c;fp=src%2Fsouthbridge%2Fintel%2Fbd82x6x%2Fbootblock.c;h=686e820e0360a4cab091e6015451bedf6b6471b7;hp=0000000000000000000000000000000000000000;hb=8e073829ec69ee89b3e91f4c040c96988084a526;hpb=cb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3

diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
new file mode 100644
index 000000000..686e820e0
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "pch.h"
+
+static void store_initial_timestamp(void)
+{
+	/* On Cougar Point we have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	device_t dev;
+
+	dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	device_t dev = PCI_DEV(0, 0x1f, 0);
+
+	/* Enable port 80 POST on LPC */
+	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+#if 0
+	RCBA32(GCS) &= (~0x04);
+#else
+	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
+	u32 reg32 = *gcs;
+	reg32 = reg32 & ~0x04;
+	*gcs = reg32;
+	post_code(0x01);
+#endif
+}
+
+static void bootblock_southbridge_init(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+	store_initial_timestamp();
+#endif
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+}