X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fsouthbridge%2Famd%2Frs780%2Frs780.c;h=717aeab2c6cef3244f26bf8ba5b6bd152b275bc1;hp=0fea909760f596435e137ec0a0a691e430499f32;hb=2143d3737553b293923ad566ef4cda3aec742f75;hpb=35e912cef3aac245202694736281aa8475e977f1

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 0fea90976..717aeab2c 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -186,7 +186,6 @@ static void rs780_nb_pci_table(device_t nb_dev)
 #endif
 }
 
-#if 0
 static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
 	/* NB_InitGFXStraps */
@@ -273,7 +272,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 
 	printk(BIOS_INFO, "GC is accessible from now on.\n");
 }
-#endif
 
 /***********************************************
 *	0:00.0  NBCFG	:
@@ -327,19 +325,15 @@ void rs780_enable(device_t dev)
 
 	case 1: /* bus0, dev1, APC. */
 		printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
-#if 0
 		rs780_nb_gfx_dev_table(nb_dev, dev);
-#endif
 		break;
 	case 2:		/* bus0, dev2,3, two GFX */
 	case 3:
 		printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
-#if 0
 		if (dev->enabled)
 			rs780_gfx_init(nb_dev, dev, dev_ind);
-#endif
 		break;
 	case 4:		/* bus0, dev4-7, four GPPSB */
 	case 5:
@@ -376,7 +370,6 @@ void rs780_enable(device_t dev)
 	default:
 		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
 	}
-	printk(BIOS_INFO, "rs780_enable: done\n");
 }
 
 struct chip_operations southbridge_amd_rs780_ops = {