X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fcpu%2Fx86%2Fsmm%2Fsmmrelocate.S;fp=src%2Fcpu%2Fx86%2Fsmm%2Fsmmrelocate.S;h=18d668c9dd0cfdd5eb367af7ad600a5a3b63844a;hp=bc5b2da41b5ffb9f029fbbd4c9d526dea7f846c2;hb=8c5b58e7c372d0c1666931040e35fef92ad56c4b;hpb=5c55463f500528b69c47a06da22339fa85d70b7e

diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index bc5b2da41..18d668c9d 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -54,13 +54,22 @@
 .code16
 
 /**
- * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 )
+ * When starting up, x86 CPUs have their SMBASE set to 0x30000. However,
+ * this is not a good place for the SMM handler to live, so it needs to
+ * be relocated.
+ * Traditionally SMM handlers used to live in the A segment (0xa0000).
+ * With growing SMM handlers, more CPU cores, etc. CPU vendors started
+ * allowing to relocate the handler to the end of physical memory, which
+ * they refer to as TSEG.
+ * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 )
  *
  * Why 0x400? It is a safe value to cover the save state area per CPU. On
  * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
  * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
  * bigger, effectively sizing our data structures 0x300 bytes.
  *
+ * Example (with SMM handler living at 0xa0000):
+ *
  * LAPICID	SMBASE		SMM Entry 	SAVE STATE
  *    0		0xa0000		0xa8000		0xafd00
  *    1		0x9fc00		0xa7c00		0xaf900
@@ -88,13 +97,7 @@
  * at 0xa8000-0xa8100 (example for core 0). That is not enough.
  *
  * This means we're basically limited to 16 cpu cores before
- * we need to use the TSEG/HSEG for the actual SMM handler plus stack.
- * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
- *
- * If we figure out the documented values above are safe to use,
- * we could pack the structure above even more, so we could use the
- * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs
- * in the ASEG.
+ * we need to move the SMM handler to TSEG.
  *
  * Note: Some versions of Pentium M need their SMBASE aligned to 32k.
  * On those the above only works for up to 2 cores. But for now we only