X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=blobdiff_plain;f=src%2Fcpu%2Famd%2Fmodel_gx2%2Fcpubug.c;h=473766c8a4109d7653a9fb883d897031210ce459;hp=ff61a30f9aee80aa35dde5c4abf52d60e0415269;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hpb=784544b934d67dc85ccfcf33e04ff148045836ad

diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index ff61a30f9..473766c8a 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -280,7 +280,7 @@ static void bug118339(void)
 
 	/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
 	 * As per Todd Roberts in PBz1094 and PBz1095
-	 * Moved from CPUREG to CPUBUG per Tom Sylla 
+	 * Moved from CPUREG to CPUBUG per Tom Sylla
 	 */
 	msrnum =  0x04C000042;		/*  GLCP SETMCTL Register */
 	msr = rdmsr(msrnum);