superiotool: add detection and dump of Infineon SLB9635 TPM

[coreboot.git] / util / superiotool / superiotool.h

diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index c953038528b4d35f2fcf334efe66f04455bde965..5583ec56697540a6d8f00c86f9bbbee40800f380 100644 (file)
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -33,8 +33,8 @@
 #include <sys/io.h>
 #endif
 #if (defined(__MACH__) && defined(__APPLE__))
-/* DirectIO is available here: http://www.coresystems.de/en/directio */
-#include <DirectIO/darwinio.h>
+/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+#include <DirectHW/DirectHW.h>
 #endif
 
 #ifdef PCI_SUPPORT
@@ -59,6 +59,55 @@
 #define INL  inl
 #endif
 
+#if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__))
+#include <sys/types.h>
+#include <machine/sysarch.h>
+#if defined(__i386__)
+#define iopl i386_iopl
+#elif defined(__x86_64__)
+#define iopl x86_64_iopl
+#endif
+
+static __inline__ void
+outb(uint8_t value, uint16_t port)
+{
+       __asm__ __volatile__ ("outb %b0,%w1": :"a" (value), "Nd" (port));
+}
+
+static __inline__ void
+outw(uint16_t value, uint16_t port)
+{
+       __asm__ __volatile__ ("outw %w0,%w1": :"a" (value), "Nd" (port));
+}
+
+static __inline__ void
+outl(uint32_t value, uint16_t port)
+{
+       __asm__ __volatile__ ("outl %0,%w1": :"a" (value), "Nd" (port));
+}
+
+static __inline__ uint8_t inb(uint16_t port)
+{
+       uint8_t value;
+       __asm__ __volatile__ ("inb %w1,%0":"=a" (value):"Nd" (port));
+       return value;
+}
+
+static __inline__ uint16_t inw(uint16_t port)
+{
+       uint16_t value;
+       __asm__ __volatile__ ("inw %w1,%0":"=a" (value):"Nd" (port));
+       return value;
+}
+
+static __inline__ uint32_t inl(uint16_t port)
+{
+       uint32_t value;
+       __asm__ __volatile__ ("inl %1,%0":"=a" (value):"Nd" (port));
+       return value;
+}
+#endif
+
 #define USAGE "Usage: superiotool [-d] [-e] [-l] [-V] [-v] [-h]\n\n\
   -d | --dump            Dump Super I/O register contents\n\
   -e | --extra-dump      Dump secondary registers too (e.g. EC registers)\n\
@@ -117,6 +166,8 @@ uint8_t regval(uint16_t port, uint8_t reg);
 void regwrite(uint16_t port, uint8_t reg, uint8_t val);
 void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port);
 void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port);
+void enter_conf_mode_fintek_7777(uint16_t port);
+void exit_conf_mode_fintek_7777(uint16_t port);
 int superio_unknown(const struct superio_registers reg_table[], uint16_t id);
 const char *get_superio_name(const struct superio_registers reg_table[],
                             uint16_t id);
@@ -131,10 +182,23 @@ void print_vendor_chips(const char *vendor,
 void probe_idregs_ali(uint16_t port);
 void print_ali_chips(void);
 
+/* amd.c */
+void probe_idregs_amd(uint16_t port);
+void print_amd_chips(void);
+
+/* serverengines.c */
+void probe_idregs_serverengines(uint16_t port);
+void print_serverengines_chips(void);
+
 /* fintek.c */
 void probe_idregs_fintek(uint16_t port);
+void probe_idregs_fintek_alternative(uint16_t port);
 void print_fintek_chips(void);
 
+/* infineon.c */
+void probe_idregs_infineon(uint16_t port);
+void print_infineon_chips(void);
+
 /* ite.c */
 void probe_idregs_ite(uint16_t port);
 void print_ite_chips(void);
@@ -143,6 +207,10 @@ void print_ite_chips(void);
 void probe_idregs_nsc(uint16_t port);
 void print_nsc_chips(void);
 
+/* nuvoton.c */
+void probe_idregs_nuvoton(uint16_t port);
+void print_nuvoton_chips(void);
+
 /* smsc.c */
 void probe_idregs_smsc(uint16_t port);
 void print_smsc_chips(void);
@@ -164,14 +232,22 @@ static const struct {
 } superio_ports_table[] = {
        {probe_idregs_ali,      {0x3f0, 0x370, EOT}},
        {probe_idregs_fintek,   {0x2e, 0x4e, EOT}},
+       {probe_idregs_fintek_alternative,       {0x2e, 0x4e, EOT}},
        /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
-       {probe_idregs_ite,      {0x2e, 0x4e, 0x370, EOT}},
-       {probe_idregs_nsc,      {0x2e, 0x4e, 0x15c, EOT}},
+       {probe_idregs_ite,      {0x25e, 0x2e, 0x4e, 0x370, EOT}},
+       {probe_idregs_nsc,      {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
+       /* I/O pairs on Nuvoton EC chips can be configured by firmware in
+        * addition to the following hardware strapping options. */
+       {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
        {probe_idregs_smsc,     {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
        {probe_idregs_winbond,  {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
 #ifdef PCI_SUPPORT
        {probe_idregs_via,      {0x3f0, EOT}},
+       /* in fact read the BASE from HW */
+       {probe_idregs_amd,      {0xaa, EOT}},
 #endif
+       {probe_idregs_serverengines,    {0x2e, EOT}},
+       {probe_idregs_infineon, {0x2e, 0x4e}},
 };
 
 /** Table of functions to print out supported Super I/O chips. */
@@ -182,11 +258,15 @@ static const struct {
        {print_fintek_chips},
        {print_ite_chips},
        {print_nsc_chips},
+       {print_nuvoton_chips},
        {print_smsc_chips},
        {print_winbond_chips},
 #ifdef PCI_SUPPORT
        {print_via_chips},
+       {print_amd_chips},
 #endif
+       {print_serverengines_chips},
+       {print_infineon_chips},
 };
 
 #endif