inteltool: Add Intel i63xx I/O Controller Hub

[coreboot.git] / util / inteltool / gpio.c

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 6b56ec43a18f89b128c5f0dfa5f8beba45aae056..1d48a6800e51155ffc233227abc19335af3acc2c 100644 (file)
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -203,6 +203,24 @@ static const io_register_t ich10_gpio_registers[] = {
        { 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t i631x_gpio_registers[] = {
+       { 0x00, 4, "GPIO_USE_SEL" },
+       { 0x04, 4, "GP_IO_SEL" },
+       { 0x08, 4, "RESERVED" },
+       { 0x0c, 4, "GP_LVL" },
+       { 0x10, 4, "RESERVED" },
+       { 0x14, 4, "RESERVED" },
+       { 0x18, 4, "GPO_BLINK" },
+       { 0x1c, 4, "RESERVED" },
+       { 0x20, 4, "RESERVED" },
+       { 0x24, 4, "RESERVED" },
+       { 0x28, 4, "RESERVED" },
+       { 0x2c, 4, "GPI_INV" },
+       { 0x30, 4, "GPIO_USE_SEL2" },
+       { 0x34, 4, "GP_IO_SEL2" },
+       { 0x38, 4, "GP_LVL2" },
+};
+
 int print_gpios(struct pci_dev *sb)
 {
        int i, size;
@@ -269,6 +287,13 @@ int print_gpios(struct pci_dev *sb)
                gpio_registers = ich0_gpio_registers;
                size = ARRAY_SIZE(ich0_gpio_registers);
                break;
+
+       case PCI_DEVICE_ID_INTEL_I63XX:
+               gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+               gpio_registers = i631x_gpio_registers;
+               size = ARRAY_SIZE(i631x_gpio_registers);
+               break;
+
        case PCI_DEVICE_ID_INTEL_82371XX:
                printf("This southbridge has GPIOs in the PM unit.\n");
                return 1;