Random Winbond Super I/O cosmetic and coding-style fixes.

[coreboot.git] / src / superio / winbond / w83627uhg / w83627uhg_early_serial.c

diff --git a/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c b/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c
index ea796367267bea41c68de7d890275ae16e37d2e9..3636641f601a3c23e8a2242f5988d1a5523bfe02 100644 (file)
--- a/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c
+++ b/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c
@@ -47,7 +47,7 @@ static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
        pnp_write_config(dev, 0x24, value);
 }
 
-static void w83627uhg_enable_serial(device_t dev, u32 iobase)
+static void w83627uhg_enable_serial(device_t dev, u16 iobase)
 {
        pnp_enter_ext_func_mode(dev);
        pnp_set_logical_device(dev);