C and other Super I/O cosmetic fixes.
[coreboot.git] / src / superio / via / vt1211 / vt1211.c
index 09346fcdaccdfa7e011ead23a75e20a391ba6d95..3cfeea66a418de59ede5a11a31611289d544c2d2 100644 (file)
@@ -205,17 +205,17 @@ struct device_operations ops = {
 
 /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, VT1211_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-       { &ops, VT1211_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-       { &ops, VT1211_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
-       { &ops, VT1211_SP2,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
-       { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, },
-       { &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, },
-       { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-       { &ops, VT1211_WDG,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-       { &ops, VT1211_WUC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-       { &ops, VT1211_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, },
-       { &ops, VT1211_FIR,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, },
+       { &ops, VT1211_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, VT1211_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, VT1211_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, VT1211_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
+       { &ops, VT1211_GAME, PNP_IO0, {0xfff8, 0}, },
+       { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+       { &ops, VT1211_WDG,  PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+       { &ops, VT1211_WUC,  PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+       { &ops, VT1211_HWM,  PNP_IO0 | PNP_IRQ0, {0xff00, 0}, },
+       { &ops, VT1211_FIR,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff00, 0}, },
        { &ops, VT1211_ROM, },
 };