C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / smsc / lpc47b272 / lpc47b272_early_serial.c

diff --git a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
index 0c31b3a9356a46e148ab66229078e3ab698a5629..75093ea0a9bfd0fc59180b3af8722739e93ac7cc 100644 (file)
--- a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
+++ b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
@@ -23,17 +23,15 @@
 #include <arch/romcc_io.h>
 #include "lpc47b272.h"
 
-/** Enable access to the LPC47B272's configuration registers. */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
 {
-       unsigned port = dev>>8;
+       u16 port = dev >> 8;
        outb(0x55, port);
 }
 
-/** Disable access to the LPC47B272's configuration registers. */
 static void pnp_exit_conf_state(device_t dev)
 {
-       unsigned port = dev>>8;
+       u16 port = dev >> 8;
        outb(0xaa, port);
 }
 
@@ -44,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev)
  * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
  * @param iobase Processor I/O port address to assign to this serial device.
  */
-static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
+static void lpc47b272_enable_serial(device_t dev, u16 iobase)
 {
        pnp_enter_conf_state(dev);
        pnp_set_logical_device(dev);