C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / nsc / pc87366 / superio.c

diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c
index a38f386d60c63ff68cc0f294b6e5be63489c9b74..af8f8993a2fdb8b1fcfeeb0690369477698facb3 100644 (file)
--- a/src/superio/nsc/pc87366/superio.c
+++ b/src/superio/nsc/pc87366/superio.c
@@ -33,15 +33,12 @@
 
 static void init(device_t dev)
 {
-       struct superio_nsc_pc87366_config *conf;
+       struct superio_nsc_pc87366_config *conf = dev->chip_info;
        struct resource *res0;
-       /* Wishlist handle well known programming interfaces more
-        * generically.
-        */
-       if (!dev->enabled) {
+
+       if (!dev->enabled)
                return;
-       }
-       conf = dev->chip_info;
+
        switch(dev->path.pnp.device) {
        case PC87366_SP1:
                res0 = find_resource(dev, PNP_IDX_IO0);
@@ -66,17 +63,17 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, PC87366_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
-       { &ops, PC87366_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
-       { &ops, PC87366_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
-       { &ops, PC87366_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, PC87366_SWC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-       { &ops, PC87366_KBCM, PNP_IRQ0 },
-       { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
-       { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
-       { &ops, PC87366_ACB,  PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
-       { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
-       { &ops, PC87366_WDT,  PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } },
+       { &ops, PC87366_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
+       { &ops, PC87366_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
+       { &ops, PC87366_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
+       { &ops, PC87366_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, PC87366_SWC,  PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+       { &ops, PC87366_KBCM, PNP_IRQ0, },
+       { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
+       { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
+       { &ops, PC87366_ACB,  PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
+       { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
+       { &ops, PC87366_WDT,  PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
 };
 
 static void enable_dev(struct device *dev)