Random ITE Super I/O fixes.

[coreboot.git] / src / superio / ite / it8712f / it8712f_early_serial.c

diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c
index 76f9bc0d078a496f3736f9e128eee96b5af1ebac..ebc8e0a7f1dea753182250dde7783d81f862b68e 100644 (file)
--- a/src/superio/ite/it8712f/it8712f_early_serial.c
+++ b/src/superio/ite/it8712f/it8712f_early_serial.c
@@ -24,7 +24,7 @@
 /* The base address is 0x2e or 0x4e, depending on config bytes. */
 #define SIO_BASE                     0x2e
 #define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     SIO_BASE+1
+#define SIO_DATA                     (SIO_BASE + 1)
 
 /* Global configuration registers. */
 #define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
@@ -35,11 +35,7 @@
 #define IT8712F_CONFIG_REG_MFC       0x2a /* Multi-function control */
 #define IT8712F_CONFIG_REG_WATCHDOG  0x72 /* Watchdog control. */
 
-#define IT8712F_CONFIGURATION_PORT   0x2e /* Write-only. */
-
-/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
-   LDN the register belongs to, before you can access the register. */
-static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
 {
        outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
        outb(ldn, SIO_DATA);
@@ -49,75 +45,69 @@ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 
 static void it8712f_enter_conf(void)
 {
-       /*  Enter the configuration state (MB PnP mode). */
-
-       /* Perform MB PnP setup to put the SIO chip at 0x2e. */
-       /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
-       /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
-       outb(0x87, IT8712F_CONFIGURATION_PORT);
-       outb(0x01, IT8712F_CONFIGURATION_PORT);
-       outb(0x55, IT8712F_CONFIGURATION_PORT);
-       outb(0x55, IT8712F_CONFIGURATION_PORT);
+       u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+       outb(0x87, port);
+       outb(0x01, port);
+       outb(0x55, port);
+       outb((port == 0x4e) ? 0xaa : 0x55, port);
 }
 
 static void it8712f_exit_conf(void)
 {
-       /* Exit the configuration state (MB PnP mode). */
        it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
 }
 
+/* Select 24MHz CLKIN (48MHz is the default). */
 void it8712f_24mhz_clkin(void)
 {
        it8712f_enter_conf();
-
-       /* Select 24MHz CLKIN (48MHZ default)*/
        it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
-
        it8712f_exit_conf();
 }
 
+/*
+ * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
+ *
+ * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
+ *
+ * Enable 3VSBSW#. (For System Suspend-to-RAM)
+ * 0: 3VSBSW# will be always inactive.
+ * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
+ */
 void it8712f_enable_3vsbsw(void)
 {
-
-       /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
-        LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
-        Enable 3VSBSW#. (For System Suspend-to-RAM)
-        0: 3VSBSW# will be always inactive.
-        1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
-       */
-
        it8712f_enter_conf();
-       it8712f_sio_write(0x07, IT8712F_CONFIG_REG_MFC, 0x80);
+       it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
        it8712f_exit_conf();
 }
 
 void it8712f_kill_watchdog(void)
 {
        it8712f_enter_conf();
-
-       /* Kill the Watchdog */
-       it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
-
+       it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
        it8712f_exit_conf();
 }
 
-/* Enable the peripheral devices on the IT8712F Super I/O chip. */
-void it8712f_enable_serial(device_t dev, unsigned iobase)
+/* Enable the serial port(s). */
+void it8712f_enable_serial(device_t dev, u16 iobase)
 {
-
        /* (1) Enter the configuration state (MB PnP mode). */
        it8712f_enter_conf();
 
        /* (2) Modify the data of configuration registers. */
 
-       /* Select the chip to configure (if there's more than one).
-          Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-          If this register is not written, both chips are configured. */
+       /*
+        * Select the chip to configure (if there's more than one).
+        * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+        * If this register is not written, both chips are configured.
+        */
+
        /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
 
        /* Enable serial port(s). */
-       it8712f_sio_write(IT8712F_SP1,  0x30, 0x1); /* Serial port 1 */
-       it8712f_sio_write(IT8712F_SP2,  0x30, 0x1); /* Serial port 2 */
+       it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
+       it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
 
        /* Clear software suspend mode (clear bit 0). TODO: Needed? */
        /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */