remove trailing whitespace

[coreboot.git] / src / southbridge / via / vt8237r / lpc.c

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 72b85b37d5ea274df56338d77d5851cfaa6533b6..e59951702f00094fb5c5b5ba8820438e35991d02 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -28,9 +28,11 @@
 #include <pc80/mc146818rtc.h>
 #include <arch/ioapic.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/cpu.h>
 #include <pc80/keyboard.h>
 #include <pc80/i8259.h>
 #include <stdlib.h>
+#include <arch/acpi.h>
 #include "vt8237r.h"
 #include "chip.h"
 
@@ -146,9 +148,6 @@ static void pci_routing_fixup(struct device *dev)
  * This avoids having to handle any System Management Interrupts (SMIs).
  */
 
-extern u8 acpi_slp_type;
-
-
 static void setup_pm(device_t dev)
 {
        u16 tmp;
@@ -217,11 +216,8 @@ static void setup_pm(device_t dev)
        /* Disable SMI on GPIO. */
        outw(0x0, VT8237R_ACPI_IO_BASE + 0x24);
 
-       /* Disable all global enable SMIs. */
-       outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a);
-
-       /* All SMI off, both IDE buses ON, PSON rising edge. */
-       outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c);
+       /* Disable all global enable SMIs, except SW SMI */
+       outw(0x40, VT8237R_ACPI_IO_BASE + 0x2a);
 
        /* Primary activity SMI disable. */
        outl(0x0, VT8237R_ACPI_IO_BASE + 0x34);
@@ -238,6 +234,10 @@ static void setup_pm(device_t dev)
        acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
        printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 #endif
+
+       /* All SMI on, both IDE buses ON, PSON rising edge. */
+       outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
+
        /* clear sleep */
        tmp &= ~(7 << 10);
        tmp |= 1;
@@ -297,11 +297,20 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x0c);
 #else
+
+  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+       /* It seems that when we pair with the K8T800, we need to disable
+        * the A2 mask
+        */
+       pci_write_config8(dev, 0x48, 0x0c);
+  #else
        /*
         * Set Read Pass Write Control Enable
         * (force A2 from APIC FSB to low).
         */
        pci_write_config8(dev, 0x48, 0x8c);
+  #endif
+
 #endif
 
        southbridge_init_common(dev);
@@ -317,6 +326,8 @@ static void vt8237r_init(struct device *dev)
 #endif
 
        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
+       printk(BIOS_SPEW, "And taking a dump:\n");
+       dump_south(dev);
 }
 
 static void vt8237a_init(struct device *dev)
@@ -467,6 +478,7 @@ static void vt8237_common_init(struct device *dev)
         * Bit | Meaning
         * -------------
         *   3 | Bypass APIC De-Assert Message (1=Enable)
+        *   2 | APIC HyperTransport Mode (1=Enable)
         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
@@ -483,12 +495,13 @@ static void vt8237_common_init(struct device *dev)
        pci_write_config8(dev, 0x4c, 0x44);
 
        /* ROM memory cycles go to LPC. */
-       pci_write_config8(dev, 0x59, 0x80);
+       pci_write_config8(dev, 0x59, 0x80);
 
        /*
         * Bit | Meaning
         * -------------
         *   3 | Bypass APIC De-Assert Message (1=Enable)
+        *   2 | APIC HyperTransport Mode (1=Enable)
         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
@@ -500,7 +513,9 @@ static void vt8237_common_init(struct device *dev)
 
        /* Enable serial IRQ, 6PCI clocks. */
        pci_write_config8(dev, 0x52, 0x9);
-
+#endif
+#if CONFIG_HAVE_SMI_HANDLER
+       smm_lock();
 #endif
 
        /* Power management setup */