remove trailing whitespace

[coreboot.git] / src / southbridge / via / vt8237r / lpc.c

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3ffc377572b614d72b8e837b433e58632fefe044..e59951702f00094fb5c5b5ba8820438e35991d02 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -32,6 +32,7 @@
 #include <pc80/keyboard.h>
 #include <pc80/i8259.h>
 #include <stdlib.h>
+#include <arch/acpi.h>
 #include "vt8237r.h"
 #include "chip.h"
 
@@ -147,9 +148,6 @@ static void pci_routing_fixup(struct device *dev)
  * This avoids having to handle any System Management Interrupts (SMIs).
  */
 
-extern u8 acpi_slp_type;
-
-
 static void setup_pm(device_t dev)
 {
        u16 tmp;
@@ -299,11 +297,20 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x0c);
 #else
+
+  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+       /* It seems that when we pair with the K8T800, we need to disable
+        * the A2 mask
+        */
+       pci_write_config8(dev, 0x48, 0x0c);
+  #else
        /*
         * Set Read Pass Write Control Enable
         * (force A2 from APIC FSB to low).
         */
        pci_write_config8(dev, 0x48, 0x8c);
+  #endif
+
 #endif
 
        southbridge_init_common(dev);
@@ -319,6 +326,8 @@ static void vt8237r_init(struct device *dev)
 #endif
 
        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
+       printk(BIOS_SPEW, "And taking a dump:\n");
+       dump_south(dev);
 }
 
 static void vt8237a_init(struct device *dev)
@@ -469,6 +478,7 @@ static void vt8237_common_init(struct device *dev)
         * Bit | Meaning
         * -------------
         *   3 | Bypass APIC De-Assert Message (1=Enable)
+        *   2 | APIC HyperTransport Mode (1=Enable)
         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
@@ -485,12 +495,13 @@ static void vt8237_common_init(struct device *dev)
        pci_write_config8(dev, 0x4c, 0x44);
 
        /* ROM memory cycles go to LPC. */
-       pci_write_config8(dev, 0x59, 0x80);
+       pci_write_config8(dev, 0x59, 0x80);
 
        /*
         * Bit | Meaning
         * -------------
         *   3 | Bypass APIC De-Assert Message (1=Enable)
+        *   2 | APIC HyperTransport Mode (1=Enable)
         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)