Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c

[coreboot.git] / src / southbridge / via / vt8231 / vt8231_lpc.c

diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
index a063adf710adadf17d6b6fcef73226c059065c96..40854dbcf7b091958e18b9765fe78e4a3fef0d94 100644 (file)
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/vt8231_lpc.c
@@ -61,9 +61,6 @@ static void vt8231_init(struct device *dev)
        enables |= 0x80;
        pci_write_config8(dev, 0x6C, enables);
 
-       // Map 4MB of FLASH into the address space
-       pci_write_config8(dev, 0x41, 0x7f);
-
        // Set bit 6 of 0x40, because Award does it (IO recovery time)
        // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
        // interrupts can be properly marked as level triggered.