In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.

[coreboot.git] / src / southbridge / intel / i82371eb / i82371eb.h

diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 7b8cce0e3863c7624c1f5aed9863634a468b69c9..3b461b5365f99d816846c94d2c9fef24808cb364 100644 (file)
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
  *
@@ -21,9 +21,25 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
-#ifndef __ROMCC__
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
+#if !defined(__ACPI__) /* dsdt include */
+
+#include <arch/io.h>
+#include <device/device.h>
 #include "chip.h"
+
 void i82371eb_enable(device_t dev);
+void i82371eb_hard_reset(void);
+
+#endif
+#endif
+#endif
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+void enable_pm(void);
 #endif
 
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
@@ -48,10 +64,59 @@ void i82371eb_enable(device_t dev);
 
 /* SMBus */
 #define SMBBA          0x90    /* SMBus base address */
+#define   SMBUS_IO_BASE        0x0f00
 #define SMBHSTCFG      0xd2    /* SMBus host configuration */
 
 /* Power management (ACPI) */
+#define PMSTS          0x00    /* Power Management Status */
+#define PMEN           0x02    /* Power Management Resume Enable */
+#define   PWRBTN_EN    (1<<8)
+#define   GBL_EN       (1<<5)
+#define PMCNTRL                0x04    /* Power Management Control */
+#define   SUS_EN       (1<<13) /* S0-S5 trigger */
+#define   SUS_TYP_MSK  (7<<10)
+#define   SUS_TYP_S0   (5<<10)
+#define   SUS_TYP_S1   (4<<10)
+#define   SUS_TYP_S2   (3<<10)
+//#define   SUS_TYP_S2>---(2<<10)
+#define   SUS_TYP_S3   (1<<10)
+#define   SUS_TYP_S5   (0<<10)
+#define   SCI_EN       (1<<0)
+#define PMTMR          0x08    /* Power Management Timer */
+#define GPSTS          0x0c    /* General Purpose Status */
+#define GPEN           0x0e    /* General Purpose Enable */
+#define   THRM_EN      (1<<0)
+#define PCNTRL         0x10    /* Processor control */
+#define GLBSTS         0x18    /* Global Status */
+#define   IRQ_RSM_STS  (1<<11)
+#define   EXTSMI_STS   (1<<10)
+#define   GSTBY_STS    (1<<8)
+#define   GP_STS       (1<<7)
+#define   BM1_STS      (1<<6)
+#define   APM_STS      (1<<5)
+#define   DEV_STS      (1<<4)
+#define   BIOS_EN      (1<<1)  /* GBL_RLS write triggers SMI */
+#define   LEGACY_USB_EN        (1<<0)  /* Keyboard controller access triggers SMI */
+#define DEVSTS         0x1c    /* Device Status */
+#define GLBEN          0x20    /* Global Enable */
+#define   EXTSMI_EN    (1<<10) /* EXTSMI# signal triggers SMI */
+#define   GSTBY_EN     (1<<8)
+#define   BM_TRP_EN    (1<<1)
+#define   BIOS_EN      (1<<1)  /* GBL_RLS write triggers SMI */
+#define   LEGACY_USB_EN        (1<<0)  /* Keyboard controller access triggers SMI */
+#define GLBCTL         0x28    /* Global Control */
+#define   EOS          (1<<16) /* End of SMI */
+#define   SMI_EN       (1<<0)  /* SMI enable */
+#define DEVCTL         0x2c    /* Device Control */
+#define   TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */
+#define GPO0           0x34
+#define GPO1           0x35
+#define GPO2           0x36
+#define GPO3           0x37
+
 #define PMBA           0x40    /* Power management base address */
+#define   DEFAULT_PMBASE       0xe400
+#define   PM_IO_BASE DEFAULT_PMBASE
 #define PMREGMISC      0x80    /* Miscellaneous power management */
 
 /* Bit definitions */
@@ -71,5 +136,6 @@ void i82371eb_enable(device_t dev);
 #define SSDE1                  (1 << 3)  /* Secondary Drive 1 UDMA/33 */
 #define ISA                    (1 << 0)  /* Select ISA */
 #define EIO                    (0 << 0)  /* Select EIO */
+#define PMIOSE                 (1 << 0)  /* PM I/O Space Enable */
 
 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */