}
/* This function can be overloaded in mainboard.c */
-void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev)
+void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev)
{
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
pci_write_config16(dev, 0x86, 0x2c00);
device_t sm_dev;
/* SATA SMBus Disable */
- /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- /* Disable SATA SMBUS */
- byte = pci_read_config8(sm_dev, 0xad);
- byte |= (1 << 1);
- /* Enable SATA and power saving */
+
byte = pci_read_config8(sm_dev, 0xad);
+ /* Disable SATA SMBUS */
byte |= (1 << 0);
+ /* Enable SATA and power saving */
+ byte |= (1 << 1);
byte |= (1 << 5);
pci_write_config8(sm_dev, 0xad, byte);
/* Program the watchdog counter to 0x10 */
byte = 0x10;
pci_write_config8(dev, 0x46, byte);
- sb700_setup_sata_phys(dev);
+ sb7xx_51xx_setup_sata_phys(dev);
/* Enable the I/O, MM, BusMaster access for SATA */
byte = pci_read_config8(dev, 0x4);
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+ /* Master Latency Timer */
+ pci_write_config32(dev, 0xC, 0x00004000);
+#endif
+
/* RPR7.7 SATA drive detection. */
/* Use BAR5+0x128,BAR0 for Primary Slave */
/* Use BAR5+0x1A8,BAR0 for Primary Slave */
}
static struct pci_operations lops_pci = {
- /* .set_subsystem = pci_dev_set_subsystem, */
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {